source: rtems/cpukit/score/cpu/lm32/rtems/score/cpu.h @ 27bfcd8

5
Last change on this file since 27bfcd8 was 27bfcd8, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 25, 2017 at 1:32:02 PM

score: Delete _CPU_Context_Fp_start()

Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().

Close #1400.

  • Property mode set to 100644
File size: 31.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief LM32 CPU Department Source
5 *
6 * This include file contains information pertaining to the LM32
7 * processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2008.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/lm32.h>
28
29/* conditional compilation parameters */
30
31/**
32 * Does RTEMS manage a dedicated interrupt stack in software?
33 *
34 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
35 * If FALSE, nothing is done.
36 *
37 * If the CPU supports a dedicated interrupt stack in hardware,
38 * then it is generally the responsibility of the BSP to allocate it
39 * and set it up.
40 *
41 * If the CPU does not support a dedicated interrupt stack, then
42 * the porter has two options: (1) execute interrupts on the
43 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
44 * interrupt stack.
45 *
46 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
47 *
48 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
49 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
50 * possible that both are FALSE for a particular CPU.  Although it
51 * is unclear what that would imply about the interrupt processing
52 * procedure on that CPU.
53 *
54 * Port Specific Information:
55 *
56 * XXX document implementation including references if appropriate
57 */
58#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
59
60/**
61 * Does the CPU follow the simple vectored interrupt model?
62 *
63 * If TRUE, then RTEMS allocates the vector table it internally manages.
64 * If FALSE, then the BSP is assumed to allocate and manage the vector
65 * table
66 *
67 * Port Specific Information:
68 *
69 * XXX document implementation including references if appropriate
70 */
71#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
72
73/**
74 * Does this CPU have hardware support for a dedicated interrupt stack?
75 *
76 * If TRUE, then it must be installed during initialization.
77 * If FALSE, then no installation is performed.
78 *
79 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
80 *
81 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
82 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
83 * possible that both are FALSE for a particular CPU.  Although it
84 * is unclear what that would imply about the interrupt processing
85 * procedure on that CPU.
86 *
87 * Port Specific Information:
88 *
89 * XXX document implementation including references if appropriate
90 */
91#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
92
93/**
94 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
95 *
96 * If TRUE, then the memory is allocated during initialization.
97 * If FALSE, then the memory is allocated during initialization.
98 *
99 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
100 *
101 * Port Specific Information:
102 *
103 * XXX document implementation including references if appropriate
104 */
105#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
106
107/**
108 * Does the RTEMS invoke the user's ISR with the vector number and
109 * a pointer to the saved interrupt frame (1) or just the vector
110 * number (0)?
111 *
112 * Port Specific Information:
113 *
114 * XXX document implementation including references if appropriate
115 */
116#define CPU_ISR_PASSES_FRAME_POINTER TRUE
117
118/**
119 * @def CPU_HARDWARE_FP
120 *
121 * Does the CPU have hardware floating point?
122 *
123 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
124 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
125 *
126 * If there is a FP coprocessor such as the i387 or mc68881, then
127 * the answer is TRUE.
128 *
129 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
130 * It indicates whether or not this CPU model has FP support.  For
131 * example, it would be possible to have an i386_nofp CPU model
132 * which set this to false to indicate that you have an i386 without
133 * an i387 and wish to leave floating point support out of RTEMS.
134 */
135
136/**
137 * @def CPU_SOFTWARE_FP
138 *
139 * Does the CPU have no hardware floating point and GCC provides a
140 * software floating point implementation which must be context
141 * switched?
142 *
143 * This feature conditional is used to indicate whether or not there
144 * is software implemented floating point that must be context
145 * switched.  The determination of whether or not this applies
146 * is very tool specific and the state saved/restored is also
147 * compiler specific.
148 *
149 * Port Specific Information:
150 *
151 * XXX document implementation including references if appropriate
152 */
153#define CPU_HARDWARE_FP     FALSE
154#define CPU_SOFTWARE_FP     FALSE
155
156/**
157 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
158 *
159 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
160 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
161 *
162 * So far, the only CPUs in which this option has been used are the
163 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
164 * gcc both implicitly used the floating point registers to perform
165 * integer multiplies.  Similarly, the PowerPC port of gcc has been
166 * seen to allocate floating point local variables and touch the FPU
167 * even when the flow through a subroutine (like vfprintf()) might
168 * not use floating point formats.
169 *
170 * If a function which you would not think utilize the FP unit DOES,
171 * then one can not easily predict which tasks will use the FP hardware.
172 * In this case, this option should be TRUE.
173 *
174 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
175 *
176 * Port Specific Information:
177 *
178 * XXX document implementation including references if appropriate
179 */
180#define CPU_ALL_TASKS_ARE_FP     FALSE
181
182/**
183 * Should the IDLE task have a floating point context?
184 *
185 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
186 * and it has a floating point context which is switched in and out.
187 * If FALSE, then the IDLE task does not have a floating point context.
188 *
189 * Setting this to TRUE negatively impacts the time required to preempt
190 * the IDLE task from an interrupt because the floating point context
191 * must be saved as part of the preemption.
192 *
193 * Port Specific Information:
194 *
195 * XXX document implementation including references if appropriate
196 */
197#define CPU_IDLE_TASK_IS_FP      FALSE
198
199/**
200 * Should the saving of the floating point registers be deferred
201 * until a context switch is made to another different floating point
202 * task?
203 *
204 * If TRUE, then the floating point context will not be stored until
205 * necessary.  It will remain in the floating point registers and not
206 * disturned until another floating point task is switched to.
207 *
208 * If FALSE, then the floating point context is saved when a floating
209 * point task is switched out and restored when the next floating point
210 * task is restored.  The state of the floating point registers between
211 * those two operations is not specified.
212 *
213 * If the floating point context does NOT have to be saved as part of
214 * interrupt dispatching, then it should be safe to set this to TRUE.
215 *
216 * Setting this flag to TRUE results in using a different algorithm
217 * for deciding when to save and restore the floating point context.
218 * The deferred FP switch algorithm minimizes the number of times
219 * the FP context is saved and restored.  The FP context is not saved
220 * until a context switch is made to another, different FP task.
221 * Thus in a system with only one FP task, the FP context will never
222 * be saved or restored.
223 *
224 * Port Specific Information:
225 *
226 * XXX document implementation including references if appropriate
227 */
228#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
229
230#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
231
232/**
233 * Does this port provide a CPU dependent IDLE task implementation?
234 *
235 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
236 * must be provided and is the default IDLE thread body instead of
237 * @ref _CPU_Thread_Idle_body.
238 *
239 * If FALSE, then use the generic IDLE thread body if the BSP does
240 * not provide one.
241 *
242 * This is intended to allow for supporting processors which have
243 * a low power or idle mode.  When the IDLE thread is executed, then
244 * the CPU can be powered down.
245 *
246 * The order of precedence for selecting the IDLE thread body is:
247 *
248 *   -#  BSP provided
249 *   -#  CPU dependent (if provided)
250 *   -#  generic (if no BSP and no CPU dependent)
251 *
252 * Port Specific Information:
253 *
254 * XXX document implementation including references if appropriate
255 */
256#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
257
258/**
259 * Does the stack grow up (toward higher addresses) or down
260 * (toward lower addresses)?
261 *
262 * If TRUE, then the grows upward.
263 * If FALSE, then the grows toward smaller addresses.
264 *
265 * Port Specific Information:
266 *
267 * XXX document implementation including references if appropriate
268 */
269#define CPU_STACK_GROWS_UP               FALSE
270
271/* L2 cache lines are 32 bytes in Milkymist SoC */
272#define CPU_CACHE_LINE_BYTES 32
273
274#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
275
276/**
277 * @ingroup CPUInterrupt
278 * The following defines the number of bits actually used in the
279 * interrupt field of the task mode.  How those bits map to the
280 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
281 *
282 * Port Specific Information:
283 *
284 * XXX document implementation including references if appropriate
285 */
286#define CPU_MODES_INTERRUPT_MASK   0x00000001
287
288#define CPU_MAXIMUM_PROCESSORS 32
289
290/*
291 *  Processor defined structures required for cpukit/score.
292 *
293 *  Port Specific Information:
294 *
295 *  XXX document implementation including references if appropriate
296 */
297
298/* may need to put some structures here.  */
299
300/**
301 * @defgroup CPUContext Processor Dependent Context Management
302 *
303 * From the highest level viewpoint, there are 2 types of context to save.
304 *
305 *    -# Interrupt registers to save
306 *    -# Task level registers to save
307 *
308 * Since RTEMS handles integer and floating point contexts separately, this
309 * means we have the following 3 context items:
310 *
311 *    -# task level context stuff::  Context_Control
312 *    -# floating point task stuff:: Context_Control_fp
313 *    -# special interrupt level context :: CPU_Interrupt_frame
314 *
315 * On some processors, it is cost-effective to save only the callee
316 * preserved registers during a task context switch.  This means
317 * that the ISR code needs to save those registers which do not
318 * persist across function calls.  It is not mandatory to make this
319 * distinctions between the caller/callee saves registers for the
320 * purpose of minimizing context saved during task switch and on interrupts.
321 * If the cost of saving extra registers is minimal, simplicity is the
322 * choice.  Save the same context on interrupt entry as for tasks in
323 * this case.
324 *
325 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
326 * care should be used in designing the context area.
327 *
328 * On some CPUs with hardware floating point support, the Context_Control_fp
329 * structure will not be used or it simply consist of an array of a
330 * fixed number of bytes.   This is done when the floating point context
331 * is dumped by a "FP save context" type instruction and the format
332 * is not really defined by the CPU.  In this case, there is no need
333 * to figure out the exact format -- only the size.  Of course, although
334 * this is enough information for RTEMS, it is probably not enough for
335 * a debugger such as gdb.  But that is another problem.
336 *
337 * Port Specific Information:
338 *
339 * XXX document implementation including references if appropriate
340 */
341/**@{**/
342
343/**
344 * This defines the minimal set of integer and processor state registers
345 * that must be saved during a voluntary context switch from one thread
346 * to another.
347 */
348typedef struct {
349  uint32_t r11;
350  uint32_t r12;
351  uint32_t r13;
352  uint32_t r14;
353  uint32_t r15;
354  uint32_t r16;
355  uint32_t r17;
356  uint32_t r18;
357  uint32_t r19;
358  uint32_t r20;
359  uint32_t r21;
360  uint32_t r22;
361  uint32_t r23;
362  uint32_t r24;
363  uint32_t r25;
364  uint32_t gp;
365  uint32_t fp;
366  uint32_t sp;
367  uint32_t ra;
368  uint32_t ie;
369  uint32_t epc;
370} Context_Control;
371
372/**
373 *
374 * This macro returns the stack pointer associated with @a _context.
375 *
376 * @param[in] _context is the thread context area to access
377 *
378 * @return This method returns the stack pointer.
379 */
380#define _CPU_Context_Get_SP( _context ) \
381  (_context)->sp
382
383/**
384 * This defines the complete set of floating point registers that must
385 * be saved during any context switch from one thread to another.
386 */
387typedef struct {
388} Context_Control_fp;
389
390/**
391 * This defines the set of integer and processor state registers that must
392 * be saved during an interrupt.  This set does not include any which are
393 * in @ref Context_Control.
394 */
395typedef struct {
396  uint32_t r1;
397  uint32_t r2;
398  uint32_t r3;
399  uint32_t r4;
400  uint32_t r5;
401  uint32_t r6;
402  uint32_t r7;
403  uint32_t r8;
404  uint32_t r9;
405  uint32_t r10;
406  uint32_t ra;
407  uint32_t ba;
408  uint32_t ea;
409} CPU_Interrupt_frame;
410
411/**
412 * This variable is optional.  It is used on CPUs on which it is difficult
413 * to generate an "uninitialized" FP context.  It is filled in by
414 * @ref _CPU_Initialize and copied into the task's FP context area during
415 * @ref _CPU_Context_Initialize.
416 *
417 * Port Specific Information:
418 *
419 * XXX document implementation including references if appropriate
420 */
421#if 0
422extern Context_Control_fp _CPU_Null_fp_context;
423#endif
424
425/** @} */
426
427/**
428 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
429 *
430 * On some CPUs, RTEMS supports a software managed interrupt stack.
431 * This stack is allocated by the Interrupt Manager and the switch
432 * is performed in @ref _ISR_Handler.  These variables contain pointers
433 * to the lowest and highest addresses in the chunk of memory allocated
434 * for the interrupt stack.  Since it is unknown whether the stack
435 * grows up or down (in general), this give the CPU dependent
436 * code the option of picking the version it wants to use.
437 *
438 * NOTE: These two variables are required if the macro
439 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
440 *
441 * Port Specific Information:
442 *
443 * XXX document implementation including references if appropriate
444 */
445/**@{**/
446
447/*
448 * Nothing prevents the porter from declaring more CPU specific variables.
449 *
450 * Port Specific Information:
451 *
452 * XXX document implementation including references if appropriate
453 */
454
455/* XXX: if needed, put more variables here */
456
457/**
458 * @ingroup CPUContext
459 * The size of the floating point context area.  On some CPUs this
460 * will not be a "sizeof" because the format of the floating point
461 * area is not defined -- only the size is.  This is usually on
462 * CPUs with a "floating point save context" instruction.
463 *
464 * Port Specific Information:
465 *
466 * XXX document implementation including references if appropriate
467 */
468#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
469
470/**
471 * Amount of extra stack (above minimum stack size) required by
472 * MPCI receive server thread.  Remember that in a multiprocessor
473 * system this thread must exist and be able to process all directives.
474 *
475 * Port Specific Information:
476 *
477 * XXX document implementation including references if appropriate
478 */
479#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
480
481/**
482 * This defines the number of entries in the @ref _ISR_Vector_table managed
483 * by RTEMS.
484 *
485 * Port Specific Information:
486 *
487 * XXX document implementation including references if appropriate
488 */
489#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
490
491/**
492 * This defines the highest interrupt vector number for this port.
493 */
494#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
495
496/**
497 * This is defined if the port has a special way to report the ISR nesting
498 * level.  Most ports maintain the variable @a _ISR_Nest_level.
499 */
500#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
501
502/** @} */
503
504/**
505 * @ingroup CPUContext
506 * Should be large enough to run all RTEMS tests.  This ensures
507 * that a "reasonable" small application should not have any problems.
508 *
509 * Port Specific Information:
510 *
511 * XXX document implementation including references if appropriate
512 */
513#define CPU_STACK_MINIMUM_SIZE          (1024*4)
514
515#define CPU_SIZEOF_POINTER 4
516
517/**
518 * CPU's worst alignment requirement for data types on a byte boundary.  This
519 * alignment does not take into account the requirements for the stack.
520 *
521 * Port Specific Information:
522 * The LM32 architecture manual simply states: "All memory accesses must be
523 * aligned to the size of the access", and there is no hardware support
524 * whatsoever for 64-bit numbers.
525 * (lm32_archman.pdf, July 2009, p. 15)
526 */
527#define CPU_ALIGNMENT              4
528
529/**
530 * This number corresponds to the byte alignment requirement for the
531 * heap handler.  This alignment requirement may be stricter than that
532 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
533 * common for the heap to follow the same alignment requirement as
534 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
535 * the heap, then this should be set to @ref CPU_ALIGNMENT.
536 *
537 * NOTE:  This does not have to be a power of 2 although it should be
538 *        a multiple of 2 greater than or equal to 2.  The requirement
539 *        to be a multiple of 2 is because the heap uses the least
540 *        significant field of the front and back flags to indicate
541 *        that a block is in use or free.  So you do not want any odd
542 *        length blocks really putting length data in that bit.
543 *
544 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
545 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
546 *        elements allocated from the heap meet all restrictions.
547 *
548 * Port Specific Information:
549 *
550 * XXX document implementation including references if appropriate
551 */
552#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
553
554/**
555 * This number corresponds to the byte alignment requirement for memory
556 * buffers allocated by the partition manager.  This alignment requirement
557 * may be stricter than that for the data types alignment specified by
558 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
559 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
560 * strict enough for the partition, then this should be set to
561 * @ref CPU_ALIGNMENT.
562 *
563 * NOTE:  This does not have to be a power of 2.  It does have to
564 *        be greater or equal to than @ref CPU_ALIGNMENT.
565 *
566 * Port Specific Information:
567 *
568 * XXX document implementation including references if appropriate
569 */
570#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
571
572/**
573 * This number corresponds to the byte alignment requirement for the
574 * stack.  This alignment requirement may be stricter than that for the
575 * data types alignment specified by @ref CPU_ALIGNMENT.
576 *
577 *
578 * Port Specific Information:
579 *
580 * Stack is software-managed
581 */
582#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
583
584/*
585 *  ISR handler macros
586 */
587
588/**
589 * @addtogroup CPUInterrupt
590 */
591/**@{**/
592
593/**
594 * Support routine to initialize the RTEMS vector table after it is allocated.
595 *
596 * Port Specific Information:
597 *
598 * XXX document implementation including references if appropriate
599 */
600#define _CPU_Initialize_vectors()
601
602/**
603 * Disable all interrupts for an RTEMS critical section.  The previous
604 * level is returned in @a _isr_cookie.
605 *
606 * @param[out] _isr_cookie will contain the previous level cookie
607 *
608 * Port Specific Information:
609 *
610 * XXX document implementation including references if appropriate
611 */
612#define _CPU_ISR_Disable( _isr_cookie ) \
613  lm32_disable_interrupts( _isr_cookie );
614
615/**
616 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
617 * This indicates the end of an RTEMS critical section.  The parameter
618 * @a _isr_cookie is not modified.
619 *
620 * @param[in] _isr_cookie contain the previous level cookie
621 *
622 * Port Specific Information:
623 *
624 * XXX document implementation including references if appropriate
625 */
626#define _CPU_ISR_Enable( _isr_cookie ) \
627  lm32_enable_interrupts( _isr_cookie );
628
629/**
630 * This temporarily restores the interrupt to @a _isr_cookie before immediately
631 * disabling them again.  This is used to divide long RTEMS critical
632 * sections into two or more parts.  The parameter @a _isr_cookie is not
633 * modified.
634 *
635 * @param[in] _isr_cookie contain the previous level cookie
636 *
637 * Port Specific Information:
638 *
639 * XXX document implementation including references if appropriate
640 */
641#define _CPU_ISR_Flash( _isr_cookie ) \
642  lm32_flash_interrupts( _isr_cookie );
643
644RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
645{
646  return ( level & 0x0001 ) != 0;
647}
648
649/**
650 * This routine and @ref _CPU_ISR_Get_level
651 * Map the interrupt level in task mode onto the hardware that the CPU
652 * actually provides.  Currently, interrupt levels which do not
653 * map onto the CPU in a generic fashion are undefined.  Someday,
654 * it would be nice if these were "mapped" by the application
655 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
656 * 8 - 255 would be available for bsp/application specific meaning.
657 * This could be used to manage a programmable interrupt controller
658 * via the rtems_task_mode directive.
659 *
660 * Port Specific Information:
661 *
662 * XXX document implementation including references if appropriate
663 */
664#define _CPU_ISR_Set_level( new_level ) \
665  { \
666    _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
667  }
668
669/**
670 * Return the current interrupt disable level for this task in
671 * the format used by the interrupt level portion of the task mode.
672 *
673 * NOTE: This routine usually must be implemented as a subroutine.
674 *
675 * Port Specific Information:
676 *
677 * XXX document implementation including references if appropriate
678 */
679uint32_t   _CPU_ISR_Get_level( void );
680
681/* end of ISR handler macros */
682
683/** @} */
684
685/* Context handler macros */
686
687/**
688 * @ingroup CPUContext
689 * Initialize the context to a state suitable for starting a
690 * task after a context restore operation.  Generally, this
691 * involves:
692 *
693 *    - setting a starting address
694 *    - preparing the stack
695 *    - preparing the stack and frame pointers
696 *    - setting the proper interrupt level in the context
697 *    - initializing the floating point context
698 *
699 * This routine generally does not set any unnecessary register
700 * in the context.  The state of the "general data" registers is
701 * undefined at task start time.
702 *
703 * @param[in] _the_context is the context structure to be initialized
704 * @param[in] _stack_base is the lowest physical address of this task's stack
705 * @param[in] _size is the size of this task's stack
706 * @param[in] _isr is the interrupt disable level
707 * @param[in] _entry_point is the thread's entry point.  This is
708 *        always @a _Thread_Handler
709 * @param[in] _is_fp is TRUE if the thread is to be a floating
710 *       point thread.  This is typically only used on CPUs where the
711 *       FPU may be easily disabled by software such as on the SPARC
712 *       where the PSR contains an enable FPU bit.
713 *
714 * Port Specific Information:
715 *
716 * XXX document implementation including references if appropriate
717 */
718extern char _gp[];
719
720#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
721                                 _isr, _entry_point, _is_fp, _tls_area ) \
722   do { \
723     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
724     \
725     (void) _is_fp; /* avoid warning for being unused */ \
726     (void) _isr;  /* avoid warning for being unused */ \
727     (_the_context)->gp = (uint32_t)_gp; \
728     (_the_context)->fp = (uint32_t)_stack; \
729     (_the_context)->sp = (uint32_t)_stack; \
730     (_the_context)->ra = (uint32_t)(_entry_point); \
731   } while ( 0 )
732
733/**
734 * This routine is responsible for somehow restarting the currently
735 * executing task.  If you are lucky, then all that is necessary
736 * is restoring the context.  Otherwise, there will need to be
737 * a special assembly routine which does something special in this
738 * case.  For many ports, simply adding a label to the restore path
739 * of @ref _CPU_Context_switch will work.  On other ports, it may be
740 * possibly to load a few arguments and jump to the restore path. It will
741 * not work if restarting self conflicts with the stack frame
742 * assumptions of restoring a context.
743 *
744 * Port Specific Information:
745 *
746 * XXX document implementation including references if appropriate
747 */
748#define _CPU_Context_Restart_self( _the_context ) \
749   _CPU_Context_restore( (_the_context) );
750
751/**
752 * This routine initializes the FP context area passed to it to.
753 * There are a few standard ways in which to initialize the
754 * floating point context.  The code included for this macro assumes
755 * that this is a CPU in which a "initial" FP context was saved into
756 * @a _CPU_Null_fp_context and it simply copies it to the destination
757 * context passed to it.
758 *
759 * Other floating point context save/restore models include:
760 *   -# not doing anything, and
761 *   -# putting a "null FP status word" in the correct place in the FP context.
762 *
763 * @param[in] _destination is the floating point context area
764 *
765 * Port Specific Information:
766 *
767 * XXX document implementation including references if appropriate
768 */
769#define _CPU_Context_Initialize_fp( _destination )
770#if 0
771  { \
772   *(*(_destination)) = _CPU_Null_fp_context; \
773  }
774#endif
775
776/* end of Context handler macros */
777
778/* Fatal Error manager macros */
779
780/**
781 * This routine copies _error into a known place -- typically a stack
782 * location or a register, optionally disables interrupts, and
783 * halts/stops the CPU.
784 *
785 * Port Specific Information:
786 *
787 * XXX document implementation including references if appropriate
788 */
789#define _CPU_Fatal_halt( _source, _error ) \
790  { \
791  }
792
793/* end of Fatal Error manager macros */
794
795#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
796
797/* functions */
798
799/**
800 * This routine performs CPU dependent initialization.
801 *
802 * Port Specific Information:
803 *
804 * XXX document implementation including references if appropriate
805 */
806void _CPU_Initialize(void);
807
808/**
809 * @addtogroup CPUInterrupt
810 */
811/**@{**/
812
813/**
814 * This routine installs a "raw" interrupt handler directly into the
815 * processor's vector table.
816 *
817 * @param[in] vector is the vector number
818 * @param[in] new_handler is the raw ISR handler to install
819 * @param[in] old_handler is the previously installed ISR Handler
820 *
821 * Port Specific Information:
822 *
823 * XXX document implementation including references if appropriate
824 */
825void _CPU_ISR_install_raw_handler(
826  uint32_t    vector,
827  proc_ptr    new_handler,
828  proc_ptr   *old_handler
829);
830
831/**
832 * This routine installs an interrupt vector.
833 *
834 * @param[in] vector is the vector number
835 * @param[in] new_handler is the RTEMS ISR handler to install
836 * @param[in] old_handler is the previously installed ISR Handler
837 *
838 * Port Specific Information:
839 *
840 * XXX document implementation including references if appropriate
841 */
842void _CPU_ISR_install_vector(
843  uint32_t    vector,
844  proc_ptr    new_handler,
845  proc_ptr   *old_handler
846);
847
848/**
849 * This routine installs the hardware interrupt stack pointer.
850 *
851 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
852 *        is TRUE.
853 *
854 * Port Specific Information:
855 *
856 * XXX document implementation including references if appropriate
857 */
858void _CPU_Install_interrupt_stack( void );
859
860/** @} */
861
862/**
863 * This routine is the CPU dependent IDLE thread body.
864 *
865 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
866 *        is TRUE.
867 *
868 * Port Specific Information:
869 *
870 * XXX document implementation including references if appropriate
871 */
872void *_CPU_Thread_Idle_body( uintptr_t ignored );
873
874/**
875 * @ingroup CPUContext
876 * This routine switches from the run context to the heir context.
877 *
878 * @param[in] run points to the context of the currently executing task
879 * @param[in] heir points to the context of the heir task
880 *
881 * Port Specific Information:
882 *
883 * XXX document implementation including references if appropriate
884 */
885void _CPU_Context_switch(
886  Context_Control  *run,
887  Context_Control  *heir
888);
889
890/**
891 * @addtogroup CPUContext
892 */
893/**@{**/
894
895/**
896 * This routine is generally used only to restart self in an
897 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
898 *
899 * @param[in] new_context points to the context to be restored.
900 *
901 * NOTE: May be unnecessary to reload some registers.
902 *
903 * Port Specific Information:
904 *
905 * XXX document implementation including references if appropriate
906 */
907void _CPU_Context_restore(
908  Context_Control *new_context
909) RTEMS_NO_RETURN;
910
911/**
912 * This routine saves the floating point context passed to it.
913 *
914 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
915 * point context area
916 *
917 * @return on output @a *fp_context_ptr will contain the address that
918 * should be used with @ref _CPU_Context_restore_fp to restore this context.
919 *
920 * Port Specific Information:
921 *
922 * XXX document implementation including references if appropriate
923 */
924void _CPU_Context_save_fp(
925  Context_Control_fp **fp_context_ptr
926);
927
928/**
929 * This routine restores the floating point context passed to it.
930 *
931 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
932 * point context area to restore
933 *
934 * @return on output @a *fp_context_ptr will contain the address that
935 * should be used with @ref _CPU_Context_save_fp to save this context.
936 *
937 * Port Specific Information:
938 *
939 * XXX document implementation including references if appropriate
940 */
941void _CPU_Context_restore_fp(
942  Context_Control_fp **fp_context_ptr
943);
944
945static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
946{
947  /* TODO */
948}
949
950static inline void _CPU_Context_validate( uintptr_t pattern )
951{
952  while (1) {
953    /* TODO */
954  }
955}
956
957/** @} */
958
959/* FIXME */
960typedef CPU_Interrupt_frame CPU_Exception_frame;
961
962void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
963
964/**
965 * @ingroup CPUEndian
966 * The following routine swaps the endian format of an unsigned int.
967 * It must be static because it is referenced indirectly.
968 *
969 * This version will work on any processor, but if there is a better
970 * way for your CPU PLEASE use it.  The most common way to do this is to:
971 *
972 *    swap least significant two bytes with 16-bit rotate
973 *    swap upper and lower 16-bits
974 *    swap most significant two bytes with 16-bit rotate
975 *
976 * Some CPUs have special instructions which swap a 32-bit quantity in
977 * a single instruction (e.g. i486).  It is probably best to avoid
978 * an "endian swapping control bit" in the CPU.  One good reason is
979 * that interrupts would probably have to be disabled to ensure that
980 * an interrupt does not try to access the same "chunk" with the wrong
981 * endian.  Another good reason is that on some CPUs, the endian bit
982 * endianness for ALL fetches -- both code and data -- so the code
983 * will be fetched incorrectly.
984 *
985 * @param[in] value is the value to be swapped
986 * @return the value after being endian swapped
987 *
988 * Port Specific Information:
989 *
990 * XXX document implementation including references if appropriate
991 */
992static inline uint32_t CPU_swap_u32(
993  uint32_t value
994)
995{
996  uint32_t byte1, byte2, byte3, byte4, swapped;
997
998  byte4 = (value >> 24) & 0xff;
999  byte3 = (value >> 16) & 0xff;
1000  byte2 = (value >> 8)  & 0xff;
1001  byte1 =  value        & 0xff;
1002
1003  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1004  return swapped;
1005}
1006
1007/**
1008 * @ingroup CPUEndian
1009 * This routine swaps a 16 bir quantity.
1010 *
1011 * @param[in] value is the value to be swapped
1012 * @return the value after being endian swapped
1013 */
1014static inline uint16_t CPU_swap_u16(uint16_t v)
1015{
1016    return v << 8 | v >> 8;
1017}
1018
1019typedef uint32_t CPU_Counter_ticks;
1020
1021CPU_Counter_ticks _CPU_Counter_read( void );
1022
1023static inline CPU_Counter_ticks _CPU_Counter_difference(
1024  CPU_Counter_ticks second,
1025  CPU_Counter_ticks first
1026)
1027{
1028  return second - first;
1029}
1030
1031#ifdef __cplusplus
1032}
1033#endif
1034
1035#endif
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