1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * This file contains all assembly code for the |
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5 | * LM32 implementation of RTEMS. |
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6 | * |
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7 | * Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999, |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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15 | * Micro-Research Finland Oy |
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16 | * |
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17 | * Michael Walle <michael@walle.cc>, 2009 |
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18 | */ |
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19 | |
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20 | #ifdef HAVE_CONFIG_H |
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21 | #include "config.h" |
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22 | #endif |
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23 | |
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24 | #include <rtems/asm.h> |
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25 | #include <rtems/score/cpu_asm.h> |
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26 | |
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27 | /* void _CPU_Context_switch(run_context, heir_context) |
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28 | * |
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29 | * This routine performs a normal non-FP context switch. |
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30 | * |
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31 | * LM32 Specific Information: |
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32 | * |
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33 | * Saves/restores all callee-saved general purpose registers as well as |
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34 | * the stack pointer, return address and interrupt enable status register |
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35 | * to/from the context. |
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36 | * |
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37 | */ |
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38 | .globl _CPU_Context_switch |
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39 | _CPU_Context_switch: |
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40 | sw (r1+0), r11 /* r1 is the first argument */ |
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41 | sw (r1+4), r12 |
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42 | sw (r1+8), r13 |
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43 | sw (r1+12), r14 |
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44 | sw (r1+16), r15 |
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45 | sw (r1+20), r16 |
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46 | sw (r1+24), r17 |
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47 | sw (r1+28), r18 |
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48 | sw (r1+32), r19 |
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49 | sw (r1+36), r20 |
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50 | sw (r1+40), r21 |
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51 | sw (r1+44), r22 |
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52 | sw (r1+48), r23 |
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53 | sw (r1+52), r24 |
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54 | sw (r1+56), r25 |
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55 | sw (r1+60), gp |
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56 | sw (r1+64), fp |
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57 | sw (r1+68), sp |
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58 | sw (r1+72), ra |
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59 | rcsr r3, IE |
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60 | sw (r1+76), r3 |
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61 | .extern _exception_stack_frame |
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62 | mvhi r3, hi(_exception_stack_frame) |
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63 | ori r3, r3, lo(_exception_stack_frame) |
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64 | lw r4, (r3+0) |
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65 | be r4, r0, 2f |
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66 | 1: |
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67 | lw r5, (r4+44) |
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68 | sw (r3+0), r0 |
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69 | bi 3f |
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70 | 2: |
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71 | mvhi r5, hi(_Thread_Dispatch) |
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72 | ori r5, r5, lo(_Thread_Dispatch) |
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73 | 3: |
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74 | sw (r1+80), r5 |
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75 | |
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76 | _CPU_Context_switch_restore: |
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77 | lw r11, (r2+0) /* r2 is the second argument */ |
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78 | lw r12, (r2+4) |
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79 | lw r13, (r2+8) |
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80 | lw r14, (r2+12) |
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81 | lw r15, (r2+16) |
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82 | lw r16, (r2+20) |
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83 | lw r17, (r2+24) |
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84 | lw r18, (r2+28) |
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85 | lw r19, (r2+32) |
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86 | lw r20, (r2+36) |
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87 | lw r21, (r2+40) |
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88 | lw r22, (r2+44) |
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89 | lw r23, (r2+48) |
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90 | lw r24, (r2+52) |
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91 | lw r25, (r2+56) |
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92 | lw gp, (r2+60) |
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93 | lw fp, (r2+64) |
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94 | lw sp, (r2+68) |
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95 | lw ra, (r2+72) |
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96 | lw r3, (r2+76) |
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97 | wcsr IE, r3 |
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98 | ret |
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99 | |
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100 | /* |
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101 | * _CPU_Context_restore |
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102 | * |
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103 | * This routine is generally used only to restart self in an |
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104 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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105 | * |
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106 | * LM32 Specific Information: |
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107 | * |
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108 | * Moves argument #1 to #2 and branches to the restore part of the |
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109 | * context switch code above. |
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110 | */ |
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111 | .globl _CPU_Context_restore |
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112 | _CPU_Context_restore: |
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113 | mv r2, r1 |
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114 | bi _CPU_Context_switch_restore |
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115 | |
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116 | /* void _ISR_Handler() |
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117 | * |
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118 | * This routine provides the RTEMS interrupt management. |
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119 | * |
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120 | * LM32 Specific Information: |
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121 | * |
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122 | * Saves all the caller-saved general purpose registers as well as the |
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123 | * return address, exception return address and breakpoint return address |
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124 | * (the latter may be unnecessary) onto the stack, which is either the task |
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125 | * stack (in case of a interrupted task) or the interrupt stack (if an |
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126 | * interrupt was interrupted). |
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127 | * After that, it figures out the pending interrupt with the highest |
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128 | * priority and calls the main ISR handler written in C, which in turn |
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129 | * handles interrupt nesting, software interrupt stack setup etc and |
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130 | * finally calls the user ISR. |
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131 | * At the end the saved registers are restored. |
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132 | * |
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133 | */ |
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134 | |
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135 | .globl _ISR_Handler |
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136 | _ISR_Handler: |
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137 | xor r0, r0, r0 |
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138 | addi sp, sp, -52 |
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139 | sw (sp+4), r1 |
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140 | sw (sp+8), r2 |
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141 | sw (sp+12), r3 |
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142 | sw (sp+16), r4 |
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143 | sw (sp+20), r5 |
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144 | sw (sp+24), r6 |
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145 | sw (sp+28), r7 |
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146 | sw (sp+32), r8 |
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147 | sw (sp+36), r9 |
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148 | sw (sp+40), r10 |
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149 | sw (sp+44), ra |
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150 | sw (sp+48), ea |
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151 | sw (sp+52), ba |
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152 | |
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153 | /* |
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154 | * Scan through IP & IM bits starting from LSB until irq vector is |
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155 | * found. The vector is stored in r1, which is the first argument for |
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156 | * __ISR_Handler. |
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157 | */ |
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158 | rcsr r2, IP |
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159 | rcsr r3, IM |
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160 | mv r1, r0 /* r1: counter for the vector number */ |
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161 | and r2, r2, r3 /* r2: pending irqs, which are enabled */ |
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162 | mvi r3, 1 /* r3: register for the walking 1 */ |
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163 | /* |
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164 | * If r2 is zero, there was no interrupt. |
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165 | * This should never happen! |
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166 | */ |
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167 | be r2, r0, exit_isr |
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168 | find_irq: |
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169 | and r4, r2, r3 |
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170 | bne r4, r0, found_irq |
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171 | sli r3, r3, 1 |
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172 | addi r1, r1, 1 |
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173 | bi find_irq |
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174 | |
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175 | found_irq: |
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176 | /* |
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177 | * Call __ISR_Handler for further processing. |
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178 | * r1 is the vector number, calculated above |
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179 | * r2 is the pointer to the CPU_Interrupt_frame |
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180 | */ |
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181 | addi r2, sp, 4 |
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182 | |
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183 | .extern __ISR_Handler |
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184 | mvhi r3, hi(__ISR_Handler) |
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185 | ori r3, r3, lo(__ISR_Handler) |
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186 | call r3 |
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187 | |
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188 | exit_isr: |
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189 | /* Restore the saved registers */ |
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190 | lw r1, (sp+4) |
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191 | lw r2, (sp+8) |
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192 | lw r3, (sp+12) |
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193 | lw r4, (sp+16) |
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194 | lw r5, (sp+20) |
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195 | lw r6, (sp+24) |
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196 | lw r7, (sp+28) |
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197 | lw r8, (sp+32) |
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198 | lw r9, (sp+36) |
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199 | lw r10, (sp+40) |
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200 | lw ra, (sp+44) |
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201 | lw ea, (sp+48) |
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202 | lw ba, (sp+52) |
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203 | addi sp, sp, 52 |
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204 | eret |
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205 | |
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