source: rtems/cpukit/score/cpu/lm32/cpu_asm.S @ 6b4d0b8

4.104.115
Last change on this file since 6b4d0b8 was 6b4d0b8, checked in by Joel Sherrill <joel.sherrill@…>, on 12/04/08 at 22:53:15

2008-12-04 Jukka Pietarinen <jukka.pietarinen@…>

  • ChangeLog?, Makefile.am, cpu.c, cpu_asm.S, preinstall.am, rtems/asm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/lm32.h, rtems/score/types.h: New files.
  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 *  $Id$
3 *
4 *  This file contains all assembly code for the
5 *  LM32 implementation of RTEMS.
6 *
7 *  Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999,
8 *    On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
15 *  Micro-Research Finland Oy
16 */
17
18#include <rtems/asm.h>
19#include <rtems/score/cpu_asm.h>
20
21#define MICO32_FULL_CONTEXT_SAVE_RESTORE
22       
23/*  void _CPU_Context_switch(run_context, heir_context)
24 *
25 *  This routine performs a normal non-FP context switch.
26 *
27 *  LM32 Specific Information:
28 *
29 *  XXX document implementation including references if appropriate
30 */
31    .globl _CPU_Context_switch
32_CPU_Context_switch:
33    sw      (r1+0), r9
34    sw      (r1+4), r10
35    sw      (r1+8), r11
36    sw      (r1+12), r12
37    sw      (r1+16), r13
38    sw      (r1+20), r14
39    sw      (r1+24), r15
40    sw      (r1+28), r16
41    sw      (r1+32), r17
42    sw      (r1+36), r18
43    sw      (r1+40), r19
44    sw      (r1+44), r20
45    sw      (r1+48), r21
46    sw      (r1+52), r22
47    sw      (r1+56), r23
48    sw      (r1+60), r24
49    sw      (r1+64), r25
50    sw      (r1+68), gp
51    sw      (r1+72), fp
52    sw      (r1+76), sp
53    sw      (r1+80), ra
54
55/*
56 *  _CPU_Context_restore
57 *
58 *  This routine is generally used only to restart self in an
59 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
60 *
61 *  NOTE: May be unnecessary to reload some registers.
62 *
63 *  LM32 Specific Information:
64 *
65 *  XXX document implementation including references if appropriate
66 */
67    .globl _CPU_Context_restore
68_CPU_Context_restore:
69    lw      r9, (r2+0)
70    lw      r10, (r2+4)
71    lw      r11, (r2+8)
72    lw      r12, (r2+12)
73    lw      r13, (r2+16)
74    lw      r14, (r2+20)
75    lw      r15, (r2+24)
76    lw      r16, (r2+28)
77    lw      r17, (r2+32)
78    lw      r18, (r2+36)
79    lw      r19, (r2+40)
80    lw      r20, (r2+44)
81    lw      r21, (r2+48)
82    lw      r22, (r2+52)
83    lw      r23, (r2+56)
84    lw      r24, (r2+60)
85    lw      r25, (r2+64)
86    lw      gp, (r2+68)
87    lw      fp, (r2+72)
88    lw      ra, (r2+80)
89    /* Stack pointer must be restored last, in case it has been updated */
90    lw      sp, (r2+76)
91    nop
92    ret
93       
94/*  void __ISR_Handler()
95 *
96 *  This routine provides the RTEMS interrupt management.
97 *
98 *  LM32 Specific Information:
99 *
100 *  XXX document implementation including references if appropriate
101 */
102
103    .globl  _ISR_Handler
104_ISR_Handler:
105    addi    sp, sp, -128
106    sw      (sp+4), r1
107    sw      (sp+8), r2
108    sw      (sp+12), r3
109    sw      (sp+16), r4
110    sw      (sp+20), r5
111    sw      (sp+24), r6
112    sw      (sp+28), r7
113    sw      (sp+32), r8
114    sw      (sp+36), r9
115    sw      (sp+40), r10
116#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
117    sw      (sp+44), r11
118    sw      (sp+48), r12
119    sw      (sp+52), r13
120    sw      (sp+56), r14
121    sw      (sp+60), r15
122    sw      (sp+64), r16
123    sw      (sp+68), r17
124    sw      (sp+72), r18
125    sw      (sp+76), r19
126    sw      (sp+80), r20
127    sw      (sp+84), r21
128    sw      (sp+88), r22
129    sw      (sp+92), r23
130    sw      (sp+96), r24
131    sw      (sp+100), r25
132    sw      (sp+104), r26
133    sw      (sp+108), r27
134#endif
135    sw      (sp+116), ra
136    sw      (sp+120), ea
137    sw      (sp+124), ba
138
139    /* Scan through (IP & IM) bits starting from LSB until irq found */
140    rcsr    r2,IP
141    rcsr    r3,IM
142    and     r4,r2,r3
143    or      r1,r0,r0
144    ori     r5,r0,1
145find_irq:       
146    and     r6,r4,r5
147    bne     r6,r0,found_irq
148    sli     r5,r5,1
149    addi    r1,r1,1
150    bne     r5,r0,find_irq
151    /* If we end up here there was no interrupt - this should never
152       happen! */
153    bi      exit_isr
154
155found_irq:
156    .extern _ISR_Vector_table
157    sli     r1,r1,2
158    mvhi    r7,hi(_ISR_Vector_table)
159    ori     r7,r7,lo(_ISR_Vector_table)
160    lw      r6,(r7+0)
161    add     r6,r6,r1
162    lw      r5,(r6+0)
163    call    r5
164
165exit_isr:
166    lw      r1, (sp+4)
167    lw      r2, (sp+8)
168    lw      r3, (sp+12)
169    lw      r4, (sp+16)
170    lw      r5, (sp+20)
171    lw      r6, (sp+24)
172    lw      r7, (sp+28)
173    lw      r8, (sp+32)
174    lw      r9, (sp+36)
175    lw      r10, (sp+40)
176#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
177    lw      r11, (sp+44)
178    lw      r12, (sp+48)
179    lw      r13, (sp+52)
180    lw      r14, (sp+56)
181    lw      r15, (sp+60)
182    lw      r16, (sp+64)
183    lw      r17, (sp+68)
184    lw      r18, (sp+72)
185    lw      r19, (sp+76)
186    lw      r20, (sp+80)
187    lw      r21, (sp+84)
188    lw      r22, (sp+88)
189    lw      r23, (sp+92)
190    lw      r24, (sp+96)
191    lw      r25, (sp+100)
192    lw      r26, (sp+104)
193    lw      r27, (sp+108)
194#endif
195    lw      ra, (sp+116)
196    lw      ea, (sp+120)
197    lw      ba, (sp+124)
198    addi    sp, sp, 128
199    nop
200    eret
201
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