source: rtems/cpukit/score/cpu/lm32/cpu_asm.S @ 42e243e

4.104.11
Last change on this file since 42e243e was 42e243e, checked in by Ralf Corsepius <ralf.corsepius@…>, on Dec 4, 2009 at 4:27:21 AM

Whitespace removal.

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1/*
2 *  $Id$
3 *
4 *  This file contains all assembly code for the
5 *  LM32 implementation of RTEMS.
6 *
7 *  Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999,
8 *    On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
15 *  Micro-Research Finland Oy
16 *
17 *  Michael Walle <michael@walle.cc>, 2009
18 */
19
20#include <rtems/asm.h>
21#include <rtems/score/cpu_asm.h>
22
23/*  void _CPU_Context_switch(run_context, heir_context)
24 *
25 *  This routine performs a normal non-FP context switch.
26 *
27 *  LM32 Specific Information:
28 *
29 *  Saves/restores all callee-saved general purpose registers as well as
30 *  the stack pointer, return address and interrupt enable status register
31 *  to/from the context.
32 *
33 */
34    .globl _CPU_Context_switch
35_CPU_Context_switch:
36    sw      (r1+0), r11   /* r1 is the first argument */
37    sw      (r1+4), r12
38    sw      (r1+8), r13
39    sw      (r1+12), r14
40    sw      (r1+16), r15
41    sw      (r1+20), r16
42    sw      (r1+24), r17
43    sw      (r1+28), r18
44    sw      (r1+32), r19
45    sw      (r1+36), r20
46    sw      (r1+40), r21
47    sw      (r1+44), r22
48    sw      (r1+48), r23
49    sw      (r1+52), r24
50    sw      (r1+56), r25
51    sw      (r1+60), gp
52    sw      (r1+64), fp
53    sw      (r1+68), sp
54    sw      (r1+72), ra
55    rcsr    r3, IE
56    sw      (r1+76), r3
57    .extern _exception_stack_frame
58    mvhi    r3, hi(_exception_stack_frame)
59    ori     r3, r3, lo(_exception_stack_frame)
60    lw      r4, (r3+0)
61    be      r4, r0, 2f
621:
63    lw      r5, (r4+44)
64    sw      (r3+0), r0
65    bi      3f
662:
67    mvhi    r5, hi(_Thread_Dispatch)
68    ori     r5, r5, lo(_Thread_Dispatch)
693:
70    sw      (r1+80), r5
71
72_CPU_Context_switch_restore:
73    lw      r11, (r2+0)   /* r2 is the second argument */
74    lw      r12, (r2+4)
75    lw      r13, (r2+8)
76    lw      r14, (r2+12)
77    lw      r15, (r2+16)
78    lw      r16, (r2+20)
79    lw      r17, (r2+24)
80    lw      r18, (r2+28)
81    lw      r19, (r2+32)
82    lw      r20, (r2+36)
83    lw      r21, (r2+40)
84    lw      r22, (r2+44)
85    lw      r23, (r2+48)
86    lw      r24, (r2+52)
87    lw      r25, (r2+56)
88    lw      gp, (r2+60)
89    lw      fp, (r2+64)
90    lw      sp, (r2+68)
91    lw      ra, (r2+72)
92    lw      r3, (r2+76)
93    wcsr    IE, r3
94    ret
95
96/*
97 *  _CPU_Context_restore
98 *
99 *  This routine is generally used only to restart self in an
100 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
101 *
102 *  LM32 Specific Information:
103 *
104 *  Moves argument #1 to #2 and branches to the restore part of the
105 *  context switch code above.
106 */
107    .globl _CPU_Context_restore
108_CPU_Context_restore:
109    mv      r2, r1
110    bi      _CPU_Context_switch_restore
111
112/*  void _ISR_Handler()
113 *
114 *  This routine provides the RTEMS interrupt management.
115 *
116 *  LM32 Specific Information:
117 *
118 *  Saves all the caller-saved general purpose registers as well as the
119 *  return address, exception return address and breakpoint return address
120 *  (the latter may be unnecessary) onto the stack, which is either the task
121 *  stack (in case of a interrupted task) or the interrupt stack (if an
122 *  interrupt was interrupted).
123 *  After that, it figures out the pending interrupt with the highest
124 *  priority and calls the main ISR handler written in C, which in turn
125 *  handles interrupt nesting, software interrupt stack setup etc and
126 *  finally calls the user ISR.
127 *  At the end the saved registers are restored.
128 *
129 */
130
131    .globl  _ISR_Handler
132_ISR_Handler:
133    xor      r0, r0, r0
134    addi     sp, sp, -52
135    sw       (sp+4), r1
136    sw       (sp+8), r2
137    sw       (sp+12), r3
138    sw       (sp+16), r4
139    sw       (sp+20), r5
140    sw       (sp+24), r6
141    sw       (sp+28), r7
142    sw       (sp+32), r8
143    sw       (sp+36), r9
144    sw       (sp+40), r10
145    sw       (sp+44), ra
146    sw       (sp+48), ea
147    sw       (sp+52), ba
148
149    /*
150     * Scan through IP & IM bits starting from LSB until irq vector is
151     * found. The vector is stored in r1, which is the first argument for
152     * __ISR_Handler.
153     */
154    rcsr    r2, IP
155    rcsr    r3, IM
156    mv      r1, r0        /* r1: counter for the vector number */
157    and     r2, r2, r3    /* r2: pending irqs, which are enabled */
158    mvi     r3, 1         /* r3: register for the walking 1 */
159    /*
160     * If r2 is zero, there was no interrupt.
161     * This should never happen!
162     */
163    be      r2, r0, exit_isr
164find_irq:
165    and     r4, r2, r3
166    bne     r4, r0, found_irq
167    sli     r3, r3, 1
168    addi    r1, r1, 1
169    bi      find_irq
170
171found_irq:
172    /*
173     * Call __ISR_Handler for further processing.
174     * r1 is the vector number, calculated above
175     * r2 is the pointer to the CPU_Interrupt_frame
176     */
177    addi    r2, sp, 4
178
179    .extern __ISR_Handler
180    mvhi    r3, hi(__ISR_Handler)
181    ori     r3, r3, lo(__ISR_Handler)
182    call    r3
183
184exit_isr:
185    /* Restore the saved registers */
186    lw      r1, (sp+4)
187    lw      r2, (sp+8)
188    lw      r3, (sp+12)
189    lw      r4, (sp+16)
190    lw      r5, (sp+20)
191    lw      r6, (sp+24)
192    lw      r7, (sp+28)
193    lw      r8, (sp+32)
194    lw      r9, (sp+36)
195    lw      r10, (sp+40)
196    lw      ra, (sp+44)
197    lw      ea, (sp+48)
198    lw      ba, (sp+52)
199    addi    sp, sp, 52
200    eret
201
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