1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief LM32 CPU Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-1999. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | * |
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15 | * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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16 | * Micro-Research Finland Oy |
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17 | */ |
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18 | |
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19 | #ifdef HAVE_CONFIG_H |
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20 | #include "config.h" |
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21 | #endif |
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22 | |
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23 | #include <rtems/system.h> |
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24 | #include <rtems/score/isr.h> |
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25 | #include <rtems/score/wkspace.h> |
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26 | |
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27 | /* _CPU_Initialize |
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28 | * |
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29 | * This routine performs processor dependent initialization. |
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30 | * |
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31 | * INPUT PARAMETERS: NONE |
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32 | * |
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33 | * LM32 Specific Information: |
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34 | * |
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35 | * XXX document implementation including references if appropriate |
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36 | */ |
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37 | |
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38 | void _CPU_Initialize(void) |
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39 | { |
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40 | /* |
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41 | * If there is not an easy way to initialize the FP context |
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42 | * during Context_Initialize, then it is usually easier to |
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43 | * save an "uninitialized" FP context here and copy it to |
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44 | * the task's during Context_Initialize. |
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45 | */ |
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46 | |
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47 | /* FP context initialization support goes here */ |
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48 | } |
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49 | |
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50 | uint32_t _CPU_ISR_Get_level( void ) |
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51 | { |
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52 | /* |
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53 | * This routine returns the current interrupt level. |
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54 | */ |
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55 | |
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56 | return 0; |
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57 | } |
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58 | |
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59 | /* |
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60 | * _CPU_ISR_install_raw_handler |
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61 | * |
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62 | * LM32 Specific Information: |
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63 | * |
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64 | * XXX document implementation including references if appropriate |
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65 | */ |
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66 | |
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67 | void _CPU_ISR_install_raw_handler( |
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68 | uint32_t vector, |
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69 | proc_ptr new_handler, |
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70 | proc_ptr *old_handler |
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71 | ) |
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72 | { |
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73 | /* |
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74 | * This is where we install the interrupt handler into the "raw" interrupt |
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75 | * table used by the CPU to dispatch interrupt handlers. |
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76 | */ |
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77 | } |
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78 | |
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79 | void _CPU_ISR_install_vector( |
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80 | uint32_t vector, |
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81 | proc_ptr new_handler, |
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82 | proc_ptr *old_handler |
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83 | ) |
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84 | { |
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85 | *old_handler = _ISR_Vector_table[ vector ]; |
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86 | |
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87 | /* |
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88 | * If the interrupt vector table is a table of pointer to isr entry |
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89 | * points, then we need to install the appropriate RTEMS interrupt |
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90 | * handler for this vector number. |
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91 | */ |
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92 | |
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93 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
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94 | |
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95 | /* |
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96 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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97 | * be used by the _ISR_Handler so the user gets control. |
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98 | */ |
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99 | |
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100 | _ISR_Vector_table[ vector ] = new_handler; |
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101 | } |
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102 | |
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103 | /* |
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104 | * _CPU_Install_interrupt_stack |
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105 | * |
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106 | * LM32 Specific Information: |
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107 | * |
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108 | * XXX document implementation including references if appropriate |
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109 | */ |
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110 | |
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111 | void _CPU_Install_interrupt_stack( void ) |
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112 | { |
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113 | } |
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114 | |
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115 | /* |
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116 | * _CPU_Thread_Idle_body |
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117 | * |
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118 | * NOTES: |
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119 | * |
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120 | * 1. This is the same as the regular CPU independent algorithm. |
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121 | * |
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122 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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123 | * instruction, then don't forget to put it in an infinite loop. |
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124 | * |
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125 | * 3. Be warned. Some processors with onboard DMA have been known |
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126 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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127 | * also be a problem with other on-chip peripherals. So use this |
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128 | * hook with caution. |
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129 | * |
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130 | * LM32 Specific Information: |
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131 | * |
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132 | * XXX document implementation including references if appropriate |
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133 | */ |
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134 | |
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135 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
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136 | { |
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137 | for( ; ; ) { |
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138 | /* The LM32 softcore itself hasn't any HLT instruction. But the |
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139 | * LM32 qemu target interprets this nop instruction as HLT. |
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140 | */ |
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141 | __asm__ volatile("and r0, r0, r0"); |
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142 | } |
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143 | } |
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