1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @brief LM32 CPU Dependent Source |
---|
5 | */ |
---|
6 | |
---|
7 | /* |
---|
8 | * COPYRIGHT (c) 1989-1999. |
---|
9 | * On-Line Applications Research Corporation (OAR). |
---|
10 | * |
---|
11 | * The license and distribution terms for this file may be |
---|
12 | * found in the file LICENSE in this distribution or at |
---|
13 | * http://www.rtems.org/license/LICENSE. |
---|
14 | * |
---|
15 | * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
---|
16 | * Micro-Research Finland Oy |
---|
17 | */ |
---|
18 | |
---|
19 | #ifdef HAVE_CONFIG_H |
---|
20 | #include "config.h" |
---|
21 | #endif |
---|
22 | |
---|
23 | #include <rtems/system.h> |
---|
24 | #include <rtems/score/isr.h> |
---|
25 | #include <rtems/score/wkspace.h> |
---|
26 | |
---|
27 | /* _CPU_Initialize |
---|
28 | * |
---|
29 | * This routine performs processor dependent initialization. |
---|
30 | * |
---|
31 | * INPUT PARAMETERS: NONE |
---|
32 | * |
---|
33 | * LM32 Specific Information: |
---|
34 | * |
---|
35 | * XXX document implementation including references if appropriate |
---|
36 | */ |
---|
37 | |
---|
38 | void _CPU_Initialize(void) |
---|
39 | { |
---|
40 | /* |
---|
41 | * If there is not an easy way to initialize the FP context |
---|
42 | * during Context_Initialize, then it is usually easier to |
---|
43 | * save an "uninitialized" FP context here and copy it to |
---|
44 | * the task's during Context_Initialize. |
---|
45 | */ |
---|
46 | |
---|
47 | /* FP context initialization support goes here */ |
---|
48 | } |
---|
49 | |
---|
50 | uint32_t _CPU_ISR_Get_level( void ) |
---|
51 | { |
---|
52 | /* |
---|
53 | * This routine returns the current interrupt level. |
---|
54 | */ |
---|
55 | |
---|
56 | return 0; |
---|
57 | } |
---|
58 | |
---|
59 | void _CPU_ISR_install_vector( |
---|
60 | uint32_t vector, |
---|
61 | CPU_ISR_handler new_handler, |
---|
62 | CPU_ISR_handler *old_handler |
---|
63 | ) |
---|
64 | { |
---|
65 | *old_handler = _ISR_Vector_table[ vector ]; |
---|
66 | |
---|
67 | /* |
---|
68 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
---|
69 | * be used by the _ISR_Handler so the user gets control. |
---|
70 | */ |
---|
71 | |
---|
72 | _ISR_Vector_table[ vector ] = new_handler; |
---|
73 | } |
---|
74 | |
---|
75 | /* |
---|
76 | * _CPU_Thread_Idle_body |
---|
77 | * |
---|
78 | * NOTES: |
---|
79 | * |
---|
80 | * 1. This is the same as the regular CPU independent algorithm. |
---|
81 | * |
---|
82 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
---|
83 | * instruction, then don't forget to put it in an infinite loop. |
---|
84 | * |
---|
85 | * 3. Be warned. Some processors with onboard DMA have been known |
---|
86 | * to stop the DMA if the CPU were put in IDLE mode. This might |
---|
87 | * also be a problem with other on-chip peripherals. So use this |
---|
88 | * hook with caution. |
---|
89 | * |
---|
90 | * LM32 Specific Information: |
---|
91 | * |
---|
92 | * XXX document implementation including references if appropriate |
---|
93 | */ |
---|
94 | |
---|
95 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
---|
96 | { |
---|
97 | for( ; ; ) { |
---|
98 | /* The LM32 softcore itself hasn't any HLT instruction. But the |
---|
99 | * LM32 qemu target interprets this nop instruction as HLT. |
---|
100 | */ |
---|
101 | __asm__ volatile("and r0, r0, r0"); |
---|
102 | } |
---|
103 | } |
---|