source: rtems/cpukit/score/cpu/lm32/cpu.c @ 5632f8d

4.104.11
Last change on this file since 5632f8d was 5632f8d, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:02:21 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • cpu.c, cpu_asm.S, irq.c: Add include of config.h
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 *  Lattice Mico32 (lm32) CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 *
14 *  Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
15 *  Micro-Research Finland Oy
16 */
17
18#ifdef HAVE_CONFIG_H
19#include "config.h"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/score/isr.h>
24#include <rtems/score/wkspace.h>
25
26/*  _CPU_Initialize
27 *
28 *  This routine performs processor dependent initialization.
29 *
30 *  INPUT PARAMETERS: NONE
31 *
32 *  LM32 Specific Information:
33 *
34 *  XXX document implementation including references if appropriate
35 */
36
37void _CPU_Initialize(void)
38{
39  /*
40   *  If there is not an easy way to initialize the FP context
41   *  during Context_Initialize, then it is usually easier to
42   *  save an "uninitialized" FP context here and copy it to
43   *  the task's during Context_Initialize.
44   */
45
46  /* FP context initialization support goes here */
47}
48
49/*PAGE
50 *
51 *  _CPU_ISR_Get_level
52 *
53 *  LM32 Specific Information:
54 *
55 *  XXX document implementation including references if appropriate
56 */
57
58uint32_t   _CPU_ISR_Get_level( void )
59{
60  /*
61   *  This routine returns the current interrupt level.
62   */
63
64  return 0;
65}
66
67/*PAGE
68 *
69 *  _CPU_ISR_install_raw_handler
70 *
71 *  LM32 Specific Information:
72 *
73 *  XXX document implementation including references if appropriate
74 */
75
76void _CPU_ISR_install_raw_handler(
77  uint32_t    vector,
78  proc_ptr    new_handler,
79  proc_ptr   *old_handler
80)
81{
82  /*
83   *  This is where we install the interrupt handler into the "raw" interrupt
84   *  table used by the CPU to dispatch interrupt handlers.
85   */
86}
87
88/*PAGE
89 *
90 *  _CPU_ISR_install_vector
91 *
92 *  This kernel routine installs the RTEMS handler for the
93 *  specified vector.
94 *
95 *  Input parameters:
96 *    vector      - interrupt vector number
97 *    old_handler - former ISR for this vector number
98 *    new_handler - replacement ISR for this vector number
99 *
100 *  Output parameters:  NONE
101 *
102 *
103 *  LM32 Specific Information:
104 *
105 *  XXX document implementation including references if appropriate
106 */
107
108void _CPU_ISR_install_vector(
109  uint32_t    vector,
110  proc_ptr    new_handler,
111  proc_ptr   *old_handler
112)
113{
114   *old_handler = _ISR_Vector_table[ vector ];
115
116   /*
117    *  If the interrupt vector table is a table of pointer to isr entry
118    *  points, then we need to install the appropriate RTEMS interrupt
119    *  handler for this vector number.
120    */
121
122   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
123
124   /*
125    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
126    *  be used by the _ISR_Handler so the user gets control.
127    */
128
129    _ISR_Vector_table[ vector ] = new_handler;
130}
131
132/*PAGE
133 *
134 *  _CPU_Install_interrupt_stack
135 *
136 *  LM32 Specific Information:
137 *
138 *  XXX document implementation including references if appropriate
139 */
140
141void _CPU_Install_interrupt_stack( void )
142{
143}
144
145/*PAGE
146 *
147 *  _CPU_Thread_Idle_body
148 *
149 *  NOTES:
150 *
151 *  1. This is the same as the regular CPU independent algorithm.
152 *
153 *  2. If you implement this using a "halt", "idle", or "shutdown"
154 *     instruction, then don't forget to put it in an infinite loop.
155 *
156 *  3. Be warned. Some processors with onboard DMA have been known
157 *     to stop the DMA if the CPU were put in IDLE mode.  This might
158 *     also be a problem with other on-chip peripherals.  So use this
159 *     hook with caution.
160 *
161 *  LM32 Specific Information:
162 *
163 *  XXX document implementation including references if appropriate
164 */
165
166void *_CPU_Thread_Idle_body( uintptr_t ignored )
167{
168  for( ; ; ) {
169    /* The LM32 softcore itself hasn't any HLT instruction. But the
170     * LM32 qemu target interprets this nop instruction as HLT.
171     */
172    asm volatile("and r0, r0, r0");
173 }
174}
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