source: rtems/cpukit/score/cpu/i960/rtems/score/cpu.h @ c346f33d

4.104.114.84.95
Last change on this file since c346f33d was c346f33d, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 30, 2004 at 11:49:14 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 13.3 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/i960.h>              /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/types.h>
26#endif
27
28#define CPU_INLINE_ENABLE_DISPATCH       FALSE
29#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
30
31/*
32 *  Use the i960's hardware interrupt stack support and have the
33 *  interrupt manager allocate the memory for it.
34 */
35
36#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
37#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
38#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
39
40/*
41 *  Does the RTEMS invoke the user's ISR with the vector number and
42 *  a pointer to the saved interrupt frame (1) or just the vector
43 *  number (0)?
44 */
45
46#define CPU_ISR_PASSES_FRAME_POINTER 0
47
48/*
49 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
50 *  (KB/MC/MX).  There does not appear to be an external coprocessor
51 *  for this family.
52 */
53
54#if ( I960_HAS_FPU == 1 )
55#define CPU_HARDWARE_FP     TRUE
56#error "Floating point support for i960 family has been implemented!!!"
57#else
58#define CPU_HARDWARE_FP     FALSE
59#endif
60
61#define CPU_SOFTWARE_FP     FALSE
62
63#define CPU_ALL_TASKS_ARE_FP             FALSE
64#define CPU_IDLE_TASK_IS_FP              FALSE
65#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
66
67#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
68#define CPU_STACK_GROWS_UP               TRUE
69#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
70
71/*
72 *  Define what is required to specify how the network to host conversion
73 *  routines are handled.
74 */
75
76#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
77#define CPU_BIG_ENDIAN                           TRUE
78#define CPU_LITTLE_ENDIAN                        FALSE
79
80
81/* structures */
82
83/*
84 *  Basic integer context for the i960 family.
85 */
86
87typedef struct {
88  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
89  void       *r1_sp;                  /* (r1)  Stack Pointer */
90  uint32_t    pc;                     /* (pc)  Processor Control */
91  void       *g8;                     /* (g8)  Global Register 8 */
92  void       *g9;                     /* (g9)  Global Register 9 */
93  void       *g10;                    /* (g10) Global Register 10 */
94  void       *g11;                    /* (g11) Global Register 11 */
95  void       *g12;                    /* (g12) Global Register 12 */
96  void       *g13;                    /* (g13) Global Register 13 */
97  uint32_t    g14;                    /* (g14) Global Register 14 */
98  void       *g15_fp;                 /* (g15) Frame Pointer */
99}   Context_Control;
100
101/*
102 *  FP context save area for the i960 Numeric Extension
103 */
104
105typedef struct {
106   uint32_t    fp0_1;                 /* (fp0) first word  */
107   uint32_t    fp0_2;                 /* (fp0) second word */
108   uint32_t    fp0_3;                 /* (fp0) third word  */
109   uint32_t    fp1_1;                 /* (fp1) first word  */
110   uint32_t    fp1_2;                 /* (fp1) second word */
111   uint32_t    fp1_3;                 /* (fp1) third word  */
112   uint32_t    fp2_1;                 /* (fp2) first word  */
113   uint32_t    fp2_2;                 /* (fp2) second word */
114   uint32_t    fp2_3;                 /* (fp2) third word  */
115   uint32_t    fp3_1;                 /* (fp3) first word  */
116   uint32_t    fp3_2;                 /* (fp3) second word */
117   uint32_t    fp3_3;                 /* (fp3) third word  */
118} Context_Control_fp;
119
120/*
121 *  The following structure defines the set of information saved
122 *  on the current stack by RTEMS upon receipt of each interrupt.
123 */
124
125typedef struct {
126  uint32_t     TBD;   /* XXX Fix for this CPU */
127} CPU_Interrupt_frame;
128
129/*
130 *  Call frame for the i960 family.
131 */
132
133typedef struct {
134  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
135  void       *r1_sp;                  /* (r1)  Stack Pointer */
136  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
137  void       *r3;                     /* (r3)  Local Register 3 */
138  void       *r4;                     /* (r4)  Local Register 4 */
139  void       *r5;                     /* (r5)  Local Register 5 */
140  void       *r6;                     /* (r6)  Local Register 6 */
141  void       *r7;                     /* (r7)  Local Register 7 */
142  void       *r8;                     /* (r8)  Local Register 8 */
143  void       *r9;                     /* (r9)  Local Register 9 */
144  void       *r10;                    /* (r10) Local Register 10 */
145  void       *r11;                    /* (r11) Local Register 11 */
146  void       *r12;                    /* (r12) Local Register 12 */
147  void       *r13;                    /* (r13) Local Register 13 */
148  void       *r14;                    /* (r14) Local Register 14 */
149  void       *r15;                    /* (r15) Local Register 15 */
150  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
151}   CPU_Call_frame;
152
153/*
154 *  The following table contains the information required to configure
155 *  the i960 specific parameters.
156 */
157
158typedef struct {
159  void       (*pretasking_hook)( void );
160  void       (*predriver_hook)( void );
161  void       (*postdriver_hook)( void );
162  void       (*idle_task)( void );
163  boolean      do_zero_of_workspace;
164  uint32_t     idle_task_stack_size;
165  uint32_t     interrupt_stack_size;
166  uint32_t     extra_mpci_receive_server_stack;
167  void *     (*stack_allocate_hook)( uint32_t   );
168  void       (*stack_free_hook)( void* );
169  /* end of fields required on all CPUs */
170}   rtems_cpu_table;
171
172/*
173 *  Macros to access required entires in the CPU Table are in
174 *  the file rtems/system.h.
175 */
176
177/*
178 *  Macros to access i960 specific additions to the CPU Table
179 *
180 *  NONE
181 */
182
183/* variables */
184
185SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
186SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
187
188/* constants */
189
190/*
191 *  This defines the number of levels and the mask used to pick those
192 *  bits out of a thread mode.
193 */
194
195#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
196#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
197
198/*
199 *  context size area for floating point
200 */
201
202#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
203
204/*
205 *  extra stack required by the MPCI receive server thread
206 */
207
208#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
209
210/*
211 *  i960 family supports 256 distinct vectors.
212 */
213
214#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
215#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
216
217/*
218 *  This is defined if the port has a special way to report the ISR nesting
219 *  level.  Most ports maintain the variable _ISR_Nest_level.
220 */
221
222#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
223
224/*
225 *  Minimum size of a thread's stack.
226 *
227 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
228 */
229
230#define CPU_STACK_MINIMUM_SIZE          2048
231
232/*
233 *  i960 is pretty tolerant of alignment but some CPU models do
234 *  better with different default aligments so we use what the
235 *  CPU model selected in rtems/score/i960.h.
236 */
237
238#define CPU_ALIGNMENT                   I960_CPU_ALIGNMENT
239#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
240#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
241
242/*
243 * i960ca stack requires 16 byte alignment
244 *
245 *  NOTE:  This factor may need to be family member dependent.
246 */
247
248#define CPU_STACK_ALIGNMENT        16
249
250/* macros */
251
252/*
253 *  ISR handler macros
254 *
255 *  These macros perform the following functions:
256 *     + initialize the RTEMS vector table
257 *     + disable all maskable CPU interrupts
258 *     + restore previous interrupt level (enable)
259 *     + temporarily restore interrupts (flash)
260 *     + set a particular level
261 */
262
263#define _CPU_Initialize_vectors()
264#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
265#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
266#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
267
268#define _CPU_ISR_Set_level( newlevel ) \
269  { \
270    uint32_t   _mask = 0; \
271    uint32_t   _level = (newlevel); \
272    \
273    __asm__ volatile ( "ldconst 0x1f0000,%0; \
274                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
275                                         : "0"  (_mask), "1" (_level) \
276    ); \
277  }
278
279uint32_t   _CPU_ISR_Get_level( void );
280
281/* ISR handler section macros */
282
283/*
284 *  Context handler macros
285 *
286 *  These macros perform the following functions:
287 *     + initialize a context area
288 *     + restart the current thread
289 *     + calculate the initial pointer into a FP context area
290 *     + initialize an FP context area
291 */
292
293#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
294                                  _isr, _entry, _is_fp ) \
295 { CPU_Call_frame *_texit_frame; \
296   uint32_t   _mask; \
297   uint32_t   _base_pc; \
298   uint32_t    _stack_tmp; \
299   void       *_stack; \
300   \
301  _stack_tmp = (uint32_t  )(_stack_base) + CPU_STACK_ALIGNMENT; \
302  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
303  _stack = (void *) _stack_tmp; \
304   \
305   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
306   \
307   (_the_context)->r0_pfp = _stack; \
308   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
309   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
310   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
311                  "modpc   0,0,%1 ; " \
312                  "andnot  %0,%1,%1 ; " \
313                  : "=d" (_mask), "=d" (_base_pc) : ); \
314   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
315   (_the_context)->g14    = 0; \
316   \
317   _texit_frame         = (CPU_Call_frame *)_stack; \
318   _texit_frame->r0_pfp = NULL; \
319   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
320   _texit_frame->r2_rip = (_entry); \
321 }
322
323#define _CPU_Context_Restart_self( _the_context ) \
324   _CPU_Context_restore( (_the_context) );
325
326#define _CPU_Context_Fp_start( _base, _offset )         NULL
327
328#define _CPU_Context_Initialize_fp( _fp_area )
329
330/* end of Context handler macros */
331
332/*
333 *  Fatal Error manager macros
334 *
335 *  These macros perform the following functions:
336 *    + disable interrupts and halt the CPU
337 */
338
339#define _CPU_Fatal_halt( _errorcode ) \
340  { uint32_t   _mask, _level; \
341    uint32_t   _error = (_errorcode); \
342    \
343    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
344                    mov     %0,%1 ; \
345                    modpc   0,%0,%1 ; \
346                    mov     %2,g0 ; \
347            self:   b       self " \
348                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
349  }
350
351/* end of Fatal Error Manager macros */
352
353/*
354 *  Bitfield handler macros
355 *
356 *  These macros perform the following functions:
357 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
358 */
359
360#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
361#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
362
363#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
364  { uint32_t   _search = (_value); \
365    \
366    (_output) = 0; /* to prevent warnings */ \
367    __asm__ volatile ( "scanbit   %0,%1  " \
368                    : "=d" (_search), "=d" (_output) \
369                    : "0"  (_search), "1"  (_output) ); \
370  }
371
372/* end of Bitfield handler macros */
373
374/*
375 *  Priority handler macros
376 *
377 *  These macros perform the following functions:
378 *    + return a mask with the bit for this major/minor portion of
379 *      of thread priority set.
380 *    + translate the bit number returned by "Bitfield_find_first_bit"
381 *      into an index into the thread ready chain bit maps
382 */
383
384#define _CPU_Priority_Mask( _bit_number ) \
385   ( 0x8000 >> (_bit_number) )
386
387#define _CPU_Priority_bits_index( _priority ) \
388   ( 15 - (_priority) )
389
390/* end of Priority handler macros */
391
392/* functions */
393
394/*
395 *  _CPU_Initialize
396 *
397 *  This routine performs CPU dependent initialization.
398 */
399
400void _CPU_Initialize(
401  rtems_cpu_table  *cpu_table,
402  void      (*thread_dispatch)
403);
404
405/*
406 *  _CPU_ISR_install_raw_handler
407 *
408 *  This routine installs a "raw" interrupt handler directly into the
409 *  processor's vector table.
410 */
411 
412void _CPU_ISR_install_raw_handler(
413  uint32_t    vector,
414  proc_ptr    new_handler,
415  proc_ptr   *old_handler
416);
417
418/*
419 *  _CPU_ISR_install_vector
420 *
421 *  This routine installs an interrupt vector.
422 */
423
424void _CPU_ISR_install_vector(
425  uint32_t    vector,
426  proc_ptr    new_handler,
427  proc_ptr   *old_handler
428);
429
430/*
431 *  _CPU_Install_interrupt_stack
432 *
433 *  This routine installs the hardware interrupt stack pointer.
434 */
435
436void _CPU_Install_interrupt_stack( void );
437
438/*
439 *  _CPU_Context_switch
440 *
441 *  This routine switches from the run context to the heir context.
442 */
443
444void _CPU_Context_switch(
445  Context_Control  *run,
446  Context_Control  *heir
447);
448
449/*
450 *  _CPU_Context_restore
451 *
452 *  This routine is generally used only to restart self in an
453 *  efficient manner and avoid stack conflicts.
454 */
455
456void _CPU_Context_restore(
457  Context_Control *new_context
458);
459
460/*
461 *  _CPU_Context_save_fp
462 *
463 *  This routine saves the floating point context passed to it.
464 */
465
466void _CPU_Context_save_fp(
467  void        **fp_context_ptr
468);
469
470/*
471 *  _CPU_Context_restore_fp
472 *
473 *  This routine restores the floating point context passed to it.
474 */
475
476void _CPU_Context_restore_fp(
477  void        **fp_context_ptr
478);
479
480#ifdef __cplusplus
481}
482#endif
483
484#endif
485/* end of include file */
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