source: rtems/cpukit/score/cpu/i960/cpu.c @ ac7d5ef0

4.104.114.84.95
Last change on this file since ac7d5ef0 was ac7d5ef0, checked in by Joel Sherrill <joel.sherrill@…>, on May 11, 1995 at 5:39:37 PM

Initial revision

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
17#else
18#warning "***    ENTIRE FILE IMPLEMENTED & TESTED FOR CA ONLY     ***"
19#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/fatal.h>
24#include <rtems/isr.h>
25
26/*  _CPU_Initialize
27 *
28 *  This routine performs processor dependent initialization.
29 *
30 *  INPUT PARAMETERS:
31 *    cpu_table       - CPU table to initialize
32 *    thread_dispatch - address of disptaching routine
33 *
34 *  OUTPUT PARAMETERS: NONE
35 */
36
37void _CPU_Initialize(
38  rtems_cpu_table  *cpu_table,
39  void      (*thread_dispatch)      /* ignored on this CPU */
40)
41{
42
43  if ( cpu_table == NULL )
44    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED );
45
46  _CPU_Table = *cpu_table;
47
48}
49
50/*  _CPU__ISR_Install_vector
51 *
52 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
53 *
54 *  Input parameters:
55 *    vector      - interrupt vector number
56 *    old_handler - former ISR for this vector number
57 *    new_handler - replacement ISR for this vector number
58 *
59 *  Output parameters:  NONE
60 *
61 */
62
63#define _Is_vector_caching_enabled( _prcb ) \
64   ((_prcb)->control_tbl->icon & 0x2000)
65
66void _CPU_ISR_install_vector(
67  unsigned32  vector,
68  proc_ptr    new_handler,
69  proc_ptr   *old_handler
70)
71{
72  i960ca_PRCB *prcb = _CPU_Table.Prcb;
73  proc_ptr    *cached_intr_tbl = NULL;
74
75/*  The i80960CA does not support vectors 0-7.  The first 9 entries
76 *  in the Interrupt Table are used to manage pending interrupts.
77 *  Thus vector 8, the first valid vector number, is actually in
78 *  slot 9 in the table.
79 */
80
81  *old_handler = _ISR_Vector_table[ vector ];
82
83  _ISR_Vector_table[ vector ] = new_handler;
84
85  prcb->intr_tbl[ vector + 1 ] = _ISR_Handler;
86  if ( _Is_vector_caching_enabled( prcb ) )
87    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
88      cached_intr_tbl[ vector >> 4 ] = _ISR_Handler;
89}
90
91/*PAGE
92 *
93 *  _CPU_Install_interrupt_stack
94 */
95
96#define soft_reset( prcb ) \
97 { register i960ca_PRCB *_prcb = (prcb); \
98   register unsigned32  *_next=0; \
99   register unsigned32   _cmd  = 0x30000; \
100   asm volatile( "lda    next,%1; \
101                  sysctl %0,%1,%2; \
102            next: mov    g0,g0" \
103                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
104                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
105 }
106
107void _CPU_Install_interrupt_stack( void )
108{
109  i960ca_PRCB *prcb = _CPU_Table.Prcb;
110  unsigned32   level;
111
112  /*
113   *  Set the Interrupt Stack in the PRCB and force a reload of it.
114   *  Interrupts are disabled for safety.
115   */
116
117  _CPU_ISR_Disable( level );
118
119    prcb->intr_stack = _CPU_Interrupt_stack_low;
120
121    soft_reset( prcb );
122
123  _CPU_ISR_Enable( level );
124}
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