source: rtems/cpukit/score/cpu/i960/cpu.c @ 637df35

4.104.114.84.95
Last change on this file since 637df35 was 637df35, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 12, 1995 at 7:47:25 PM

Ada95, gnat, go32

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
17#else
18#warning "***    ENTIRE FILE IMPLEMENTED & TESTED FOR CA ONLY     ***"
19#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/fatal.h>
24#include <rtems/isr.h>
25
26/*  _CPU_Initialize
27 *
28 *  This routine performs processor dependent initialization.
29 *
30 *  INPUT PARAMETERS:
31 *    cpu_table       - CPU table to initialize
32 *    thread_dispatch - address of disptaching routine
33 *
34 *  OUTPUT PARAMETERS: NONE
35 */
36
37void _CPU_Initialize(
38  rtems_cpu_table  *cpu_table,
39  void      (*thread_dispatch)      /* ignored on this CPU */
40)
41{
42
43  if ( cpu_table == NULL )
44    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED );
45
46  _CPU_Table = *cpu_table;
47
48}
49
50/*PAGE
51 *
52 *  _CPU_ISR_install_raw_handler
53 */
54 
55#define _Is_vector_caching_enabled( _prcb ) \
56   ((_prcb)->control_tbl->icon & 0x2000)
57
58void _CPU_ISR_install_raw_handler(
59  unsigned32  vector,
60  proc_ptr    new_handler,
61  proc_ptr   *old_handler
62)
63{
64  i960ca_PRCB *prcb = _CPU_Table.Prcb;
65  proc_ptr    *cached_intr_tbl = NULL;
66
67  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
68   *  in the Interrupt Table are used to manage pending interrupts.
69   *  Thus vector 8, the first valid vector number, is actually in
70   *  slot 9 in the table.
71   */
72
73  *old_handler = prcb->intr_tbl[ vector + 1 ];
74
75  prcb->intr_tbl[ vector + 1 ] = new_handler;
76
77  if ( _Is_vector_caching_enabled( prcb ) )
78    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
79      cached_intr_tbl[ vector >> 4 ] = new_handler;
80}
81
82/*PAGE
83 *
84 *  _CPU__ISR_install_vector
85 *
86 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
87 *
88 *  Input parameters:
89 *    vector      - interrupt vector number
90 *    old_handler - former ISR for this vector number
91 *    new_handler - replacement ISR for this vector number
92 *
93 *  Output parameters:  NONE
94 *
95 */
96
97void _CPU_ISR_install_vector(
98  unsigned32  vector,
99  proc_ptr    new_handler,
100  proc_ptr   *old_handler
101)
102{
103  proc_ptr ignored;
104
105  *old_handler = _ISR_Vector_table[ vector ];
106
107  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
108
109  _ISR_Vector_table[ vector ] = new_handler;
110}
111
112/*PAGE
113 *
114 *  _CPU_Install_interrupt_stack
115 */
116
117#define soft_reset( prcb ) \
118 { register i960ca_PRCB *_prcb = (prcb); \
119   register unsigned32  *_next=0; \
120   register unsigned32   _cmd  = 0x30000; \
121   asm volatile( "lda    next,%1; \
122                  sysctl %0,%1,%2; \
123            next: mov    g0,g0" \
124                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
125                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
126 }
127
128void _CPU_Install_interrupt_stack( void )
129{
130  i960ca_PRCB *prcb = _CPU_Table.Prcb;
131  unsigned32   level;
132
133  /*
134   *  Set the Interrupt Stack in the PRCB and force a reload of it.
135   *  Interrupts are disabled for safety.
136   */
137
138  _CPU_ISR_Disable( level );
139
140    prcb->intr_stack = _CPU_Interrupt_stack_low;
141
142    soft_reset( prcb );
143
144  _CPU_ISR_Enable( level );
145}
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