source: rtems/cpukit/score/cpu/i960/cpu.c @ 3652ad35

4.104.114.84.95
Last change on this file since 3652ad35 was 3a4ae6c, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 11, 1995 at 7:35:39 PM

The word "RTEMS" almost completely removed from the core.

Configuration Table Template file added and all tests
modified to use this. All gvar.h and conftbl.h files
removed from test directories.

Configuration parameter maximum_devices added.

Core semaphore and mutex handlers added and RTEMS API Semaphore
Manager updated to reflect this.

Initialization sequence changed to invoke API specific initialization
routines. Initialization tasks table now owned by RTEMS Tasks Manager.

Added user extension for post-switch.

Utilized user extensions to implement API specific functionality
like signal dispatching.

Added extensions to the System Initialization Thread so that an
API can register a function to be invoked while the system
is being initialized. These are largely equivalent to the
pre-driver and post-driver hooks.

Added the Modules file oar-go32_p5, modified oar-go32, and modified
the file make/custom/go32.cfg to look at an environment varable which
determines what CPU model is being used.

All BSPs updated to reflect named devices and clock driver's IOCTL
used by the Shared Memory Driver. Also merged clock isr into
main file and removed ckisr.c where possible.

Updated spsize to reflect new and moved variables.

Makefiles for the executive source and include files updated to show
break down of files into Core, RTEMS API, and Neither.

Header and inline files installed into subdirectory based on whether
logically in the Core or a part of the RTEMS API.

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
17#else
18#warning "***    ENTIRE FILE IMPLEMENTED & TESTED FOR CA ONLY     ***"
19#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/fatal.h>
24#include <rtems/core/isr.h>
25
26/*  _CPU_Initialize
27 *
28 *  This routine performs processor dependent initialization.
29 *
30 *  INPUT PARAMETERS:
31 *    cpu_table       - CPU table to initialize
32 *    thread_dispatch - address of disptaching routine
33 *
34 *  OUTPUT PARAMETERS: NONE
35 */
36
37void _CPU_Initialize(
38  rtems_cpu_table  *cpu_table,
39  void      (*thread_dispatch)      /* ignored on this CPU */
40)
41{
42
43  _CPU_Table = *cpu_table;
44
45}
46
47/*PAGE
48 *
49 *  _CPU_ISR_Get_level
50 */
51 
52unsigned32 _CPU_ISR_Get_level( void )
53{
54  unsigned32 level;
55 
56  i960_get_interrupt_level( level );
57 
58  return level;
59}
60
61/*PAGE
62 *
63 *  _CPU_ISR_install_raw_handler
64 */
65 
66#define _Is_vector_caching_enabled( _prcb ) \
67   ((_prcb)->control_tbl->icon & 0x2000)
68
69void _CPU_ISR_install_raw_handler(
70  unsigned32  vector,
71  proc_ptr    new_handler,
72  proc_ptr   *old_handler
73)
74{
75  i960ca_PRCB *prcb = _CPU_Table.Prcb;
76  proc_ptr    *cached_intr_tbl = NULL;
77
78  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
79   *  in the Interrupt Table are used to manage pending interrupts.
80   *  Thus vector 8, the first valid vector number, is actually in
81   *  slot 9 in the table.
82   */
83
84  *old_handler = prcb->intr_tbl[ vector + 1 ];
85
86  prcb->intr_tbl[ vector + 1 ] = new_handler;
87
88  if ( _Is_vector_caching_enabled( prcb ) )
89    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
90      cached_intr_tbl[ vector >> 4 ] = new_handler;
91}
92
93/*PAGE
94 *
95 *  _CPU__ISR_install_vector
96 *
97 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
98 *
99 *  Input parameters:
100 *    vector      - interrupt vector number
101 *    old_handler - former ISR for this vector number
102 *    new_handler - replacement ISR for this vector number
103 *
104 *  Output parameters:  NONE
105 *
106 */
107
108void _CPU_ISR_install_vector(
109  unsigned32  vector,
110  proc_ptr    new_handler,
111  proc_ptr   *old_handler
112)
113{
114  proc_ptr ignored;
115
116  *old_handler = _ISR_Vector_table[ vector ];
117
118  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
119
120  _ISR_Vector_table[ vector ] = new_handler;
121}
122
123/*PAGE
124 *
125 *  _CPU_Install_interrupt_stack
126 */
127
128#define soft_reset( prcb ) \
129 { register i960ca_PRCB *_prcb = (prcb); \
130   register unsigned32  *_next=0; \
131   register unsigned32   _cmd  = 0x30000; \
132   asm volatile( "lda    next,%1; \
133                  sysctl %0,%1,%2; \
134            next: mov    g0,g0" \
135                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
136                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
137 }
138
139void _CPU_Install_interrupt_stack( void )
140{
141  i960ca_PRCB *prcb = _CPU_Table.Prcb;
142  unsigned32   level;
143
144  /*
145   *  Set the Interrupt Stack in the PRCB and force a reload of it.
146   *  Interrupts are disabled for safety.
147   */
148
149  _CPU_ISR_Disable( level );
150
151    prcb->intr_stack = _CPU_Interrupt_stack_low;
152
153    soft_reset( prcb );
154
155  _CPU_ISR_Enable( level );
156}
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