[ac7d5ef0] | 1 | /* |
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| 2 | * Intel i960CA Dependent Source |
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| 3 | * |
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| 4 | * |
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[60b791ad] | 5 | * COPYRIGHT (c) 1989-1998. |
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[ac7d5ef0] | 6 | * On-Line Applications Research Corporation (OAR). |
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[03f2154e] | 7 | * Copyright assigned to U.S. Government, 1994. |
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[ac7d5ef0] | 8 | * |
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[98e4ebf5] | 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 11 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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| 17 | #else |
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| 18 | #warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA ONLY ***" |
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| 19 | #warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***" |
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| 20 | #endif |
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| 21 | |
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| 22 | #include <rtems/system.h> |
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[5e9b32b] | 23 | #include <rtems/score/isr.h> |
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[ac7d5ef0] | 24 | |
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| 25 | /* _CPU_Initialize |
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| 26 | * |
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| 27 | * This routine performs processor dependent initialization. |
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| 28 | * |
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| 29 | * INPUT PARAMETERS: |
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| 30 | * cpu_table - CPU table to initialize |
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| 31 | * thread_dispatch - address of disptaching routine |
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| 32 | * |
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| 33 | * OUTPUT PARAMETERS: NONE |
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| 34 | */ |
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| 35 | |
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| 36 | void _CPU_Initialize( |
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| 37 | rtems_cpu_table *cpu_table, |
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| 38 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 39 | ) |
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| 40 | { |
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| 41 | |
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| 42 | _CPU_Table = *cpu_table; |
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| 43 | |
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| 44 | } |
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| 45 | |
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[3a4ae6c] | 46 | /*PAGE |
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| 47 | * |
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| 48 | * _CPU_ISR_Get_level |
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| 49 | */ |
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| 50 | |
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| 51 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 52 | { |
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| 53 | unsigned32 level; |
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| 54 | |
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| 55 | i960_get_interrupt_level( level ); |
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| 56 | |
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| 57 | return level; |
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| 58 | } |
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| 59 | |
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[637df35] | 60 | /*PAGE |
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| 61 | * |
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| 62 | * _CPU_ISR_install_raw_handler |
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| 63 | */ |
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| 64 | |
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| 65 | #define _Is_vector_caching_enabled( _prcb ) \ |
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| 66 | ((_prcb)->control_tbl->icon & 0x2000) |
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| 67 | |
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| 68 | void _CPU_ISR_install_raw_handler( |
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| 69 | unsigned32 vector, |
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| 70 | proc_ptr new_handler, |
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| 71 | proc_ptr *old_handler |
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| 72 | ) |
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| 73 | { |
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| 74 | i960ca_PRCB *prcb = _CPU_Table.Prcb; |
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| 75 | proc_ptr *cached_intr_tbl = NULL; |
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| 76 | |
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| 77 | /* The i80960CA does not support vectors 0-7. The first 9 entries |
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| 78 | * in the Interrupt Table are used to manage pending interrupts. |
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| 79 | * Thus vector 8, the first valid vector number, is actually in |
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| 80 | * slot 9 in the table. |
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| 81 | */ |
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| 82 | |
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| 83 | *old_handler = prcb->intr_tbl[ vector + 1 ]; |
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| 84 | |
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| 85 | prcb->intr_tbl[ vector + 1 ] = new_handler; |
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| 86 | |
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| 87 | if ( _Is_vector_caching_enabled( prcb ) ) |
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| 88 | if ( (vector & 0xf) == 0x2 ) /* cacheable? */ |
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| 89 | cached_intr_tbl[ vector >> 4 ] = new_handler; |
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| 90 | } |
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| 91 | |
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| 92 | /*PAGE |
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| 93 | * |
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| 94 | * _CPU__ISR_install_vector |
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[ac7d5ef0] | 95 | * |
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| 96 | * Install the RTEMS vector wrapper in the CPU's interrupt table. |
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| 97 | * |
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| 98 | * Input parameters: |
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| 99 | * vector - interrupt vector number |
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| 100 | * old_handler - former ISR for this vector number |
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| 101 | * new_handler - replacement ISR for this vector number |
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| 102 | * |
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| 103 | * Output parameters: NONE |
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| 104 | * |
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| 105 | */ |
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| 106 | |
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| 107 | void _CPU_ISR_install_vector( |
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| 108 | unsigned32 vector, |
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| 109 | proc_ptr new_handler, |
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| 110 | proc_ptr *old_handler |
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| 111 | ) |
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| 112 | { |
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[637df35] | 113 | proc_ptr ignored; |
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[ac7d5ef0] | 114 | |
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| 115 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 116 | |
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[637df35] | 117 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[ac7d5ef0] | 118 | |
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[637df35] | 119 | _ISR_Vector_table[ vector ] = new_handler; |
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[ac7d5ef0] | 120 | } |
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| 121 | |
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| 122 | /*PAGE |
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| 123 | * |
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| 124 | * _CPU_Install_interrupt_stack |
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| 125 | */ |
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| 126 | |
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| 127 | #define soft_reset( prcb ) \ |
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| 128 | { register i960ca_PRCB *_prcb = (prcb); \ |
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| 129 | register unsigned32 *_next=0; \ |
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| 130 | register unsigned32 _cmd = 0x30000; \ |
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| 131 | asm volatile( "lda next,%1; \ |
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| 132 | sysctl %0,%1,%2; \ |
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| 133 | next: mov g0,g0" \ |
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| 134 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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| 135 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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| 136 | } |
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| 137 | |
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| 138 | void _CPU_Install_interrupt_stack( void ) |
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| 139 | { |
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| 140 | i960ca_PRCB *prcb = _CPU_Table.Prcb; |
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| 141 | unsigned32 level; |
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| 142 | |
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| 143 | /* |
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| 144 | * Set the Interrupt Stack in the PRCB and force a reload of it. |
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| 145 | * Interrupts are disabled for safety. |
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| 146 | */ |
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| 147 | |
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| 148 | _CPU_ISR_Disable( level ); |
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| 149 | |
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| 150 | prcb->intr_stack = _CPU_Interrupt_stack_low; |
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| 151 | |
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| 152 | soft_reset( prcb ); |
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| 153 | |
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| 154 | _CPU_ISR_Enable( level ); |
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| 155 | } |
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