1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Test FPU/SSE Context Save and Restore |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Authorship |
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9 | * ---------- |
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10 | * This software was created by |
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11 | * Till Straumann <strauman@slac.stanford.edu>, 2009, |
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12 | * Stanford Linear Accelerator Center, Stanford University. |
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13 | * |
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14 | * Acknowledgement of sponsorship |
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15 | * ------------------------------ |
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16 | * This software was produced by |
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17 | * the Stanford Linear Accelerator Center, Stanford University, |
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18 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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19 | * |
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20 | * Government disclaimer of liability |
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21 | * ---------------------------------- |
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22 | * Neither the United States nor the United States Department of Energy, |
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23 | * nor any of their employees, makes any warranty, express or implied, or |
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24 | * assumes any legal liability or responsibility for the accuracy, |
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25 | * completeness, or usefulness of any data, apparatus, product, or process |
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26 | * disclosed, or represents that its use would not infringe privately owned |
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27 | * rights. |
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28 | * |
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29 | * Stanford disclaimer of liability |
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30 | * -------------------------------- |
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31 | * Stanford University makes no representations or warranties, express or |
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32 | * implied, nor assumes any liability for the use of this software. |
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33 | * |
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34 | * Stanford disclaimer of copyright |
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35 | * -------------------------------- |
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36 | * Stanford University, owner of the copyright, hereby disclaims its |
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37 | * copyright and all other rights in this software. Hence, anyone may |
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38 | * freely use it for any purpose without restriction. |
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39 | * |
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40 | * Maintenance of notices |
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41 | * ---------------------- |
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42 | * In the interest of clarity regarding the origin and status of this |
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43 | * SLAC software, this and all the preceding Stanford University notices |
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44 | * are to remain affixed to any copy or derivative of this software made |
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45 | * or distributed by the recipient and are to be affixed to any copy of |
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46 | * software made or distributed by the recipient that contains a copy or |
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47 | * derivative of this software. |
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48 | * |
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49 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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50 | */ |
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51 | |
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52 | |
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53 | /* Code for testing FPU/SSE context save/restore across exceptions |
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54 | * (including interrupts). |
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55 | * |
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56 | * There are two tasks and an IRQ/EXC handler involved. One task (LP) |
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57 | * is of lower priority than the other (HP) task. |
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58 | * |
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59 | * 1) LP task sets up a context area in memory (known contents; every |
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60 | * register is loaded with different values) |
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61 | * |
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62 | * 2) LP task |
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63 | * 2a saves original FP/SSE context |
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64 | * 2b loads context from 1) into FPU/SSE |
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65 | * 2c raises an exception or interrupt |
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66 | * |
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67 | * * (2d save FPU/SSE context after irq/exception returns to |
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68 | * separate area for verification |
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69 | * 2e reload original FP/SSE context.) |
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70 | * |
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71 | * * All these five steps are coded in assembly to prevent |
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72 | * gcc from manipulating the FP/SSE state. The last two steps, |
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73 | * however, are effectively executed during 6 when control is |
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74 | * returned to the LP task. |
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75 | * |
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76 | * 3) IRQ/EXC handler OS wrapper saves context, initializes FPU and |
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77 | * MXCSR. |
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78 | * |
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79 | * 4) user (our) irq/exc handler clears exception condition, clobbers |
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80 | * FPU and XMM regs and finally releases a semaphore on which HP |
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81 | * task is waiting. |
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82 | * |
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83 | * 5) context switch to HP task. HP task clobbers FPU and XMM regs. |
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84 | * Then it tries to re-acquire the synchronization semaphore and |
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85 | * blocks. |
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86 | * |
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87 | * 6) task switch back to (interrupted) LP task. Original context is |
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88 | * restored and verified against the context that was setup in 1). |
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89 | * |
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90 | * |
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91 | * Three methods for interrupting the LP task are tested |
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92 | * |
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93 | * a) FP exception (by setting an exception status in the context from 1) |
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94 | * b) SSE exception (by computing the square root of a vector of negative |
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95 | * numbers. |
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96 | * c) IRQ (software IRQ via 'INT xx' instruction) |
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97 | * |
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98 | */ |
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99 | |
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100 | #ifdef HAVE_CONFIG_H |
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101 | #include "config.h" |
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102 | #endif |
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103 | |
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104 | #ifdef __rtems__ |
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105 | #include <rtems.h> |
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106 | #include <rtems/score/cpu.h> |
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107 | #include <rtems/irq.h> |
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108 | #include <rtems/error.h> |
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109 | #endif |
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110 | |
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111 | #include <inttypes.h> |
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112 | #include <stdio.h> |
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113 | #include <stdlib.h> |
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114 | #include <string.h> |
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115 | #include <math.h> |
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116 | |
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117 | /* This is currently hardcoded (int xx opcode requires immediate operand) */ |
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118 | #define SSE_TEST_IRQ 10 |
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119 | |
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120 | typedef uint8_t __v8 __attribute__((vector_size(16))); |
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121 | typedef uint32_t __v32 __attribute__((vector_size(16))); |
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122 | typedef float __vf __attribute__((vector_size(16))); |
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123 | |
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124 | #ifndef __rtems__ |
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125 | /* Clone of what is defined in rtems/score/cpu.h (for testing under linux) */ |
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126 | typedef struct Context_Control_sse { |
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127 | uint16_t fcw; |
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128 | uint16_t fsw; |
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129 | uint8_t ftw; |
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130 | uint8_t res_1; |
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131 | uint16_t fop; |
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132 | uint32_t fpu_ip; |
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133 | uint16_t cs; |
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134 | uint16_t res_2; |
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135 | uint32_t fpu_dp; |
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136 | uint16_t ds; |
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137 | uint16_t res_3; |
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138 | uint32_t mxcsr; |
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139 | uint32_t mxcsr_mask; |
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140 | struct { |
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141 | uint8_t fpreg[10]; |
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142 | uint8_t res_4[ 6]; |
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143 | } fp_mmregs[8]; |
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144 | uint8_t xmmregs[8][16]; |
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145 | uint8_t res_5[224]; |
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146 | } Context_Control_sse |
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147 | __attribute__((aligned(16))) |
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148 | ; |
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149 | #endif |
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150 | |
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151 | #define MXCSR_FZ (1<<15) /* Flush to zero */ |
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152 | #define MXCSR_RC(x) (((x)&3)<<13) /* Rounding ctrl */ |
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153 | #define MXCSR_PM (1<<12) /* Precision msk */ |
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154 | #define MXCSR_UM (1<<11) /* Underflow msk */ |
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155 | #define MXCSR_OM (1<<10) /* Overflow msk */ |
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156 | #define MXCSR_ZM (1<< 9) /* Divbyzero msk */ |
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157 | #define MXCSR_DM (1<< 8) /* Denormal msk */ |
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158 | #define MXCSR_IM (1<< 7) /* Invalidop msk */ |
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159 | #define MXCSR_DAZ (1<< 6) /* Denorml are 0 */ |
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160 | #define MXCSR_PE (1<< 5) /* Precision flg */ |
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161 | #define MXCSR_UE (1<< 4) /* Underflow flg */ |
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162 | #define MXCSR_OE (1<< 3) /* Overflow flg */ |
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163 | #define MXCSR_ZE (1<< 2) /* Divbyzero flg */ |
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164 | #define MXCSR_DE (1<< 1) /* Denormal flg */ |
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165 | #define MXCSR_IE (1<< 0) /* Invalidop flg */ |
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166 | |
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167 | #define MXCSR_ALLM (MXCSR_PM | MXCSR_UM | MXCSR_OM | MXCSR_ZM | MXCSR_DM | MXCSR_IM) |
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168 | #define MXCSR_ALLE (MXCSR_PE | MXCSR_UE | MXCSR_OE | MXCSR_ZE | MXCSR_DE | MXCSR_IE) |
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169 | |
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170 | #define FPSR_B (1<<15) /* FPU busy */ |
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171 | #define FPSR_C3 (1<<14) /* Cond code C3 */ |
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172 | #define FPSR_TOP(x) (((x)&7)<<11) /* TOP */ |
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173 | #define FPSR_C2 (1<<10) /* Cond code C2 */ |
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174 | #define FPSR_C1 (1<< 9) /* Cond code C1 */ |
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175 | #define FPSR_C0 (1<< 8) /* Cond code C0 */ |
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176 | #define FPSR_ES (1<< 7) /* Error summary */ |
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177 | #define FPSR_SF (1<< 6) /* Stack fault */ |
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178 | #define FPSR_PE (1<< 5) /* Precision flg */ |
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179 | #define FPSR_UE (1<< 4) /* Underflow flg */ |
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180 | #define FPSR_OE (1<< 3) /* Overflow flg */ |
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181 | #define FPSR_ZE (1<< 2) /* Divbyzero flg */ |
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182 | #define FPSR_DE (1<< 1) /* Denormal flg */ |
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183 | #define FPSR_IE (1<< 0) /* Invalidop flg */ |
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184 | |
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185 | #define FPCW_X (1<<12) /* Infinity ctrl */ |
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186 | #define FPCW_RC(x) (((x)&3)<<10) /* Rounding ctrl */ |
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187 | #define FPCW_PC(x) (((x)&3)<< 8) /* Precision ctl */ |
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188 | #define FPCW_PM (1<< 5) /* Precision msk */ |
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189 | #define FPCW_UM (1<< 4) /* Underflow msk */ |
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190 | #define FPCW_OM (1<< 3) /* Overflow msk */ |
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191 | #define FPCW_ZM (1<< 2) /* Divbyzero msk */ |
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192 | #define FPCW_DM (1<< 1) /* Denormal msk */ |
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193 | #define FPCW_IM (1<< 0) /* Invalidop msk */ |
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194 | |
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195 | #define FPCW_ALLM (FPCW_PM | FPCW_UM | FPCW_OM | FPCW_ZM | FPCW_DM | FPCW_IM) |
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196 | #define FPSR_ALLE (FPSR_ES | FPSR_SF | FPSR_PE | FPSR_UE | FPSR_OE | FPSR_ZE | FPSR_DE | FPSR_IE) |
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197 | |
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198 | /* Store 'double' into 80-bit register image */ |
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199 | void |
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200 | fp_st1(uint8_t (*p_dst)[10], double v) |
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201 | { |
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202 | asm volatile("fstpt %0":"=m"(*p_dst):"t"(v):"st"); |
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203 | } |
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204 | |
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205 | /* Store 'double' into 80-bit register image #i in context */ |
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206 | void |
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207 | fp_st(Context_Control_sse *p_ctxt, int i, double v) |
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208 | { |
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209 | fp_st1(&p_ctxt->fp_mmregs[i].fpreg,v); |
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210 | } |
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211 | |
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212 | /* Load 'double' from 80-bit register image */ |
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213 | double |
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214 | fp_ld1(uint8_t (*p_src)[10]) |
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215 | { |
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216 | double v; |
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217 | |
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218 | asm volatile("fldt %1":"=t"(v):"m"((*p_src)[0]),"m"(*p_src)); |
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219 | return v; |
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220 | } |
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221 | |
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222 | /* Load 'double' from 80-bit register image #i in context */ |
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223 | double |
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224 | fp_ld(Context_Control_sse *p_ctxt, int i) |
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225 | { |
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226 | return fp_ld1(&p_ctxt->fp_mmregs[i].fpreg); |
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227 | } |
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228 | |
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229 | #define FPUCLOBBER \ |
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230 | "st","st(1)","st(2)","st(3)", \ |
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231 | "st(4)","st(5)","st(6)","st(7)",\ |
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232 | "fpsr","fpcr" |
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233 | |
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234 | /* There seems to be no way to say that mxcsr was clobbered */ |
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235 | |
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236 | #define SSECLOBBER \ |
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237 | "xmm0","xmm1","xmm2","xmm3", \ |
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238 | "xmm4","xmm5","xmm6","xmm7" |
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239 | |
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240 | static void |
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241 | sse_clobber(uint32_t x) |
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242 | { |
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243 | __v32 v = { x, x, x, x }; |
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244 | asm volatile ( |
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245 | " movdqa %0, %%xmm0 \n" |
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246 | " movdqa %%xmm0, %%xmm1 \n" |
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247 | " movdqa %%xmm0, %%xmm2 \n" |
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248 | " movdqa %%xmm0, %%xmm3 \n" |
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249 | " movdqa %%xmm0, %%xmm4 \n" |
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250 | " movdqa %%xmm0, %%xmm5 \n" |
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251 | " movdqa %%xmm0, %%xmm6 \n" |
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252 | " movdqa %%xmm0, %%xmm7 \n" |
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253 | : |
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254 | :"m"(v) |
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255 | :SSECLOBBER |
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256 | ); |
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257 | } |
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258 | |
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259 | void |
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260 | all_clobber(uint32_t v1, uint32_t v2); |
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261 | |
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262 | __asm__ ( |
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263 | "all_clobber: \n" |
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264 | " finit \n" |
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265 | " movq 0(%esp), %xmm0 \n" |
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266 | " punpcklqdq %xmm0, %xmm0 \n" |
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267 | " movdqa %xmm0, %xmm1 \n" |
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268 | " movdqa %xmm0, %xmm2 \n" |
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269 | " movdqa %xmm0, %xmm3 \n" |
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270 | " movdqa %xmm0, %xmm4 \n" |
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271 | " movdqa %xmm0, %xmm5 \n" |
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272 | " movdqa %xmm0, %xmm6 \n" |
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273 | " movdqa %xmm0, %xmm7 \n" |
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274 | " ret \n" |
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275 | ); |
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276 | |
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277 | /* Clear FPU and save FPU/SSE registers to context area */ |
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278 | |
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279 | void |
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280 | init_ctxt(Context_Control_sse *p_ctxt); |
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281 | |
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282 | __asm__ ( |
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283 | "init_ctxt: \n" |
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284 | " finit \n" |
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285 | " mov 4(%esp), %eax\n" |
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286 | " fxsave (%eax) \n" |
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287 | " fwait \n" |
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288 | " ret \n" |
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289 | ); |
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290 | |
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291 | /* Save FPU/SSE registers to context area */ |
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292 | |
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293 | static void |
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294 | stor_ctxt(Context_Control_sse *p_ctxt) |
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295 | { |
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296 | memset(p_ctxt, 0, sizeof(*p_ctxt)); |
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297 | asm volatile( |
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298 | /* " finit \n" */ |
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299 | " fxsave %0 \n" |
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300 | " fwait \n" |
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301 | : "=m"(*p_ctxt) |
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302 | : |
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303 | : FPUCLOBBER |
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304 | ); |
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305 | } |
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306 | |
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307 | #define H08 "0x%02"PRIx8 |
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308 | #define H16 "0x%04"PRIx16 |
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309 | #define H32 "0x%08"PRIx32 |
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310 | |
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311 | #define F16 "mismatch ("H16" != "H16")\n" |
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312 | |
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313 | #define FLDCMP(fld, fmt) \ |
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314 | if ( a->fld != b->fld ) { \ |
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315 | rval = 1; \ |
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316 | if ( !quiet ) \ |
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317 | fprintf(stderr,#fld" mismatch ("fmt" != "fmt")\n",a->fld, b->fld); \ |
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318 | } |
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319 | |
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320 | #define FLTCMP(i) \ |
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321 | do { \ |
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322 | if ( ( (a->ftw ^ b->ftw) & (1<<i)) \ |
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323 | || ( (a->ftw & b->ftw & (1<<i)) && \ |
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324 | memcmp(a->fp_mmregs[i].fpreg, \ |
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325 | b->fp_mmregs[i].fpreg, \ |
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326 | sizeof(a->fp_mmregs[i].fpreg)) \ |
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327 | ) \ |
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328 | ) { \ |
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329 | rval = 1; \ |
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330 | if ( !quiet ) { \ |
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331 | double fa = fp_ld(a, i); \ |
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332 | double fb = fp_ld(b, i); \ |
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333 | if ( ((a->ftw ^ b->ftw) & (1<<i)) ) \ |
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334 | fprintf(stderr,"fpreg[%u] TAG mismatch (%u != %u)\n",i,(a->ftw & (1<<i)) ? 1 : 0,(b->ftw & (1<<i)) ? 1 : 0); \ |
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335 | else \ |
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336 | fprintf(stderr,"fpreg[%u] mismatch (%g != %g)\n",i,fa,fb); \ |
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337 | } \ |
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338 | } \ |
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339 | } while (0) |
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340 | |
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341 | #define XMMCMP(i) \ |
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342 | do { \ |
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343 | if ( memcmp(&a->xmmregs[i], \ |
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344 | &b->xmmregs[i], \ |
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345 | sizeof(a->xmmregs[i])) \ |
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346 | ) { \ |
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347 | rval = 1; \ |
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348 | if ( !quiet ) { \ |
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349 | int _jj; \ |
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350 | fprintf(stderr,"xmmreg[%u] mismatch:\n", i); \ |
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351 | fprintf(stderr," "); \ |
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352 | for (_jj=0; _jj<16; _jj++) \ |
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353 | fprintf(stderr,"%02x ",a->xmmregs[i][_jj]); \ |
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354 | fprintf(stderr,"\n !=\n"); \ |
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355 | fprintf(stderr," "); \ |
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356 | for (_jj=0; _jj<16; _jj++) \ |
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357 | fprintf(stderr,"%02x ",b->xmmregs[i][_jj]); \ |
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358 | fprintf(stderr,"\n"); \ |
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359 | } \ |
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360 | } \ |
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361 | } while (0) |
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362 | |
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363 | |
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364 | /* Compare two FPU/SSE context areas and flag differences; |
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365 | * RETURNS: zero if the contexts match and nonzero otherwise |
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366 | */ |
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367 | static int |
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368 | cmp_ctxt(Context_Control_sse *a, Context_Control_sse *b, int quiet) |
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369 | { |
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370 | int rval = 0; |
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371 | int i; |
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372 | FLDCMP(fcw,H16); |
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373 | FLDCMP(fsw,H16); |
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374 | FLDCMP(ftw,H08); |
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375 | FLDCMP(fop,H16); |
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376 | FLDCMP(fpu_ip,H32); |
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377 | FLDCMP(cs,H16); |
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378 | FLDCMP(fpu_dp,H32); |
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379 | FLDCMP(ds,H16); |
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380 | FLDCMP(mxcsr,H32); |
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381 | FLDCMP(mxcsr_mask,H32); |
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382 | for ( i=0; i<8; i++ ) { |
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383 | FLTCMP(i); |
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384 | } |
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385 | for ( i=0; i<8; i++ ) { |
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386 | XMMCMP(i); |
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387 | } |
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388 | return rval; |
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389 | } |
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390 | |
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391 | /* Possible arguments to exc_raise() */ |
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392 | |
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393 | #define FP_EXC 0 |
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394 | #define IRQ_EXC 1 |
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395 | #define SSE_EXC -1 |
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396 | |
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397 | /* Check stack alignment by raising the interrupt from a |
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398 | * non-16-byte aligned section of code. The exception/IRQ |
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399 | * handler must align the stack and SSE context area |
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400 | * properly or it will crash. |
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401 | */ |
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402 | #define __INTRAISE(x) " int $32+"#x" \n" |
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403 | #define INTRAISE(x) __INTRAISE(x) |
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404 | |
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405 | __asm__ ( |
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406 | "do_raise: \n" |
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407 | " fwait \n" |
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408 | " test %eax, %eax \n" |
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409 | " je 2f \n" |
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410 | " jl 1f \n" |
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411 | INTRAISE(SSE_TEST_IRQ) |
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412 | " jmp 2f \n" |
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413 | "1: sqrtps %xmm0, %xmm0 \n" |
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414 | "2: \n" |
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415 | " ret \n" |
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416 | ); |
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417 | |
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418 | #define SSE_TEST_HP_FAILED 1 |
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419 | #define SSE_TEST_FSPR_FAILED 2 |
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420 | #define SSE_TEST_CTXTCMP_FAILED 4 |
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421 | |
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422 | static const char *fail_msgs[] = { |
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423 | "Seems that HP task was not executing", |
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424 | "FPSR 'Invalid-operation' flag should be clear", |
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425 | "Restored context does NOT match the saved one", |
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426 | }; |
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427 | |
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428 | static void prstat(int st, const char *where) |
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429 | { |
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430 | int i,msk; |
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431 | for ( i=0, msk=1; i<sizeof(fail_msgs)/sizeof(fail_msgs[0]); i++, msk<<=1 ) { |
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432 | if ( (st & msk) ) { |
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433 | fprintf(stderr,"sse_test ERROR: %s (testing: %s)\n", fail_msgs[i], where); |
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434 | } |
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435 | } |
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436 | } |
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437 | |
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438 | int sse_test_debug = 0; |
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439 | |
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440 | static int |
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441 | exc_raise(int kind) |
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442 | { |
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443 | Context_Control_sse nctxt; |
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444 | Context_Control_sse octxt; |
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445 | Context_Control_sse orig_ctxt; |
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446 | int i,j,rval; |
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447 | double s2; |
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448 | uint16_t fsw; |
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449 | __vf f4 = { -1., -2., -3., -4. }; |
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450 | __vf tmp; |
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451 | __v32 sgn = { (1<<31), (1<<31), (1<<31), (1<<31) }; |
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452 | |
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453 | stor_ctxt(&octxt); |
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454 | |
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455 | octxt.fsw &= ~FPSR_ALLE; |
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456 | octxt.mxcsr &= ~MXCSR_ALLE; |
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457 | |
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458 | for ( i=0; i<8; i++ ) { |
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459 | fp_st(&octxt, i, (double)i+0.1); |
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460 | for (j=0; j<16; j++) { |
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461 | octxt.xmmregs[i][j]=(i<<4)+j; |
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462 | } |
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463 | } |
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464 | |
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465 | |
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466 | if ( SSE_EXC == kind ) { |
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467 | memcpy(octxt.xmmregs[0], &f4, sizeof(f4)); |
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468 | octxt.mxcsr &= ~MXCSR_IM; |
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469 | } |
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470 | |
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471 | /* set tags to 'valid' */ |
---|
472 | octxt.ftw = 0xff; |
---|
473 | |
---|
474 | /* enable 'invalid arg' exception */ |
---|
475 | octxt.fcw &= ~ ( FPCW_IM ); |
---|
476 | |
---|
477 | if ( FP_EXC == kind ) { |
---|
478 | octxt.fsw |= ( FPSR_IE | FPSR_ES ); |
---|
479 | } |
---|
480 | |
---|
481 | if ( sse_test_debug ) |
---|
482 | printk("RAISE (fsw was 0x%04x)\n", orig_ctxt.fsw); |
---|
483 | asm volatile( |
---|
484 | " fxsave %2 \n" |
---|
485 | #ifdef __rtems__ |
---|
486 | " movl %4, sse_test_check\n" |
---|
487 | #endif |
---|
488 | " fxrstor %3 \n" |
---|
489 | " call do_raise \n" |
---|
490 | #ifdef __rtems__ |
---|
491 | " movl sse_test_check, %1\n" |
---|
492 | #else |
---|
493 | " movl $0, %1 \n" |
---|
494 | #endif |
---|
495 | #ifdef TEST_MISMATCH |
---|
496 | " pxor %%xmm0, %%xmm0 \n" |
---|
497 | #endif |
---|
498 | " fxsave %0 \n" |
---|
499 | " fxrstor %2 \n" |
---|
500 | : "=m"(nctxt),"=&r"(rval),"=m"(orig_ctxt) |
---|
501 | : "m"(octxt), "i"(SSE_TEST_HP_FAILED),"a"(kind) |
---|
502 | : "xmm0" |
---|
503 | ); |
---|
504 | |
---|
505 | if ( ( FPSR_IE & nctxt.fsw ) ) { |
---|
506 | rval |= SSE_TEST_FSPR_FAILED; |
---|
507 | } |
---|
508 | if ( FP_EXC == kind ) |
---|
509 | nctxt.fsw |= (FPSR_IE | FPSR_ES); |
---|
510 | else if ( SSE_EXC == kind ) { |
---|
511 | tmp = __builtin_ia32_sqrtps( (__vf)(~sgn & (__v32)f4) ); |
---|
512 | /* sqrt raises PE; just clear it */ |
---|
513 | nctxt.mxcsr &= ~MXCSR_PE; |
---|
514 | memcpy( octxt.xmmregs[0], &tmp, sizeof(tmp) ); |
---|
515 | } |
---|
516 | |
---|
517 | if ( cmp_ctxt(&nctxt, &octxt, 0) ) { |
---|
518 | rval |= SSE_TEST_CTXTCMP_FAILED; |
---|
519 | } |
---|
520 | |
---|
521 | s2 = sqrt(2.0); |
---|
522 | |
---|
523 | asm volatile("fstsw %0":"=m"(fsw)); |
---|
524 | |
---|
525 | if ( sse_test_debug ) |
---|
526 | printf("sqrt(2): %f (FSTW: 0x%02"PRIx16")\n", sqrt(2.0), fsw); |
---|
527 | |
---|
528 | return rval; |
---|
529 | } |
---|
530 | |
---|
531 | #ifdef __rtems__ |
---|
532 | static void |
---|
533 | sse_test_ehdl(CPU_Exception_frame *p_f); |
---|
534 | |
---|
535 | rtems_id sse_test_sync = 0; |
---|
536 | cpuExcHandlerType sse_test_ohdl = 0; |
---|
537 | |
---|
538 | CPU_Exception_frame *sse_test_frame = 0; |
---|
539 | volatile int sse_test_check = SSE_TEST_HP_FAILED; |
---|
540 | unsigned sse_tests = 0; |
---|
541 | |
---|
542 | rtems_task |
---|
543 | sse_test_hp_task(rtems_task_argument arg) |
---|
544 | { |
---|
545 | rtems_id sync = (rtems_id)arg; |
---|
546 | |
---|
547 | uint16_t fp_cw; |
---|
548 | uint32_t mxcsr; |
---|
549 | rtems_status_code sc; |
---|
550 | const char * msgs[] = {"FPU_EXC", "SSE_EXC", "IRQ_EXC"}; |
---|
551 | int i; |
---|
552 | |
---|
553 | /* verify that FPU control word is default value */ |
---|
554 | asm volatile("fstcw %0":"=m"(fp_cw)); |
---|
555 | if ( fp_cw != _CPU_Null_fp_context.fpucw ) { |
---|
556 | fprintf( |
---|
557 | stderr, |
---|
558 | "ERROR: FPU CW initialization mismatch: got 0x%04"PRIx16"; expected 0x%04"PRIx16"\n", |
---|
559 | fp_cw, |
---|
560 | _CPU_Null_fp_context.fpucw |
---|
561 | ); |
---|
562 | } |
---|
563 | |
---|
564 | /* check MXCSR default value */ |
---|
565 | asm volatile("stmxcsr %0":"=m"(mxcsr)); |
---|
566 | if ( mxcsr != _CPU_Null_fp_context.mxcsr ) { |
---|
567 | fprintf( |
---|
568 | stderr, |
---|
569 | "ERROR: MXCSR initialization mismatch: got 0x%08"PRIx32"; expected 0x%08"PRIx32"\n", |
---|
570 | mxcsr, |
---|
571 | _CPU_Null_fp_context.mxcsr |
---|
572 | ); |
---|
573 | } |
---|
574 | |
---|
575 | |
---|
576 | for (i=0; i<sizeof(msgs)/sizeof(msgs[0]); i++ ) { |
---|
577 | if ( ( sse_tests & (1<<i) ) ) { |
---|
578 | if ( sse_test_debug ) |
---|
579 | printk("HP task will now block for %s\n",msgs[i]); |
---|
580 | |
---|
581 | /* Blocking here lets the low-priority task continue */ |
---|
582 | sc = rtems_semaphore_obtain(sync, RTEMS_WAIT, 500); |
---|
583 | |
---|
584 | all_clobber(0xaffeaffe, 0xcafecafe); |
---|
585 | |
---|
586 | if ( RTEMS_SUCCESSFUL != sc ) { |
---|
587 | rtems_error(sc,"ERROR: sse_test hp task wasn't notified of exception\n"); |
---|
588 | goto bail; |
---|
589 | } |
---|
590 | |
---|
591 | /* set flag indicating that we executed until here */ |
---|
592 | sse_test_check = 0; |
---|
593 | } |
---|
594 | } |
---|
595 | |
---|
596 | bail: |
---|
597 | rtems_task_suspend(RTEMS_SELF); |
---|
598 | } |
---|
599 | |
---|
600 | /* Flags to skip individual tests */ |
---|
601 | #define SSE_TEST_FPU_EXC (1<<0) |
---|
602 | #define SSE_TEST_SSE_EXC (1<<1) |
---|
603 | #define SSE_TEST_IRQ_EXC (1<<2) |
---|
604 | |
---|
605 | #define SSE_TEST_ALL 7 |
---|
606 | |
---|
607 | /* If this flag is given the executing task is not deleted |
---|
608 | * when the test finishes. This is useful if you want to |
---|
609 | * execute from a shell or similar. |
---|
610 | */ |
---|
611 | #define SSE_TEST_NO_DEL (1<<0) |
---|
612 | |
---|
613 | /* Task arg is bitmask of these flags */ |
---|
614 | rtems_task |
---|
615 | sse_test_lp_task(rtems_task_argument arg) |
---|
616 | { |
---|
617 | rtems_id hp_task = 0; |
---|
618 | rtems_status_code sc; |
---|
619 | rtems_task_priority pri; |
---|
620 | uint16_t fp_cw,fp_cw_set; |
---|
621 | uint32_t mxcsr, mxcsr_set; |
---|
622 | rtems_irq_connect_data irqd; |
---|
623 | int flags = (int)arg; |
---|
624 | int st; |
---|
625 | int errs = 0; |
---|
626 | |
---|
627 | sse_tests = SSE_TEST_ALL & ~(flags>>1); |
---|
628 | |
---|
629 | sse_test_ohdl = 0; |
---|
630 | |
---|
631 | fp_cw_set = _CPU_Null_fp_context.fpucw | FPCW_RC(3) ; |
---|
632 | mxcsr_set = _CPU_Null_fp_context.mxcsr | MXCSR_RC(3) ; |
---|
633 | asm volatile("ldmxcsr %0"::"m"(mxcsr_set)); |
---|
634 | asm volatile("fldcw %0"::"m"(fp_cw_set)); |
---|
635 | |
---|
636 | sc = rtems_semaphore_create( |
---|
637 | rtems_build_name('s','s','e','S'), |
---|
638 | 0, |
---|
639 | RTEMS_SIMPLE_BINARY_SEMAPHORE, |
---|
640 | 0, |
---|
641 | &sse_test_sync |
---|
642 | ); |
---|
643 | if ( RTEMS_SUCCESSFUL != sc ) { |
---|
644 | rtems_error(sc, "sse_test ERROR: creation of 'sync' semaphore failed"); |
---|
645 | errs++; |
---|
646 | goto bail; |
---|
647 | } |
---|
648 | |
---|
649 | rtems_task_set_priority( RTEMS_SELF, RTEMS_CURRENT_PRIORITY, &pri ); |
---|
650 | |
---|
651 | sc = rtems_task_create( |
---|
652 | rtems_build_name('s','s','e','H'), |
---|
653 | pri - 2, |
---|
654 | 20000, |
---|
655 | RTEMS_DEFAULT_MODES, |
---|
656 | RTEMS_FLOATING_POINT, |
---|
657 | &hp_task |
---|
658 | ); |
---|
659 | if ( RTEMS_SUCCESSFUL != sc ) { |
---|
660 | hp_task = 0; |
---|
661 | rtems_error( sc, "sse_test ERROR: creation of high-priority task failed"); |
---|
662 | errs++; |
---|
663 | goto bail; |
---|
664 | } |
---|
665 | |
---|
666 | sc = rtems_task_start( hp_task, sse_test_hp_task, (rtems_task_argument)sse_test_sync ); |
---|
667 | if ( RTEMS_SUCCESSFUL != sc ) { |
---|
668 | rtems_error( sc, "sse_test ERROR: start of high-priority task failed"); |
---|
669 | goto bail; |
---|
670 | } |
---|
671 | |
---|
672 | /* Test if FP/SSE context is saved/restored across an exception */ |
---|
673 | sse_test_ohdl = _currentExcHandler; |
---|
674 | _currentExcHandler = sse_test_ehdl; |
---|
675 | |
---|
676 | if ( (sse_tests & SSE_TEST_FPU_EXC) ) { |
---|
677 | if ( (st = exc_raise(FP_EXC)) ) { |
---|
678 | prstat(st,"FP_EXC"); |
---|
679 | errs++; |
---|
680 | } |
---|
681 | |
---|
682 | /* Test modified FPCW/MXCSR */ |
---|
683 | asm volatile("fstcw %0":"=m"(fp_cw)); |
---|
684 | asm volatile("stmxcsr %0":"=m"(mxcsr)); |
---|
685 | mxcsr &= ~(MXCSR_ALLE); |
---|
686 | if ( fp_cw != fp_cw_set ) { |
---|
687 | fprintf(stderr,"sse_test ERROR: FPCW mismatch (after FP_EXC): expected 0x%04"PRIx16", got 0x%04"PRIx16"\n", fp_cw_set, fp_cw); |
---|
688 | errs++; |
---|
689 | } |
---|
690 | if ( mxcsr != mxcsr_set ) { |
---|
691 | fprintf(stderr,"sse_test ERROR: MXCSR mismatch (after FP_EXC): expected 0x%08"PRIx32", got 0x%08"PRIx32"\n", mxcsr_set, mxcsr); |
---|
692 | errs++; |
---|
693 | } |
---|
694 | } |
---|
695 | |
---|
696 | if ( (sse_tests & SSE_TEST_SSE_EXC) ) { |
---|
697 | if ( (st = exc_raise(SSE_EXC)) ) { |
---|
698 | prstat(st, "SSE_EXC"); |
---|
699 | errs++; |
---|
700 | } |
---|
701 | |
---|
702 | /* Test modified FPCW/MXCSR */ |
---|
703 | asm volatile("fstcw %0":"=m"(fp_cw)); |
---|
704 | asm volatile("stmxcsr %0":"=m"(mxcsr)); |
---|
705 | mxcsr &= ~(MXCSR_ALLE); |
---|
706 | if ( fp_cw != fp_cw_set ) { |
---|
707 | fprintf(stderr,"sse_test ERROR: FPCW mismatch (after SSE_EXC): expected 0x%04"PRIx16", got 0x%04"PRIx16"\n", fp_cw_set, fp_cw); |
---|
708 | errs++; |
---|
709 | } |
---|
710 | if ( mxcsr != mxcsr_set ) { |
---|
711 | fprintf(stderr,"sse_test ERROR: MXCSR mismatch (after SSE_EXC): expected 0x%08"PRIx32", got 0x%08"PRIx32"\n", mxcsr_set, mxcsr); |
---|
712 | errs++; |
---|
713 | } |
---|
714 | } |
---|
715 | |
---|
716 | |
---|
717 | if ( (sse_tests & SSE_TEST_IRQ_EXC) ) { |
---|
718 | memset( &irqd, 0, sizeof(irqd) ); |
---|
719 | irqd.name = SSE_TEST_IRQ; |
---|
720 | irqd.hdl = (void*)sse_test_ehdl; |
---|
721 | irqd.handle = 0; |
---|
722 | |
---|
723 | if ( ! BSP_install_rtems_irq_handler( &irqd ) ) { |
---|
724 | fprintf(stderr, "sse_test ERROR: Unable to install ISR\n"); |
---|
725 | errs++; |
---|
726 | goto bail; |
---|
727 | } |
---|
728 | |
---|
729 | /* Test if FP/SSE context is saved/restored across an interrupt */ |
---|
730 | if ( (st = exc_raise(IRQ_EXC)) ) { |
---|
731 | prstat(st, "IRQ"); |
---|
732 | errs++; |
---|
733 | } |
---|
734 | |
---|
735 | if ( ! BSP_remove_rtems_irq_handler( &irqd ) ) { |
---|
736 | fprintf(stderr, "sse_test ERROR: Unable to uninstall ISR\n"); |
---|
737 | } |
---|
738 | |
---|
739 | /* Test modified FPCW/MXCSR */ |
---|
740 | asm volatile("fstcw %0":"=m"(fp_cw)); |
---|
741 | asm volatile("stmxcsr %0":"=m"(mxcsr)); |
---|
742 | mxcsr &= ~(MXCSR_ALLE); |
---|
743 | if ( fp_cw != fp_cw_set ) { |
---|
744 | fprintf(stderr,"sse_test ERROR: FPCW mismatch (after IRQ): expected 0x%04"PRIx16", got 0x%04"PRIx16"\n", fp_cw_set, fp_cw); |
---|
745 | errs++; |
---|
746 | } |
---|
747 | if ( mxcsr != mxcsr_set ) { |
---|
748 | fprintf(stderr,"sse_test ERROR: MXCSR mismatch (after IRQ): expected 0x%08"PRIx32", got 0x%08"PRIx32"\n", mxcsr_set, mxcsr); |
---|
749 | errs++; |
---|
750 | } |
---|
751 | } |
---|
752 | |
---|
753 | |
---|
754 | bail: |
---|
755 | /* Wait for console to calm down... */ |
---|
756 | rtems_task_wake_after(5); |
---|
757 | fprintf(stderr,"SSE/FPU Test %s (%u errors)\n", errs ? "FAILED":"PASSED", errs); |
---|
758 | if ( sse_test_ohdl ) { |
---|
759 | _currentExcHandler = sse_test_ohdl; |
---|
760 | sse_test_ohdl = 0; |
---|
761 | } |
---|
762 | if ( sse_test_sync ) |
---|
763 | rtems_semaphore_delete( sse_test_sync ); |
---|
764 | sse_test_sync = 0; |
---|
765 | if ( hp_task ) |
---|
766 | rtems_task_delete( hp_task ); |
---|
767 | |
---|
768 | if ( ! (flags & SSE_TEST_NO_DEL) ) |
---|
769 | rtems_task_delete( RTEMS_SELF ); |
---|
770 | } |
---|
771 | |
---|
772 | static void |
---|
773 | sse_test_ehdl(CPU_Exception_frame *p_f) |
---|
774 | { |
---|
775 | int i,j,start = 0; |
---|
776 | int mismatch; |
---|
777 | __vf f4; |
---|
778 | |
---|
779 | if ( p_f ) { |
---|
780 | printk("Got exception #%u\n", p_f->idtIndex); |
---|
781 | printk("EIP: 0x%08x, ESP: 0x%08x\n", p_f->eip, p_f->esp0); |
---|
782 | printk("TID: 0x%08x\n", _Thread_Executing->Object.id); |
---|
783 | |
---|
784 | if ( ! p_f->fp_ctxt ) { |
---|
785 | printk("ERROR: NO FP/SSE CONTEXT ATTACHED ??\n"); |
---|
786 | sse_test_ohdl(p_f); |
---|
787 | } |
---|
788 | if ( 16 == p_f->idtIndex ) { |
---|
789 | printk("Resetting FP status (0x%04"PRIx16")\n", p_f->fp_ctxt->fsw); |
---|
790 | p_f->fp_ctxt->fsw = 0; |
---|
791 | } else if ( 19 == p_f->idtIndex ) { |
---|
792 | start = 1; |
---|
793 | memcpy(&f4, p_f->fp_ctxt->xmmregs[0], sizeof(f4)); |
---|
794 | f4 = -f4; |
---|
795 | memcpy(p_f->fp_ctxt->xmmregs[0], &f4, sizeof(f4)); |
---|
796 | p_f->fp_ctxt->mxcsr &= ~MXCSR_ALLE; |
---|
797 | } else { |
---|
798 | printk("(skipping non-FP exception)\n"); |
---|
799 | sse_test_ohdl(p_f); |
---|
800 | } |
---|
801 | |
---|
802 | printk("Checking XMM regs -- "); |
---|
803 | for ( mismatch=0, i=start; i<8; i++ ) { |
---|
804 | for ( j=0; j<16; j++ ) { |
---|
805 | if ( p_f->fp_ctxt->xmmregs[i][j] != ((i<<4) | j) ) |
---|
806 | mismatch++; |
---|
807 | } |
---|
808 | } |
---|
809 | if ( mismatch ) { |
---|
810 | printk("%u mismatches; dump:\n", mismatch); |
---|
811 | for ( i=0; i<8; i++ ) { |
---|
812 | for ( j=0; j<16; j++ ) { |
---|
813 | printk("0x%02x ", p_f->fp_ctxt->xmmregs[i][j]); |
---|
814 | } |
---|
815 | printk("\n"); |
---|
816 | } |
---|
817 | } else { |
---|
818 | printk("OK\n"); |
---|
819 | } |
---|
820 | } else { |
---|
821 | printk("IRQ %u\n", SSE_TEST_IRQ); |
---|
822 | } |
---|
823 | printk("Clobbering FPU/SSE state\n"); |
---|
824 | asm volatile("finit"); |
---|
825 | sse_clobber(0xdeadbeef); |
---|
826 | printk("Notifying task\n"); |
---|
827 | rtems_semaphore_release( sse_test_sync ); |
---|
828 | } |
---|
829 | |
---|
830 | #else |
---|
831 | |
---|
832 | /* Code using signals for testing under linux; unfortunately, 32-bit |
---|
833 | * linux seems to pass no SSE context info to the sigaction... |
---|
834 | */ |
---|
835 | |
---|
836 | #include <signal.h> |
---|
837 | #include <ucontext.h> |
---|
838 | |
---|
839 | #define MKCASE(X) case FPE_##X: msg="FPE_"#X; break; |
---|
840 | |
---|
841 | #define CLRXMM(i) __asm__ volatile("pxor %%xmm"#i", %%xmm"#i:::"xmm"#i) |
---|
842 | |
---|
843 | static void |
---|
844 | fpe_act(int signum, siginfo_t *p_info, void *arg3) |
---|
845 | { |
---|
846 | ucontext_t *p_ctxt = arg3; |
---|
847 | const char *msg = "FPE_UNKNOWN"; |
---|
848 | uint16_t *p_fst; |
---|
849 | |
---|
850 | if ( SIGFPE != signum ) { |
---|
851 | fprintf(stderr,"WARNING: fpe_act handles SIGFPE\n"); |
---|
852 | return; |
---|
853 | } |
---|
854 | switch ( p_info->si_code ) { |
---|
855 | default: |
---|
856 | fprintf(stderr,"WARNING: fpe_act got unkown code %u\n", p_info->si_code); |
---|
857 | return; |
---|
858 | MKCASE(INTDIV); |
---|
859 | MKCASE(INTOVF); |
---|
860 | MKCASE(FLTDIV); |
---|
861 | MKCASE(FLTOVF); |
---|
862 | MKCASE(FLTUND); |
---|
863 | MKCASE(FLTRES); |
---|
864 | MKCASE(FLTINV); |
---|
865 | MKCASE(FLTSUB); |
---|
866 | } |
---|
867 | fprintf(stderr,"Got SIGFPE (%s) @%p\n", msg, p_info->si_addr); |
---|
868 | #ifdef __linux__ |
---|
869 | fprintf(stderr,"Resetting FP status 0x%02lx\n", p_ctxt->uc_mcontext.fpregs->sw); |
---|
870 | p_ctxt->uc_mcontext.fpregs->sw = 0; |
---|
871 | #ifdef TEST_MISMATCH |
---|
872 | fp_st1((void*)&p_ctxt->uc_mcontext.fpregs->_st[3],2.345); |
---|
873 | #endif |
---|
874 | #endif |
---|
875 | |
---|
876 | /* Clear FPU; if context is properly saved/restored around exception |
---|
877 | * then this shouldn't disturb the register contents of the interrupted |
---|
878 | * task/process. |
---|
879 | */ |
---|
880 | asm volatile("finit"); |
---|
881 | sse_clobber(0xdeadbeef); |
---|
882 | } |
---|
883 | |
---|
884 | static void |
---|
885 | test(void) |
---|
886 | { |
---|
887 | Context_Control_sse ctxt; |
---|
888 | |
---|
889 | stor_ctxt(&ctxt); |
---|
890 | printf("FPCW: 0x%"PRIx16"\nFPSW: 0x%"PRIx16"\n", ctxt.fcw, ctxt.fsw); |
---|
891 | printf("FTAG: 0x%"PRIx8"\n",ctxt.ftw); |
---|
892 | } |
---|
893 | |
---|
894 | int |
---|
895 | main(int argc, char **argv) |
---|
896 | { |
---|
897 | struct sigaction a1, a2; |
---|
898 | uint32_t mxcsr; |
---|
899 | |
---|
900 | memset(&a1, 0, sizeof(a1)); |
---|
901 | |
---|
902 | a1.sa_sigaction = fpe_act; |
---|
903 | a1.sa_flags = SA_SIGINFO; |
---|
904 | |
---|
905 | if ( sigaction(SIGFPE, &a1, &a2) ) { |
---|
906 | perror("sigaction"); |
---|
907 | return 1; |
---|
908 | } |
---|
909 | |
---|
910 | asm volatile("stmxcsr %0":"=m"(mxcsr)); |
---|
911 | printf("MXCSR: 0x%08"PRIx32"\n", mxcsr); |
---|
912 | |
---|
913 | test(); |
---|
914 | exc_raise(0); |
---|
915 | return 0; |
---|
916 | } |
---|
917 | #endif |
---|
918 | |
---|
919 | /* Helpers to access CR4 and MXCSR */ |
---|
920 | |
---|
921 | uint32_t |
---|
922 | mfcr4() |
---|
923 | { |
---|
924 | uint32_t rval; |
---|
925 | asm volatile("mov %%cr4, %0":"=r"(rval)); |
---|
926 | return rval; |
---|
927 | } |
---|
928 | |
---|
929 | void |
---|
930 | mtcr4(uint32_t rval) |
---|
931 | { |
---|
932 | asm volatile("mov %0, %%cr4"::"r"(rval)); |
---|
933 | } |
---|
934 | |
---|
935 | uint32_t |
---|
936 | mfmxcsr() |
---|
937 | { |
---|
938 | uint32_t rval; |
---|
939 | asm volatile("stmxcsr %0":"=m"(rval)); |
---|
940 | return rval; |
---|
941 | } |
---|
942 | |
---|
943 | void |
---|
944 | mtmxcsr(uint32_t rval) |
---|
945 | { |
---|
946 | asm volatile("ldmxcsr %0"::"m"(rval)); |
---|
947 | } |
---|
948 | |
---|
949 | |
---|
950 | float |
---|
951 | sseraise() |
---|
952 | { |
---|
953 | __vf f4={-2., -2., -2. -2.}; |
---|
954 | float f; |
---|
955 | f4 = __builtin_ia32_sqrtps( f4 ); |
---|
956 | memcpy(&f,&f4,sizeof(f)); |
---|
957 | return f; |
---|
958 | } |
---|