1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Intel I386 CPU Dependent Source |
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5 | * |
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6 | * This include file contains information pertaining to the Intel |
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7 | * i386 processor. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * COPYRIGHT (c) 1989-2011. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #ifndef _RTEMS_SCORE_CPU_H |
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20 | #define _RTEMS_SCORE_CPU_H |
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21 | |
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22 | #ifndef ASM |
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23 | #include <string.h> /* for memcpy */ |
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24 | #endif |
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25 | |
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26 | #ifdef __cplusplus |
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27 | extern "C" { |
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28 | #endif |
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29 | |
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30 | #include <rtems/score/types.h> |
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31 | #include <rtems/score/i386.h> |
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32 | |
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33 | #ifndef ASM |
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34 | #include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ |
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35 | #include <rtems/score/registers.h> /* formerly part of libcpu */ |
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36 | #endif |
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37 | |
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38 | /* conditional compilation parameters */ |
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39 | |
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40 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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41 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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42 | |
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43 | /* |
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44 | * Does the CPU follow the simple vectored interrupt model? |
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45 | * |
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46 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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47 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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48 | * table |
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49 | * |
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50 | * PowerPC Specific Information: |
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51 | * |
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52 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
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53 | * They do not use the simple vectored interrupt model. |
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54 | */ |
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55 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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56 | |
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57 | /* |
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58 | * i386 has an RTEMS allocated and managed interrupt stack. |
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59 | */ |
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60 | |
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61 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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62 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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63 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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64 | |
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65 | /* |
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66 | * Does the RTEMS invoke the user's ISR with the vector number and |
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67 | * a pointer to the saved interrupt frame (1) or just the vector |
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68 | * number (0)? |
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69 | */ |
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70 | |
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71 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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72 | |
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73 | /* |
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74 | * Some family members have no FP, some have an FPU such as the i387 |
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75 | * for the i386, others have it built in (i486DX, Pentium). |
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76 | */ |
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77 | |
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78 | #ifdef __SSE__ |
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79 | #define CPU_HARDWARE_FP TRUE |
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80 | #define CPU_SOFTWARE_FP FALSE |
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81 | |
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82 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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83 | #define CPU_IDLE_TASK_IS_FP TRUE |
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84 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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85 | #else /* __SSE__ */ |
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86 | |
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87 | #if ( I386_HAS_FPU == 1 ) |
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88 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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89 | #else |
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90 | #define CPU_HARDWARE_FP FALSE |
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91 | #endif |
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92 | #define CPU_SOFTWARE_FP FALSE |
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93 | |
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94 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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95 | #define CPU_IDLE_TASK_IS_FP FALSE |
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96 | #if defined(RTEMS_SMP) |
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97 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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98 | #else |
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99 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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100 | #endif |
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101 | #endif /* __SSE__ */ |
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102 | |
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103 | #define CPU_STACK_GROWS_UP FALSE |
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104 | #define CPU_STRUCTURE_ALIGNMENT |
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105 | |
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106 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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107 | |
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108 | /* |
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109 | * Does this port provide a CPU dependent IDLE task implementation? |
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110 | * |
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111 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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112 | * must be provided and is the default IDLE thread body instead of |
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113 | * _CPU_Thread_Idle_body. |
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114 | * |
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115 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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116 | * not provide one. |
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117 | */ |
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118 | |
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119 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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120 | |
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121 | /* |
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122 | * Define what is required to specify how the network to host conversion |
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123 | * routines are handled. |
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124 | */ |
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125 | |
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126 | #define CPU_BIG_ENDIAN FALSE |
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127 | #define CPU_LITTLE_ENDIAN TRUE |
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128 | |
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129 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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130 | |
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131 | /* structures */ |
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132 | |
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133 | #ifndef ASM |
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134 | |
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135 | typedef struct { |
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136 | /* There is no CPU specific per-CPU state */ |
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137 | } CPU_Per_CPU_control; |
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138 | |
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139 | /* |
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140 | * Basic integer context for the i386 family. |
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141 | */ |
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142 | |
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143 | typedef struct { |
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144 | uint32_t eflags; /* extended flags register */ |
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145 | void *esp; /* extended stack pointer register */ |
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146 | void *ebp; /* extended base pointer register */ |
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147 | uint32_t ebx; /* extended bx register */ |
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148 | uint32_t esi; /* extended source index register */ |
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149 | uint32_t edi; /* extended destination index flags register */ |
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150 | } Context_Control; |
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151 | |
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152 | #define _CPU_Context_Get_SP( _context ) \ |
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153 | (_context)->esp |
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154 | |
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155 | /* |
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156 | * FP context save area for the i387 numeric coprocessors. |
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157 | */ |
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158 | #ifdef __SSE__ |
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159 | /* All FPU and SSE registers are volatile; hence, as long |
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160 | * as we are within normally executing C code (including |
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161 | * a task switch) there is no need for saving/restoring |
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162 | * any of those registers. |
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163 | * We must save/restore the full FPU/SSE context across |
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164 | * interrupts and exceptions, however: |
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165 | * - after ISR execution a _Thread_Dispatch() may happen |
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166 | * and it is therefore necessary to save the FPU/SSE |
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167 | * registers to be restored when control is returned |
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168 | * to the interrupted task. |
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169 | * - gcc may implicitly use FPU/SSE instructions in |
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170 | * an ISR. |
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171 | * |
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172 | * Even though there is no explicit mentioning of the FPU |
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173 | * control word in the SYSV ABI (i386) being non-volatile |
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174 | * we maintain MXCSR and the FPU control-word for each task. |
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175 | */ |
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176 | typedef struct { |
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177 | uint32_t mxcsr; |
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178 | uint16_t fpucw; |
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179 | } Context_Control_fp; |
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180 | |
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181 | #else |
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182 | |
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183 | typedef struct { |
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184 | uint8_t fp_save_area[108]; /* context size area for I80387 */ |
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185 | /* 28 bytes for environment */ |
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186 | } Context_Control_fp; |
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187 | |
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188 | #endif |
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189 | |
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190 | |
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191 | /* |
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192 | * The following structure defines the set of information saved |
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193 | * on the current stack by RTEMS upon receipt of execptions. |
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194 | * |
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195 | * idtIndex is either the interrupt number or the trap/exception number. |
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196 | * faultCode is the code pushed by the processor on some exceptions. |
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197 | * |
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198 | * Since the first registers are directly pushed by the CPU they |
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199 | * may not respect 16-byte stack alignment, which is, however, |
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200 | * mandatory for the SSE register area. |
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201 | * Therefore, these registers are stored at an aligned address |
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202 | * and a pointer is stored in the CPU_Exception_frame. |
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203 | * If the executive was compiled without SSE support then |
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204 | * this pointer is NULL. |
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205 | */ |
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206 | |
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207 | struct Context_Control_sse; |
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208 | |
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209 | typedef struct { |
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210 | struct Context_Control_sse *fp_ctxt; |
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211 | uint32_t edi; |
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212 | uint32_t esi; |
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213 | uint32_t ebp; |
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214 | uint32_t esp0; |
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215 | uint32_t ebx; |
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216 | uint32_t edx; |
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217 | uint32_t ecx; |
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218 | uint32_t eax; |
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219 | uint32_t idtIndex; |
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220 | uint32_t faultCode; |
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221 | uint32_t eip; |
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222 | uint32_t cs; |
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223 | uint32_t eflags; |
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224 | } CPU_Exception_frame; |
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225 | |
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226 | #ifdef __SSE__ |
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227 | typedef struct Context_Control_sse { |
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228 | uint16_t fcw; |
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229 | uint16_t fsw; |
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230 | uint8_t ftw; |
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231 | uint8_t res_1; |
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232 | uint16_t fop; |
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233 | uint32_t fpu_ip; |
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234 | uint16_t cs; |
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235 | uint16_t res_2; |
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236 | uint32_t fpu_dp; |
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237 | uint16_t ds; |
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238 | uint16_t res_3; |
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239 | uint32_t mxcsr; |
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240 | uint32_t mxcsr_mask; |
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241 | struct { |
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242 | uint8_t fpreg[10]; |
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243 | uint8_t res_4[ 6]; |
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244 | } fp_mmregs[8]; |
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245 | uint8_t xmmregs[8][16]; |
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246 | uint8_t res_5[224]; |
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247 | } Context_Control_sse |
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248 | __attribute__((aligned(16))) |
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249 | ; |
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250 | #endif |
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251 | |
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252 | typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); |
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253 | extern cpuExcHandlerType _currentExcHandler; |
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254 | extern void rtems_exception_init_mngt(void); |
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255 | |
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256 | /* |
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257 | * This port does not pass any frame info to the |
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258 | * interrupt handler. |
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259 | */ |
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260 | |
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261 | typedef void CPU_Interrupt_frame; |
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262 | |
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263 | typedef enum { |
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264 | I386_EXCEPTION_DIVIDE_BY_ZERO = 0, |
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265 | I386_EXCEPTION_DEBUG = 1, |
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266 | I386_EXCEPTION_NMI = 2, |
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267 | I386_EXCEPTION_BREAKPOINT = 3, |
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268 | I386_EXCEPTION_OVERFLOW = 4, |
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269 | I386_EXCEPTION_BOUND = 5, |
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270 | I386_EXCEPTION_ILLEGAL_INSTR = 6, |
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271 | I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, |
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272 | I386_EXCEPTION_DOUBLE_FAULT = 8, |
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273 | I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, |
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274 | I386_EXCEPTION_INVALID_TSS = 10, |
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275 | I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, |
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276 | I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, |
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277 | I386_EXCEPTION_GENERAL_PROT_ERR = 13, |
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278 | I386_EXCEPTION_PAGE_FAULT = 14, |
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279 | I386_EXCEPTION_INTEL_RES15 = 15, |
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280 | I386_EXCEPTION_FLOAT_ERROR = 16, |
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281 | I386_EXCEPTION_ALIGN_CHECK = 17, |
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282 | I386_EXCEPTION_MACHINE_CHECK = 18, |
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283 | I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ |
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284 | |
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285 | } Intel_symbolic_exception_name; |
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286 | |
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287 | |
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288 | /* |
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289 | * context size area for floating point |
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290 | * |
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291 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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292 | */ |
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293 | |
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294 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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295 | |
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296 | /* variables */ |
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297 | |
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298 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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299 | |
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300 | #endif /* ASM */ |
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301 | |
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302 | /* constants */ |
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303 | |
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304 | /* |
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305 | * This defines the number of levels and the mask used to pick those |
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306 | * bits out of a thread mode. |
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307 | */ |
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308 | |
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309 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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310 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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311 | |
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312 | /* |
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313 | * extra stack required by the MPCI receive server thread |
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314 | */ |
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315 | |
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316 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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317 | |
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318 | /* |
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319 | * i386 family supports 256 distinct vectors. |
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320 | */ |
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321 | |
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322 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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323 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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324 | |
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325 | /* |
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326 | * This is defined if the port has a special way to report the ISR nesting |
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327 | * level. Most ports maintain the variable _ISR_Nest_level. |
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328 | */ |
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329 | |
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330 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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331 | |
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332 | /* |
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333 | * Minimum size of a thread's stack. |
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334 | */ |
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335 | |
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336 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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337 | |
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338 | #define CPU_SIZEOF_POINTER 4 |
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339 | |
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340 | /* |
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341 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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342 | */ |
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343 | |
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344 | #define CPU_ALIGNMENT 4 |
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345 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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346 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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347 | |
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348 | /* |
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349 | * On i386 thread stacks require no further alignment after allocation |
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350 | * from the Workspace. However, since gcc maintains 16-byte alignment |
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351 | * we try to respect that. If you find an option to let gcc squeeze |
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352 | * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still |
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353 | * doesn't waste much space since this only determines the *initial* |
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354 | * alignment. |
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355 | */ |
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356 | |
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357 | #define CPU_STACK_ALIGNMENT 16 |
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358 | |
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359 | /* macros */ |
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360 | |
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361 | #ifndef ASM |
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362 | /* |
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363 | * ISR handler macros |
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364 | * |
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365 | * These macros perform the following functions: |
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366 | * + initialize the RTEMS vector table |
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367 | * + disable all maskable CPU interrupts |
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368 | * + restore previous interrupt level (enable) |
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369 | * + temporarily restore interrupts (flash) |
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370 | * + set a particular level |
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371 | */ |
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372 | |
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373 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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374 | |
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375 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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376 | |
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377 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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378 | |
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379 | #define _CPU_ISR_Set_level( _new_level ) \ |
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380 | { \ |
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381 | if ( _new_level ) __asm__ volatile ( "cli" ); \ |
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382 | else __asm__ volatile ( "sti" ); \ |
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383 | } |
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384 | |
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385 | uint32_t _CPU_ISR_Get_level( void ); |
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386 | |
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387 | /* Make sure interrupt stack has space for ISR |
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388 | * 'vector' arg at the top and that it is aligned |
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389 | * properly. |
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390 | */ |
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391 | |
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392 | #define _CPU_Interrupt_stack_setup( _lo, _hi ) \ |
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393 | do { \ |
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394 | _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ |
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395 | } while (0) |
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396 | |
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397 | #endif /* ASM */ |
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398 | |
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399 | /* end of ISR handler macros */ |
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400 | |
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401 | /* |
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402 | * Context handler macros |
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403 | * |
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404 | * These macros perform the following functions: |
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405 | * + initialize a context area |
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406 | * + restart the current thread |
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407 | * + calculate the initial pointer into a FP context area |
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408 | * + initialize an FP context area |
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409 | */ |
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410 | |
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411 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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412 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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413 | |
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414 | #ifndef ASM |
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415 | |
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416 | /* |
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417 | * Stack alignment note: |
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418 | * |
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419 | * We want the stack to look to the '_entry_point' routine |
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420 | * like an ordinary stack frame as if '_entry_point' was |
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421 | * called from C-code. |
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422 | * Note that '_entry_point' is jumped-to by the 'ret' |
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423 | * instruction returning from _CPU_Context_switch() or |
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424 | * _CPU_Context_restore() thus popping the _entry_point |
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425 | * from the stack. |
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426 | * However, _entry_point expects a frame to look like this: |
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427 | * |
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428 | * args [_Thread_Handler expects no args, however] |
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429 | * ------ (alignment boundary) |
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430 | * SP-> return_addr return here when _entry_point returns which (never happens) |
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431 | * |
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432 | * |
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433 | * Hence we must initialize the stack as follows |
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434 | * |
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435 | * [arg1 ]: n/a |
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436 | * [arg0 (aligned)]: n/a |
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437 | * [ret. addr ]: NULL |
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438 | * SP-> [jump-target ]: _entry_point |
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439 | * |
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440 | * When Context_switch returns it pops the _entry_point from |
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441 | * the stack which then finds a standard layout. |
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442 | */ |
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443 | |
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444 | |
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445 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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446 | _isr, _entry_point, _is_fp, _tls_area ) \ |
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447 | do { \ |
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448 | uint32_t _stack; \ |
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449 | \ |
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450 | if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ |
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451 | else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ |
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452 | \ |
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453 | _stack = ((uint32_t)(_stack_base)) + (_size); \ |
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454 | _stack &= ~ (CPU_STACK_ALIGNMENT - 1); \ |
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455 | _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ \ |
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456 | *((proc_ptr *)(_stack)) = (_entry_point); \ |
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457 | (_the_context)->ebp = (void *) 0; \ |
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458 | (_the_context)->esp = (void *) _stack; \ |
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459 | } while (0) |
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460 | |
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461 | #define _CPU_Context_Restart_self( _the_context ) \ |
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462 | _CPU_Context_restore( (_the_context) ); |
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463 | |
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464 | #if defined(RTEMS_SMP) |
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465 | uint32_t _CPU_SMP_Initialize( void ); |
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466 | |
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467 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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468 | |
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469 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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470 | |
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471 | uint32_t _CPU_SMP_Get_current_processor( void ); |
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472 | |
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473 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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474 | |
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475 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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476 | { |
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477 | __asm__ volatile ( "" : : : "memory" ); |
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478 | } |
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479 | |
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480 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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481 | { |
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482 | __asm__ volatile ( "" : : : "memory" ); |
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483 | } |
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484 | #endif |
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485 | |
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486 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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487 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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488 | |
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489 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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490 | { \ |
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491 | memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ |
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492 | } |
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493 | |
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494 | /* end of Context handler macros */ |
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495 | |
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496 | /* |
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497 | * Fatal Error manager macros |
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498 | * |
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499 | * These macros perform the following functions: |
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500 | * + disable interrupts and halt the CPU |
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501 | */ |
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502 | |
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503 | #define _CPU_Fatal_halt( _error ) \ |
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504 | { \ |
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505 | uint32_t _error_lvalue = ( _error ); \ |
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506 | __asm__ volatile ( "cli ; \ |
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507 | movl %0,%%eax ; \ |
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508 | hlt" \ |
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509 | : "=r" ((_error_lvalue)) : "0" ((_error_lvalue)) \ |
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510 | ); \ |
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511 | } |
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512 | |
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513 | #endif /* ASM */ |
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514 | |
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515 | /* end of Fatal Error manager macros */ |
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516 | |
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517 | /* |
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518 | * Bitfield handler macros |
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519 | * |
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520 | * These macros perform the following functions: |
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521 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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522 | */ |
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523 | |
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524 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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525 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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526 | |
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527 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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528 | { \ |
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529 | register uint16_t __value_in_register = (_value); \ |
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530 | \ |
---|
531 | _output = 0; \ |
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532 | \ |
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533 | __asm__ volatile ( "bsfw %0,%1 " \ |
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534 | : "=r" (__value_in_register), "=r" (_output) \ |
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535 | : "0" (__value_in_register), "1" (_output) \ |
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536 | ); \ |
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537 | } |
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538 | |
---|
539 | /* end of Bitfield handler macros */ |
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540 | |
---|
541 | /* |
---|
542 | * Priority handler macros |
---|
543 | * |
---|
544 | * These macros perform the following functions: |
---|
545 | * + return a mask with the bit for this major/minor portion of |
---|
546 | * of thread priority set. |
---|
547 | * + translate the bit number returned by "Bitfield_find_first_bit" |
---|
548 | * into an index into the thread ready chain bit maps |
---|
549 | */ |
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550 | |
---|
551 | #define _CPU_Priority_Mask( _bit_number ) \ |
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552 | ( 1 << (_bit_number) ) |
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553 | |
---|
554 | #define _CPU_Priority_bits_index( _priority ) \ |
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555 | (_priority) |
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556 | |
---|
557 | /* functions */ |
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558 | |
---|
559 | #ifndef ASM |
---|
560 | /* |
---|
561 | * _CPU_Initialize |
---|
562 | * |
---|
563 | * This routine performs CPU dependent initialization. |
---|
564 | */ |
---|
565 | |
---|
566 | void _CPU_Initialize(void); |
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567 | |
---|
568 | /* |
---|
569 | * _CPU_ISR_install_raw_handler |
---|
570 | * |
---|
571 | * This routine installs a "raw" interrupt handler directly into the |
---|
572 | * processor's vector table. |
---|
573 | */ |
---|
574 | |
---|
575 | void _CPU_ISR_install_raw_handler( |
---|
576 | uint32_t vector, |
---|
577 | proc_ptr new_handler, |
---|
578 | proc_ptr *old_handler |
---|
579 | ); |
---|
580 | |
---|
581 | /* |
---|
582 | * _CPU_ISR_install_vector |
---|
583 | * |
---|
584 | * This routine installs an interrupt vector. |
---|
585 | */ |
---|
586 | |
---|
587 | void _CPU_ISR_install_vector( |
---|
588 | uint32_t vector, |
---|
589 | proc_ptr new_handler, |
---|
590 | proc_ptr *old_handler |
---|
591 | ); |
---|
592 | |
---|
593 | /* |
---|
594 | * _CPU_Thread_Idle_body |
---|
595 | * |
---|
596 | * Use the halt instruction of low power mode of a particular i386 model. |
---|
597 | */ |
---|
598 | |
---|
599 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
---|
600 | |
---|
601 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
602 | |
---|
603 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
---|
604 | |
---|
605 | /* |
---|
606 | * _CPU_Context_switch |
---|
607 | * |
---|
608 | * This routine switches from the run context to the heir context. |
---|
609 | */ |
---|
610 | |
---|
611 | void _CPU_Context_switch( |
---|
612 | Context_Control *run, |
---|
613 | Context_Control *heir |
---|
614 | ); |
---|
615 | |
---|
616 | /* |
---|
617 | * _CPU_Context_restore |
---|
618 | * |
---|
619 | * This routine is generally used only to restart self in an |
---|
620 | * efficient manner and avoid stack conflicts. |
---|
621 | */ |
---|
622 | |
---|
623 | void _CPU_Context_restore( |
---|
624 | Context_Control *new_context |
---|
625 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
626 | |
---|
627 | /* |
---|
628 | * _CPU_Context_save_fp |
---|
629 | * |
---|
630 | * This routine saves the floating point context passed to it. |
---|
631 | */ |
---|
632 | |
---|
633 | #ifdef __SSE__ |
---|
634 | #define _CPU_Context_save_fp(fp_context_pp) \ |
---|
635 | do { \ |
---|
636 | __asm__ __volatile__( \ |
---|
637 | "fstcw %0" \ |
---|
638 | :"=m"((*(fp_context_pp))->fpucw) \ |
---|
639 | ); \ |
---|
640 | __asm__ __volatile__( \ |
---|
641 | "stmxcsr %0" \ |
---|
642 | :"=m"((*(fp_context_pp))->mxcsr) \ |
---|
643 | ); \ |
---|
644 | } while (0) |
---|
645 | #else |
---|
646 | void _CPU_Context_save_fp( |
---|
647 | Context_Control_fp **fp_context_ptr |
---|
648 | ); |
---|
649 | #endif |
---|
650 | |
---|
651 | /* |
---|
652 | * _CPU_Context_restore_fp |
---|
653 | * |
---|
654 | * This routine restores the floating point context passed to it. |
---|
655 | */ |
---|
656 | #ifdef __SSE__ |
---|
657 | #define _CPU_Context_restore_fp(fp_context_pp) \ |
---|
658 | do { \ |
---|
659 | __asm__ __volatile__( \ |
---|
660 | "fldcw %0" \ |
---|
661 | ::"m"((*(fp_context_pp))->fpucw) \ |
---|
662 | :"fpcr" \ |
---|
663 | ); \ |
---|
664 | __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ |
---|
665 | } while (0) |
---|
666 | #else |
---|
667 | void _CPU_Context_restore_fp( |
---|
668 | Context_Control_fp **fp_context_ptr |
---|
669 | ); |
---|
670 | #endif |
---|
671 | |
---|
672 | #ifdef __SSE__ |
---|
673 | #define _CPU_Context_Initialization_at_thread_begin() \ |
---|
674 | do { \ |
---|
675 | __asm__ __volatile__( \ |
---|
676 | "finit" \ |
---|
677 | : \ |
---|
678 | : \ |
---|
679 | :"st","st(1)","st(2)","st(3)", \ |
---|
680 | "st(4)","st(5)","st(6)","st(7)", \ |
---|
681 | "fpsr","fpcr" \ |
---|
682 | ); \ |
---|
683 | if ( _Thread_Executing->fp_context ) { \ |
---|
684 | _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ |
---|
685 | } \ |
---|
686 | } while (0) |
---|
687 | #endif |
---|
688 | |
---|
689 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
690 | { |
---|
691 | /* TODO */ |
---|
692 | } |
---|
693 | |
---|
694 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
695 | { |
---|
696 | while (1) { |
---|
697 | /* TODO */ |
---|
698 | } |
---|
699 | } |
---|
700 | |
---|
701 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
702 | |
---|
703 | typedef uint32_t CPU_Counter_ticks; |
---|
704 | |
---|
705 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
706 | |
---|
707 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
708 | CPU_Counter_ticks second, |
---|
709 | CPU_Counter_ticks first |
---|
710 | ) |
---|
711 | { |
---|
712 | return second - first; |
---|
713 | } |
---|
714 | |
---|
715 | #endif /* ASM */ |
---|
716 | |
---|
717 | #ifdef __cplusplus |
---|
718 | } |
---|
719 | #endif |
---|
720 | |
---|
721 | #endif |
---|