source: rtems/cpukit/score/cpu/i386/rtems/score/cpu.h @ 03b7789

4.11
Last change on this file since 03b7789 was 03b7789, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 26, 2014 at 1:09:10 PM

score: Statically initialize _ISR_Vector_table

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1/**
2 * @file
3 *
4 * @brief Intel I386 CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Intel
7 * i386 processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifndef ASM
23#include <string.h> /* for memcpy */
24#endif
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <rtems/score/types.h>
31#include <rtems/score/i386.h>
32
33#ifndef ASM
34#include <rtems/score/interrupts.h>     /* formerly in libcpu/cpu.h> */
35#include <rtems/score/registers.h>      /* formerly part of libcpu */
36#endif
37
38/* conditional compilation parameters */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
42
43/*
44 *  Does the CPU follow the simple vectored interrupt model?
45 *
46 *  If TRUE, then RTEMS allocates the vector table it internally manages.
47 *  If FALSE, then the BSP is assumed to allocate and manage the vector
48 *  table
49 *
50 *  PowerPC Specific Information:
51 *
52 *  The PowerPC and x86 were the first to use the PIC interrupt model.
53 *  They do not use the simple vectored interrupt model.
54 */
55#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
56
57/*
58 *  i386 has an RTEMS allocated and managed interrupt stack.
59 */
60
61#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
62#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
63#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
64
65/*
66 *  Does the RTEMS invoke the user's ISR with the vector number and
67 *  a pointer to the saved interrupt frame (1) or just the vector
68 *  number (0)?
69 */
70
71#define CPU_ISR_PASSES_FRAME_POINTER 0
72
73/*
74 *  Some family members have no FP, some have an FPU such as the i387
75 *  for the i386, others have it built in (i486DX, Pentium).
76 */
77
78#ifdef __SSE__
79#define CPU_HARDWARE_FP                  TRUE
80#define CPU_SOFTWARE_FP                  FALSE
81
82#define CPU_ALL_TASKS_ARE_FP             TRUE
83#define CPU_IDLE_TASK_IS_FP              TRUE
84#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
85#else /* __SSE__ */
86
87#if ( I386_HAS_FPU == 1 )
88#define CPU_HARDWARE_FP     TRUE    /* i387 for i386 */
89#else
90#define CPU_HARDWARE_FP     FALSE
91#endif
92#define CPU_SOFTWARE_FP     FALSE
93
94#define CPU_ALL_TASKS_ARE_FP             FALSE
95#define CPU_IDLE_TASK_IS_FP              FALSE
96#if defined(RTEMS_SMP)
97  #define CPU_USE_DEFERRED_FP_SWITCH     FALSE
98#else
99  #define CPU_USE_DEFERRED_FP_SWITCH     TRUE
100#endif
101#endif /* __SSE__ */
102
103#define CPU_STACK_GROWS_UP               FALSE
104#define CPU_STRUCTURE_ALIGNMENT
105
106#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
107
108/*
109 *  Does this port provide a CPU dependent IDLE task implementation?
110 *
111 *  If TRUE, then the routine _CPU_Thread_Idle_body
112 *  must be provided and is the default IDLE thread body instead of
113 *  _CPU_Thread_Idle_body.
114 *
115 *  If FALSE, then use the generic IDLE thread body if the BSP does
116 *  not provide one.
117 */
118
119#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
120
121/*
122 *  Define what is required to specify how the network to host conversion
123 *  routines are handled.
124 */
125
126#define CPU_BIG_ENDIAN                           FALSE
127#define CPU_LITTLE_ENDIAN                        TRUE
128
129#define CPU_PER_CPU_CONTROL_SIZE 0
130
131/* structures */
132
133#ifndef ASM
134
135typedef struct {
136  /* There is no CPU specific per-CPU state */
137} CPU_Per_CPU_control;
138
139/*
140 *  Basic integer context for the i386 family.
141 */
142
143typedef struct {
144  uint32_t    eflags;   /* extended flags register                   */
145  void       *esp;      /* extended stack pointer register           */
146  void       *ebp;      /* extended base pointer register            */
147  uint32_t    ebx;      /* extended bx register                      */
148  uint32_t    esi;      /* extended source index register            */
149  uint32_t    edi;      /* extended destination index flags register */
150}   Context_Control;
151
152#define _CPU_Context_Get_SP( _context ) \
153  (_context)->esp
154
155/*
156 *  FP context save area for the i387 numeric coprocessors.
157 */
158#ifdef __SSE__
159/* All FPU and SSE registers are volatile; hence, as long
160 * as we are within normally executing C code (including
161 * a task switch) there is no need for saving/restoring
162 * any of those registers.
163 * We must save/restore the full FPU/SSE context across
164 * interrupts and exceptions, however:
165 *   -  after ISR execution a _Thread_Dispatch() may happen
166 *      and it is therefore necessary to save the FPU/SSE
167 *      registers to be restored when control is returned
168 *      to the interrupted task.
169 *   -  gcc may implicitly use FPU/SSE instructions in
170 *      an ISR.
171 *
172 * Even though there is no explicit mentioning of the FPU
173 * control word in the SYSV ABI (i386) being non-volatile
174 * we maintain MXCSR and the FPU control-word for each task.
175 */
176typedef struct {
177        uint32_t  mxcsr;
178        uint16_t  fpucw;
179} Context_Control_fp;
180
181#else
182
183typedef struct {
184  uint8_t     fp_save_area[108];    /* context size area for I80387 */
185                                    /*  28 bytes for environment    */
186} Context_Control_fp;
187
188#endif
189
190
191/*
192 *  The following structure defines the set of information saved
193 *  on the current stack by RTEMS upon receipt of execptions.
194 *
195 * idtIndex is either the interrupt number or the trap/exception number.
196 * faultCode is the code pushed by the processor on some exceptions.
197 *
198 * Since the first registers are directly pushed by the CPU they
199 * may not respect 16-byte stack alignment, which is, however,
200 * mandatory for the SSE register area.
201 * Therefore, these registers are stored at an aligned address
202 * and a pointer is stored in the CPU_Exception_frame.
203 * If the executive was compiled without SSE support then
204 * this pointer is NULL.
205 */
206
207struct Context_Control_sse;
208
209typedef struct {
210  struct Context_Control_sse *fp_ctxt;
211  uint32_t    edi;
212  uint32_t    esi;
213  uint32_t    ebp;
214  uint32_t    esp0;
215  uint32_t    ebx;
216  uint32_t    edx;
217  uint32_t    ecx;
218  uint32_t    eax;
219  uint32_t    idtIndex;
220  uint32_t    faultCode;
221  uint32_t    eip;
222  uint32_t    cs;
223  uint32_t    eflags;
224} CPU_Exception_frame;
225
226#ifdef __SSE__
227typedef struct Context_Control_sse {
228  uint16_t  fcw;
229  uint16_t  fsw;
230  uint8_t   ftw;
231  uint8_t   res_1;
232  uint16_t  fop;
233  uint32_t  fpu_ip;
234  uint16_t  cs;
235  uint16_t  res_2;
236  uint32_t  fpu_dp;
237  uint16_t  ds;
238  uint16_t  res_3;
239  uint32_t  mxcsr;
240  uint32_t  mxcsr_mask;
241  struct {
242        uint8_t fpreg[10];
243        uint8_t res_4[ 6];
244  } fp_mmregs[8];
245  uint8_t   xmmregs[8][16];
246  uint8_t   res_5[224];
247} Context_Control_sse
248__attribute__((aligned(16)))
249;
250#endif
251
252typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
253extern cpuExcHandlerType _currentExcHandler;
254extern void rtems_exception_init_mngt(void);
255
256/*
257 * This port does not pass any frame info to the
258 * interrupt handler.
259 */
260
261typedef void CPU_Interrupt_frame;
262
263typedef enum {
264  I386_EXCEPTION_DIVIDE_BY_ZERO      = 0,
265  I386_EXCEPTION_DEBUG               = 1,
266  I386_EXCEPTION_NMI                 = 2,
267  I386_EXCEPTION_BREAKPOINT          = 3,
268  I386_EXCEPTION_OVERFLOW            = 4,
269  I386_EXCEPTION_BOUND               = 5,
270  I386_EXCEPTION_ILLEGAL_INSTR       = 6,
271  I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
272  I386_EXCEPTION_DOUBLE_FAULT        = 8,
273  I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
274  I386_EXCEPTION_INVALID_TSS         = 10,
275  I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
276  I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
277  I386_EXCEPTION_GENERAL_PROT_ERR    = 13,
278  I386_EXCEPTION_PAGE_FAULT          = 14,
279  I386_EXCEPTION_INTEL_RES15         = 15,
280  I386_EXCEPTION_FLOAT_ERROR         = 16,
281  I386_EXCEPTION_ALIGN_CHECK         = 17,
282  I386_EXCEPTION_MACHINE_CHECK       = 18,
283  I386_EXCEPTION_ENTER_RDBG          = 50     /* to enter manually RDBG */
284
285} Intel_symbolic_exception_name;
286
287
288/*
289 *  context size area for floating point
290 *
291 *  NOTE:  This is out of place on the i386 to avoid a forward reference.
292 */
293
294#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
295
296/* variables */
297
298SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
299
300#endif /* ASM */
301
302/* constants */
303
304/*
305 *  This defines the number of levels and the mask used to pick those
306 *  bits out of a thread mode.
307 */
308
309#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
310#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
311
312/*
313 *  extra stack required by the MPCI receive server thread
314 */
315
316#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
317
318/*
319 *  This is defined if the port has a special way to report the ISR nesting
320 *  level.  Most ports maintain the variable _ISR_Nest_level.
321 */
322
323#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
324
325/*
326 *  Minimum size of a thread's stack.
327 */
328
329#define CPU_STACK_MINIMUM_SIZE          4096
330
331#define CPU_SIZEOF_POINTER 4
332
333/*
334 *  i386 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
335 */
336
337#define CPU_ALIGNMENT                    4
338#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
339#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
340
341/*
342 *  On i386 thread stacks require no further alignment after allocation
343 *  from the Workspace. However, since gcc maintains 16-byte alignment
344 *  we try to respect that. If you find an option to let gcc squeeze
345 *  the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still
346 *  doesn't waste much space since this only determines the *initial*
347 *  alignment.
348 */
349
350#define CPU_STACK_ALIGNMENT             16
351
352/* macros */
353
354#ifndef ASM
355/*
356 *  ISR handler macros
357 *
358 *  These macros perform the following functions:
359 *     + initialize the RTEMS vector table
360 *     + disable all maskable CPU interrupts
361 *     + restore previous interrupt level (enable)
362 *     + temporarily restore interrupts (flash)
363 *     + set a particular level
364 */
365
366#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
367
368#define _CPU_ISR_Enable( _level )  i386_enable_interrupts( _level )
369
370#define _CPU_ISR_Flash( _level )   i386_flash_interrupts( _level )
371
372#define _CPU_ISR_Set_level( _new_level ) \
373  { \
374    if ( _new_level ) __asm__ volatile ( "cli" ); \
375    else              __asm__ volatile ( "sti" ); \
376  }
377
378uint32_t   _CPU_ISR_Get_level( void );
379
380/*  Make sure interrupt stack has space for ISR
381 *  'vector' arg at the top and that it is aligned
382 *  properly.
383 */
384
385#define _CPU_Interrupt_stack_setup( _lo, _hi )  \
386        do {                                        \
387                _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \
388        } while (0)
389
390#endif /* ASM */
391
392/* end of ISR handler macros */
393
394/*
395 *  Context handler macros
396 *
397 *  These macros perform the following functions:
398 *     + initialize a context area
399 *     + restart the current thread
400 *     + calculate the initial pointer into a FP context area
401 *     + initialize an FP context area
402 */
403
404#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
405#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
406
407#ifndef ASM
408
409/*
410 * Stack alignment note:
411 *
412 * We want the stack to look to the '_entry_point' routine
413 * like an ordinary stack frame as if '_entry_point' was
414 * called from C-code.
415 * Note that '_entry_point' is jumped-to by the 'ret'
416 * instruction returning from _CPU_Context_switch() or
417 * _CPU_Context_restore() thus popping the _entry_point
418 * from the stack.
419 * However, _entry_point expects a frame to look like this:
420 *
421 *      args        [_Thread_Handler expects no args, however]
422 *      ------      (alignment boundary)
423 * SP-> return_addr return here when _entry_point returns which (never happens)
424 *
425 *
426 * Hence we must initialize the stack as follows
427 *
428 *         [arg1          ]:  n/a
429 *         [arg0 (aligned)]:  n/a
430 *         [ret. addr     ]:  NULL
431 * SP->    [jump-target   ]:  _entry_point
432 *
433 * When Context_switch returns it pops the _entry_point from
434 * the stack which then finds a standard layout.
435 */
436
437
438#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
439                                   _isr, _entry_point, _is_fp, _tls_area ) \
440  do { \
441    uint32_t   _stack; \
442    \
443    if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \
444    else          (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \
445    \
446    _stack  = ((uint32_t)(_stack_base)) + (_size); \
447        _stack &= ~ (CPU_STACK_ALIGNMENT - 1); \
448    _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ \
449    *((proc_ptr *)(_stack)) = (_entry_point); \
450    (_the_context)->ebp     = (void *) 0; \
451    (_the_context)->esp     = (void *) _stack; \
452  } while (0)
453
454#define _CPU_Context_Restart_self( _the_context ) \
455   _CPU_Context_restore( (_the_context) );
456
457#if defined(RTEMS_SMP)
458  uint32_t _CPU_SMP_Initialize( void );
459
460  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
461
462  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
463
464  uint32_t _CPU_SMP_Get_current_processor( void );
465
466  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
467
468  static inline void _CPU_SMP_Processor_event_broadcast( void )
469  {
470    __asm__ volatile ( "" : : : "memory" );
471  }
472
473  static inline void _CPU_SMP_Processor_event_receive( void )
474  {
475    __asm__ volatile ( "" : : : "memory" );
476  }
477#endif
478
479#define _CPU_Context_Fp_start( _base, _offset ) \
480   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
481
482#define _CPU_Context_Initialize_fp( _fp_area ) \
483  { \
484    memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \
485  }
486
487/* end of Context handler macros */
488
489/*
490 *  Fatal Error manager macros
491 *
492 *  These macros perform the following functions:
493 *    + disable interrupts and halt the CPU
494 */
495
496#define _CPU_Fatal_halt( _error ) \
497  { \
498    uint32_t _error_lvalue = ( _error ); \
499    __asm__ volatile ( "cli ; \
500                    movl %0,%%eax ; \
501                    hlt" \
502                    : "=r" ((_error_lvalue)) : "0" ((_error_lvalue)) \
503    ); \
504  }
505
506#endif /* ASM */
507
508/* end of Fatal Error manager macros */
509
510/*
511 *  Bitfield handler macros
512 *
513 *  These macros perform the following functions:
514 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
515 */
516
517#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
518#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
519
520#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
521  { \
522    register uint16_t   __value_in_register = (_value); \
523    \
524    _output = 0; \
525    \
526    __asm__ volatile ( "bsfw    %0,%1 " \
527                    : "=r" (__value_in_register), "=r" (_output) \
528                    : "0"  (__value_in_register), "1"  (_output) \
529    ); \
530  }
531
532/* end of Bitfield handler macros */
533
534/*
535 *  Priority handler macros
536 *
537 *  These macros perform the following functions:
538 *    + return a mask with the bit for this major/minor portion of
539 *      of thread priority set.
540 *    + translate the bit number returned by "Bitfield_find_first_bit"
541 *      into an index into the thread ready chain bit maps
542 */
543
544#define _CPU_Priority_Mask( _bit_number ) \
545  ( 1 << (_bit_number) )
546
547#define _CPU_Priority_bits_index( _priority ) \
548  (_priority)
549
550/* functions */
551
552#ifndef ASM
553/*
554 *  _CPU_Initialize
555 *
556 *  This routine performs CPU dependent initialization.
557 */
558
559void _CPU_Initialize(void);
560
561/*
562 *  _CPU_ISR_install_raw_handler
563 *
564 *  This routine installs a "raw" interrupt handler directly into the
565 *  processor's vector table.
566 */
567
568void _CPU_ISR_install_raw_handler(
569  uint32_t    vector,
570  proc_ptr    new_handler,
571  proc_ptr   *old_handler
572);
573
574/*
575 *  _CPU_ISR_install_vector
576 *
577 *  This routine installs an interrupt vector.
578 */
579
580void _CPU_ISR_install_vector(
581  uint32_t    vector,
582  proc_ptr    new_handler,
583  proc_ptr   *old_handler
584);
585
586/*
587 *  _CPU_Thread_Idle_body
588 *
589 *  Use the halt instruction of low power mode of a particular i386 model.
590 */
591
592#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
593
594void *_CPU_Thread_Idle_body( uintptr_t ignored );
595
596#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
597
598/*
599 *  _CPU_Context_switch
600 *
601 *  This routine switches from the run context to the heir context.
602 */
603
604void _CPU_Context_switch(
605  Context_Control  *run,
606  Context_Control  *heir
607);
608
609/*
610 *  _CPU_Context_restore
611 *
612 *  This routine is generally used only to restart self in an
613 *  efficient manner and avoid stack conflicts.
614 */
615
616void _CPU_Context_restore(
617  Context_Control *new_context
618) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
619
620/*
621 *  _CPU_Context_save_fp
622 *
623 *  This routine saves the floating point context passed to it.
624 */
625
626#ifdef __SSE__
627#define _CPU_Context_save_fp(fp_context_pp) \
628  do {                                      \
629    __asm__ __volatile__(                   \
630      "fstcw %0"                            \
631      :"=m"((*(fp_context_pp))->fpucw)      \
632    );                                      \
633        __asm__ __volatile__(                   \
634      "stmxcsr %0"                          \
635      :"=m"((*(fp_context_pp))->mxcsr)      \
636    );                                      \
637  } while (0)
638#else
639void _CPU_Context_save_fp(
640  Context_Control_fp **fp_context_ptr
641);
642#endif
643
644/*
645 *  _CPU_Context_restore_fp
646 *
647 *  This routine restores the floating point context passed to it.
648 */
649#ifdef __SSE__
650#define _CPU_Context_restore_fp(fp_context_pp) \
651  do {                                         \
652    __asm__ __volatile__(                      \
653      "fldcw %0"                               \
654      ::"m"((*(fp_context_pp))->fpucw)         \
655      :"fpcr"                                  \
656    );                                         \
657    __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr);  \
658  } while (0)
659#else
660void _CPU_Context_restore_fp(
661  Context_Control_fp **fp_context_ptr
662);
663#endif
664
665#ifdef __SSE__
666#define _CPU_Context_Initialization_at_thread_begin() \
667  do {                                                \
668    __asm__ __volatile__(                             \
669      "finit"                                         \
670      :                                               \
671      :                                               \
672      :"st","st(1)","st(2)","st(3)",                  \
673       "st(4)","st(5)","st(6)","st(7)",               \
674       "fpsr","fpcr"                                  \
675    );                                                \
676        if ( _Thread_Executing->fp_context ) {            \
677          _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \
678   }                                                  \
679  } while (0)
680#endif
681
682static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
683{
684  /* TODO */
685}
686
687static inline void _CPU_Context_validate( uintptr_t pattern )
688{
689  while (1) {
690    /* TODO */
691  }
692}
693
694void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
695
696typedef uint32_t CPU_Counter_ticks;
697
698CPU_Counter_ticks _CPU_Counter_read( void );
699
700static inline CPU_Counter_ticks _CPU_Counter_difference(
701  CPU_Counter_ticks second,
702  CPU_Counter_ticks first
703)
704{
705  return second - first;
706}
707
708#endif /* ASM */
709
710#ifdef __cplusplus
711}
712#endif
713
714#endif
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