[6d6891e] | 1 | /** |
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[d9e0006] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief Intel I386 CPU Dependent Source |
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| 5 | * |
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| 6 | * This include file contains information pertaining to the Intel |
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| 7 | * i386 processor. |
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[6d6891e] | 8 | */ |
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| 9 | |
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| 10 | /* |
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[06dcaf0] | 11 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_CPU_H |
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| 20 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 21 | |
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[a6d48e3] | 22 | #ifndef ASM |
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[af063f6] | 23 | #include <string.h> /* for memcpy */ |
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[a6d48e3] | 24 | #endif |
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[af063f6] | 25 | |
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[7908ba5b] | 26 | #ifdef __cplusplus |
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| 27 | extern "C" { |
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| 28 | #endif |
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| 29 | |
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[89b85e51] | 30 | #include <rtems/score/types.h> |
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| 31 | #include <rtems/score/i386.h> |
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[7908ba5b] | 32 | |
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| 33 | #ifndef ASM |
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[a324355] | 34 | #include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ |
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| 35 | #include <rtems/score/registers.h> /* formerly part of libcpu */ |
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[7908ba5b] | 36 | #endif |
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| 37 | |
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| 38 | /* conditional compilation parameters */ |
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| 39 | |
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| 40 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 41 | |
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[562cadfa] | 42 | /* |
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| 43 | * Does the CPU follow the simple vectored interrupt model? |
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| 44 | * |
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| 45 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 46 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 47 | * table |
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| 48 | * |
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| 49 | * PowerPC Specific Information: |
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| 50 | * |
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| 51 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
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| 52 | * They do not use the simple vectored interrupt model. |
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| 53 | */ |
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| 54 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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| 55 | |
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[7908ba5b] | 56 | /* |
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| 57 | * i386 has an RTEMS allocated and managed interrupt stack. |
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| 58 | */ |
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| 59 | |
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| 60 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 61 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 62 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 63 | |
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| 64 | /* |
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| 65 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[84c53452] | 66 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 67 | * number (0)? |
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| 68 | */ |
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| 69 | |
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| 70 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 71 | |
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| 72 | /* |
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| 73 | * Some family members have no FP, some have an FPU such as the i387 |
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| 74 | * for the i386, others have it built in (i486DX, Pentium). |
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| 75 | */ |
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| 76 | |
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[b02f4cc1] | 77 | #ifdef __SSE__ |
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| 78 | #define CPU_HARDWARE_FP TRUE |
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| 79 | #define CPU_SOFTWARE_FP FALSE |
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| 80 | |
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| 81 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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| 82 | #define CPU_IDLE_TASK_IS_FP TRUE |
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| 83 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 84 | #else /* __SSE__ */ |
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| 85 | |
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[7908ba5b] | 86 | #if ( I386_HAS_FPU == 1 ) |
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| 87 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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| 88 | #else |
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| 89 | #define CPU_HARDWARE_FP FALSE |
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| 90 | #endif |
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[17508d02] | 91 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 92 | |
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| 93 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 94 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[965ef82] | 95 | #if defined(RTEMS_SMP) |
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| 96 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 97 | #else |
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| 98 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 99 | #endif |
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[b02f4cc1] | 100 | #endif /* __SSE__ */ |
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[7908ba5b] | 101 | |
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| 102 | #define CPU_STACK_GROWS_UP FALSE |
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[a8865f8] | 103 | |
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| 104 | /* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */ |
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| 105 | #define CPU_CACHE_LINE_BYTES 64 |
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| 106 | |
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[7908ba5b] | 107 | #define CPU_STRUCTURE_ALIGNMENT |
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| 108 | |
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| 109 | /* |
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| 110 | * Does this port provide a CPU dependent IDLE task implementation? |
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[84c53452] | 111 | * |
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[7908ba5b] | 112 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 113 | * must be provided and is the default IDLE thread body instead of |
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| 114 | * _CPU_Thread_Idle_body. |
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| 115 | * |
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| 116 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 117 | * not provide one. |
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| 118 | */ |
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[84c53452] | 119 | |
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[fd05a05] | 120 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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[7908ba5b] | 121 | |
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| 122 | /* |
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| 123 | * Define what is required to specify how the network to host conversion |
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| 124 | * routines are handled. |
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| 125 | */ |
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| 126 | |
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| 127 | #define CPU_BIG_ENDIAN FALSE |
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| 128 | #define CPU_LITTLE_ENDIAN TRUE |
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| 129 | |
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[10fd4aac] | 130 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 131 | |
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[38b59a6] | 132 | #define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 |
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| 133 | #define I386_CONTEXT_CONTROL_ESP_OFFSET 4 |
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| 134 | #define I386_CONTEXT_CONTROL_EBP_OFFSET 8 |
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| 135 | #define I386_CONTEXT_CONTROL_EBX_OFFSET 12 |
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| 136 | #define I386_CONTEXT_CONTROL_ESI_OFFSET 16 |
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| 137 | #define I386_CONTEXT_CONTROL_EDI_OFFSET 20 |
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| 138 | |
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| 139 | #ifdef RTEMS_SMP |
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| 140 | #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 24 |
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| 141 | #endif |
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| 142 | |
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[7908ba5b] | 143 | /* structures */ |
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| 144 | |
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[a6d48e3] | 145 | #ifndef ASM |
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| 146 | |
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[10fd4aac] | 147 | typedef struct { |
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| 148 | /* There is no CPU specific per-CPU state */ |
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| 149 | } CPU_Per_CPU_control; |
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| 150 | |
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[7908ba5b] | 151 | /* |
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| 152 | * Basic integer context for the i386 family. |
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| 153 | */ |
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| 154 | |
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| 155 | typedef struct { |
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[e6aeabd] | 156 | uint32_t eflags; /* extended flags register */ |
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[7908ba5b] | 157 | void *esp; /* extended stack pointer register */ |
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| 158 | void *ebp; /* extended base pointer register */ |
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[e6aeabd] | 159 | uint32_t ebx; /* extended bx register */ |
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| 160 | uint32_t esi; /* extended source index register */ |
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| 161 | uint32_t edi; /* extended destination index flags register */ |
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[38b59a6] | 162 | #ifdef RTEMS_SMP |
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| 163 | volatile bool is_executing; |
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| 164 | #endif |
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[7908ba5b] | 165 | } Context_Control; |
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| 166 | |
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[0ca6d0d9] | 167 | #define _CPU_Context_Get_SP( _context ) \ |
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| 168 | (_context)->esp |
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| 169 | |
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[38b59a6] | 170 | #ifdef RTEMS_SMP |
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[11b05f1] | 171 | static inline bool _CPU_Context_Get_is_executing( |
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| 172 | const Context_Control *context |
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| 173 | ) |
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| 174 | { |
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| 175 | return context->is_executing; |
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| 176 | } |
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| 177 | |
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| 178 | static inline void _CPU_Context_Set_is_executing( |
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| 179 | Context_Control *context, |
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| 180 | bool is_executing |
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| 181 | ) |
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| 182 | { |
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| 183 | context->is_executing = is_executing; |
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| 184 | } |
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[38b59a6] | 185 | #endif |
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| 186 | |
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[7908ba5b] | 187 | /* |
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| 188 | * FP context save area for the i387 numeric coprocessors. |
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| 189 | */ |
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[b02f4cc1] | 190 | #ifdef __SSE__ |
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| 191 | /* All FPU and SSE registers are volatile; hence, as long |
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| 192 | * as we are within normally executing C code (including |
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| 193 | * a task switch) there is no need for saving/restoring |
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| 194 | * any of those registers. |
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| 195 | * We must save/restore the full FPU/SSE context across |
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| 196 | * interrupts and exceptions, however: |
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| 197 | * - after ISR execution a _Thread_Dispatch() may happen |
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| 198 | * and it is therefore necessary to save the FPU/SSE |
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| 199 | * registers to be restored when control is returned |
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| 200 | * to the interrupted task. |
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| 201 | * - gcc may implicitly use FPU/SSE instructions in |
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| 202 | * an ISR. |
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| 203 | * |
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| 204 | * Even though there is no explicit mentioning of the FPU |
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| 205 | * control word in the SYSV ABI (i386) being non-volatile |
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| 206 | * we maintain MXCSR and the FPU control-word for each task. |
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| 207 | */ |
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| 208 | typedef struct { |
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| 209 | uint32_t mxcsr; |
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| 210 | uint16_t fpucw; |
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| 211 | } Context_Control_fp; |
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| 212 | |
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| 213 | #else |
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[7908ba5b] | 214 | |
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| 215 | typedef struct { |
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[e6aeabd] | 216 | uint8_t fp_save_area[108]; /* context size area for I80387 */ |
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[7908ba5b] | 217 | /* 28 bytes for environment */ |
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| 218 | } Context_Control_fp; |
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| 219 | |
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[b02f4cc1] | 220 | #endif |
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| 221 | |
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[7908ba5b] | 222 | |
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| 223 | /* |
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| 224 | * The following structure defines the set of information saved |
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| 225 | * on the current stack by RTEMS upon receipt of execptions. |
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| 226 | * |
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| 227 | * idtIndex is either the interrupt number or the trap/exception number. |
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| 228 | * faultCode is the code pushed by the processor on some exceptions. |
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[b02f4cc1] | 229 | * |
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| 230 | * Since the first registers are directly pushed by the CPU they |
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| 231 | * may not respect 16-byte stack alignment, which is, however, |
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| 232 | * mandatory for the SSE register area. |
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| 233 | * Therefore, these registers are stored at an aligned address |
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| 234 | * and a pointer is stored in the CPU_Exception_frame. |
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| 235 | * If the executive was compiled without SSE support then |
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| 236 | * this pointer is NULL. |
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[7908ba5b] | 237 | */ |
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| 238 | |
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[b02f4cc1] | 239 | struct Context_Control_sse; |
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| 240 | |
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[7908ba5b] | 241 | typedef struct { |
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[b02f4cc1] | 242 | struct Context_Control_sse *fp_ctxt; |
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[e6aeabd] | 243 | uint32_t edi; |
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| 244 | uint32_t esi; |
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| 245 | uint32_t ebp; |
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| 246 | uint32_t esp0; |
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| 247 | uint32_t ebx; |
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| 248 | uint32_t edx; |
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| 249 | uint32_t ecx; |
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| 250 | uint32_t eax; |
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| 251 | uint32_t idtIndex; |
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| 252 | uint32_t faultCode; |
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| 253 | uint32_t eip; |
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| 254 | uint32_t cs; |
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| 255 | uint32_t eflags; |
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[7908ba5b] | 256 | } CPU_Exception_frame; |
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| 257 | |
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[b02f4cc1] | 258 | #ifdef __SSE__ |
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| 259 | typedef struct Context_Control_sse { |
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| 260 | uint16_t fcw; |
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| 261 | uint16_t fsw; |
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| 262 | uint8_t ftw; |
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| 263 | uint8_t res_1; |
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| 264 | uint16_t fop; |
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| 265 | uint32_t fpu_ip; |
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| 266 | uint16_t cs; |
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| 267 | uint16_t res_2; |
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| 268 | uint32_t fpu_dp; |
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| 269 | uint16_t ds; |
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| 270 | uint16_t res_3; |
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| 271 | uint32_t mxcsr; |
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| 272 | uint32_t mxcsr_mask; |
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| 273 | struct { |
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| 274 | uint8_t fpreg[10]; |
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| 275 | uint8_t res_4[ 6]; |
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| 276 | } fp_mmregs[8]; |
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| 277 | uint8_t xmmregs[8][16]; |
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| 278 | uint8_t res_5[224]; |
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| 279 | } Context_Control_sse |
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| 280 | __attribute__((aligned(16))) |
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| 281 | ; |
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| 282 | #endif |
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| 283 | |
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[7908ba5b] | 284 | typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); |
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| 285 | extern cpuExcHandlerType _currentExcHandler; |
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[1b502424] | 286 | extern void rtems_exception_init_mngt(void); |
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[7908ba5b] | 287 | |
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| 288 | /* |
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[78667e3] | 289 | * This port does not pass any frame info to the |
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| 290 | * interrupt handler. |
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[7908ba5b] | 291 | */ |
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| 292 | |
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[78667e3] | 293 | typedef void CPU_Interrupt_frame; |
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[7908ba5b] | 294 | |
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| 295 | typedef enum { |
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| 296 | I386_EXCEPTION_DIVIDE_BY_ZERO = 0, |
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| 297 | I386_EXCEPTION_DEBUG = 1, |
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| 298 | I386_EXCEPTION_NMI = 2, |
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| 299 | I386_EXCEPTION_BREAKPOINT = 3, |
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| 300 | I386_EXCEPTION_OVERFLOW = 4, |
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| 301 | I386_EXCEPTION_BOUND = 5, |
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| 302 | I386_EXCEPTION_ILLEGAL_INSTR = 6, |
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| 303 | I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, |
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| 304 | I386_EXCEPTION_DOUBLE_FAULT = 8, |
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| 305 | I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, |
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| 306 | I386_EXCEPTION_INVALID_TSS = 10, |
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| 307 | I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, |
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| 308 | I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, |
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| 309 | I386_EXCEPTION_GENERAL_PROT_ERR = 13, |
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| 310 | I386_EXCEPTION_PAGE_FAULT = 14, |
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| 311 | I386_EXCEPTION_INTEL_RES15 = 15, |
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| 312 | I386_EXCEPTION_FLOAT_ERROR = 16, |
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| 313 | I386_EXCEPTION_ALIGN_CHECK = 17, |
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| 314 | I386_EXCEPTION_MACHINE_CHECK = 18, |
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| 315 | I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ |
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| 316 | |
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| 317 | } Intel_symbolic_exception_name; |
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[84c53452] | 318 | |
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[7908ba5b] | 319 | |
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| 320 | /* |
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| 321 | * context size area for floating point |
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| 322 | * |
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| 323 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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| 324 | */ |
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| 325 | |
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| 326 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 327 | |
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| 328 | /* variables */ |
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| 329 | |
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[deaf716] | 330 | extern Context_Control_fp _CPU_Null_fp_context; |
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[7908ba5b] | 331 | |
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[a6d48e3] | 332 | #endif /* ASM */ |
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| 333 | |
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[7908ba5b] | 334 | /* constants */ |
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| 335 | |
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| 336 | /* |
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| 337 | * This defines the number of levels and the mask used to pick those |
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| 338 | * bits out of a thread mode. |
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| 339 | */ |
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| 340 | |
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| 341 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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| 342 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 343 | |
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| 344 | /* |
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| 345 | * extra stack required by the MPCI receive server thread |
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| 346 | */ |
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| 347 | |
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| 348 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 349 | |
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[4db30283] | 350 | /* |
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| 351 | * This is defined if the port has a special way to report the ISR nesting |
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| 352 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 353 | */ |
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| 354 | |
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| 355 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 356 | |
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[7908ba5b] | 357 | /* |
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| 358 | * Minimum size of a thread's stack. |
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| 359 | */ |
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| 360 | |
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[6952f3d] | 361 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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[7908ba5b] | 362 | |
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[f1738ed] | 363 | #define CPU_SIZEOF_POINTER 4 |
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| 364 | |
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[7908ba5b] | 365 | /* |
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| 366 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 367 | */ |
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| 368 | |
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| 369 | #define CPU_ALIGNMENT 4 |
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| 370 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 371 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 372 | |
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| 373 | /* |
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| 374 | * On i386 thread stacks require no further alignment after allocation |
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[a6d48e3] | 375 | * from the Workspace. However, since gcc maintains 16-byte alignment |
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| 376 | * we try to respect that. If you find an option to let gcc squeeze |
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| 377 | * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still |
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| 378 | * doesn't waste much space since this only determines the *initial* |
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| 379 | * alignment. |
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[7908ba5b] | 380 | */ |
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| 381 | |
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[a6d48e3] | 382 | #define CPU_STACK_ALIGNMENT 16 |
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[7908ba5b] | 383 | |
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| 384 | /* macros */ |
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| 385 | |
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[a6d48e3] | 386 | #ifndef ASM |
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[7908ba5b] | 387 | /* |
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| 388 | * ISR handler macros |
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| 389 | * |
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| 390 | * These macros perform the following functions: |
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[effa6593] | 391 | * + initialize the RTEMS vector table |
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[7908ba5b] | 392 | * + disable all maskable CPU interrupts |
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| 393 | * + restore previous interrupt level (enable) |
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| 394 | * + temporarily restore interrupts (flash) |
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| 395 | * + set a particular level |
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| 396 | */ |
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| 397 | |
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[3267f95] | 398 | #if !defined(RTEMS_PARAVIRT) |
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[7908ba5b] | 399 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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| 400 | |
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| 401 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 402 | |
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| 403 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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| 404 | |
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| 405 | #define _CPU_ISR_Set_level( _new_level ) \ |
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| 406 | { \ |
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[c05f6238] | 407 | if ( _new_level ) __asm__ volatile ( "cli" ); \ |
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| 408 | else __asm__ volatile ( "sti" ); \ |
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[7908ba5b] | 409 | } |
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[3267f95] | 410 | #else |
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[dda25b1] | 411 | #define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts() |
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[3267f95] | 412 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 413 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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[dda25b1] | 414 | #define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) |
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[3267f95] | 415 | #endif |
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[7908ba5b] | 416 | |
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[e6aeabd] | 417 | uint32_t _CPU_ISR_Get_level( void ); |
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[7908ba5b] | 418 | |
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[42e243e] | 419 | /* Make sure interrupt stack has space for ISR |
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[b01d7c7] | 420 | * 'vector' arg at the top and that it is aligned |
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| 421 | * properly. |
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| 422 | */ |
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| 423 | |
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| 424 | #define _CPU_Interrupt_stack_setup( _lo, _hi ) \ |
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| 425 | do { \ |
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| 426 | _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ |
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| 427 | } while (0) |
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| 428 | |
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[a6d48e3] | 429 | #endif /* ASM */ |
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| 430 | |
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[7908ba5b] | 431 | /* end of ISR handler macros */ |
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| 432 | |
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| 433 | /* |
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| 434 | * Context handler macros |
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| 435 | * |
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| 436 | * These macros perform the following functions: |
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| 437 | * + initialize a context area |
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| 438 | * + restart the current thread |
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| 439 | * + calculate the initial pointer into a FP context area |
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| 440 | * + initialize an FP context area |
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| 441 | */ |
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| 442 | |
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| 443 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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| 444 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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| 445 | |
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[a6d48e3] | 446 | #ifndef ASM |
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| 447 | |
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| 448 | /* |
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| 449 | * Stack alignment note: |
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[42e243e] | 450 | * |
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[a6d48e3] | 451 | * We want the stack to look to the '_entry_point' routine |
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| 452 | * like an ordinary stack frame as if '_entry_point' was |
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| 453 | * called from C-code. |
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| 454 | * Note that '_entry_point' is jumped-to by the 'ret' |
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| 455 | * instruction returning from _CPU_Context_switch() or |
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| 456 | * _CPU_Context_restore() thus popping the _entry_point |
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| 457 | * from the stack. |
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| 458 | * However, _entry_point expects a frame to look like this: |
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| 459 | * |
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| 460 | * args [_Thread_Handler expects no args, however] |
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| 461 | * ------ (alignment boundary) |
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| 462 | * SP-> return_addr return here when _entry_point returns which (never happens) |
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| 463 | * |
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[42e243e] | 464 | * |
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[a6d48e3] | 465 | * Hence we must initialize the stack as follows |
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| 466 | * |
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| 467 | * [arg1 ]: n/a |
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| 468 | * [arg0 (aligned)]: n/a |
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| 469 | * [ret. addr ]: NULL |
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| 470 | * SP-> [jump-target ]: _entry_point |
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| 471 | * |
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| 472 | * When Context_switch returns it pops the _entry_point from |
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| 473 | * the stack which then finds a standard layout. |
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| 474 | */ |
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| 475 | |
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| 476 | |
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[38b59a6] | 477 | |
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[7908ba5b] | 478 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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[022851a] | 479 | _isr, _entry_point, _is_fp, _tls_area ) \ |
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[7908ba5b] | 480 | do { \ |
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[e6aeabd] | 481 | uint32_t _stack; \ |
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[7908ba5b] | 482 | \ |
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[6c8e0dc8] | 483 | (void) _is_fp; /* avoid warning for being unused */ \ |
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[7908ba5b] | 484 | if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ |
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| 485 | else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ |
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| 486 | \ |
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[a6d48e3] | 487 | _stack = ((uint32_t)(_stack_base)) + (_size); \ |
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| 488 | _stack &= ~ (CPU_STACK_ALIGNMENT - 1); \ |
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| 489 | _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ \ |
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[7908ba5b] | 490 | *((proc_ptr *)(_stack)) = (_entry_point); \ |
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[020363d] | 491 | (_the_context)->ebp = (void *) 0; \ |
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[7908ba5b] | 492 | (_the_context)->esp = (void *) _stack; \ |
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| 493 | } while (0) |
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| 494 | |
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| 495 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 496 | _CPU_Context_restore( (_the_context) ); |
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| 497 | |
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[06dcaf0] | 498 | #if defined(RTEMS_SMP) |
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[53e008b] | 499 | uint32_t _CPU_SMP_Initialize( void ); |
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| 500 | |
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| 501 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 502 | |
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| 503 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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[4627fcd] | 504 | |
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[c34f94f7] | 505 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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| 506 | |
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[47d60134] | 507 | uint32_t _CPU_SMP_Get_current_processor( void ); |
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[39e51758] | 508 | |
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[ca63ae2] | 509 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 510 | |
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[07f6e419] | 511 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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[2f6108f9] | 512 | { |
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| 513 | __asm__ volatile ( "" : : : "memory" ); |
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| 514 | } |
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| 515 | |
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[f7740e97] | 516 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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[2f6108f9] | 517 | { |
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| 518 | __asm__ volatile ( "" : : : "memory" ); |
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| 519 | } |
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[06dcaf0] | 520 | #endif |
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| 521 | |
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[7908ba5b] | 522 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 523 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 524 | |
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| 525 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 526 | { \ |
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[af063f6] | 527 | memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ |
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[7908ba5b] | 528 | } |
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| 529 | |
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| 530 | /* end of Context handler macros */ |
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| 531 | |
---|
| 532 | /* |
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| 533 | * Fatal Error manager macros |
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| 534 | * |
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| 535 | * These macros perform the following functions: |
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| 536 | * + disable interrupts and halt the CPU |
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| 537 | */ |
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| 538 | |
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[505dc61] | 539 | extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) |
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| 540 | RTEMS_NO_RETURN; |
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[7908ba5b] | 541 | |
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[a6d48e3] | 542 | #endif /* ASM */ |
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| 543 | |
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[7908ba5b] | 544 | /* end of Fatal Error manager macros */ |
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| 545 | |
---|
| 546 | /* |
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| 547 | * Bitfield handler macros |
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| 548 | * |
---|
| 549 | * These macros perform the following functions: |
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| 550 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 551 | */ |
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| 552 | |
---|
| 553 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 554 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 555 | |
---|
| 556 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 557 | { \ |
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[e6aeabd] | 558 | register uint16_t __value_in_register = (_value); \ |
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[7908ba5b] | 559 | \ |
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| 560 | _output = 0; \ |
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| 561 | \ |
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[c05f6238] | 562 | __asm__ volatile ( "bsfw %0,%1 " \ |
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[7908ba5b] | 563 | : "=r" (__value_in_register), "=r" (_output) \ |
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| 564 | : "0" (__value_in_register), "1" (_output) \ |
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| 565 | ); \ |
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| 566 | } |
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| 567 | |
---|
| 568 | /* end of Bitfield handler macros */ |
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| 569 | |
---|
| 570 | /* |
---|
| 571 | * Priority handler macros |
---|
| 572 | * |
---|
| 573 | * These macros perform the following functions: |
---|
| 574 | * + return a mask with the bit for this major/minor portion of |
---|
| 575 | * of thread priority set. |
---|
| 576 | * + translate the bit number returned by "Bitfield_find_first_bit" |
---|
| 577 | * into an index into the thread ready chain bit maps |
---|
| 578 | */ |
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| 579 | |
---|
| 580 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 581 | ( 1 << (_bit_number) ) |
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| 582 | |
---|
| 583 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 584 | (_priority) |
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| 585 | |
---|
| 586 | /* functions */ |
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| 587 | |
---|
[a6d48e3] | 588 | #ifndef ASM |
---|
[7908ba5b] | 589 | /* |
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| 590 | * _CPU_Initialize |
---|
| 591 | * |
---|
| 592 | * This routine performs CPU dependent initialization. |
---|
| 593 | */ |
---|
| 594 | |
---|
[c03e2bc] | 595 | void _CPU_Initialize(void); |
---|
[7908ba5b] | 596 | |
---|
| 597 | /* |
---|
| 598 | * _CPU_ISR_install_raw_handler |
---|
| 599 | * |
---|
[84c53452] | 600 | * This routine installs a "raw" interrupt handler directly into the |
---|
[7908ba5b] | 601 | * processor's vector table. |
---|
| 602 | */ |
---|
[84c53452] | 603 | |
---|
[7908ba5b] | 604 | void _CPU_ISR_install_raw_handler( |
---|
[e6aeabd] | 605 | uint32_t vector, |
---|
[7908ba5b] | 606 | proc_ptr new_handler, |
---|
| 607 | proc_ptr *old_handler |
---|
| 608 | ); |
---|
| 609 | |
---|
| 610 | /* |
---|
| 611 | * _CPU_ISR_install_vector |
---|
| 612 | * |
---|
| 613 | * This routine installs an interrupt vector. |
---|
| 614 | */ |
---|
| 615 | |
---|
| 616 | void _CPU_ISR_install_vector( |
---|
[e6aeabd] | 617 | uint32_t vector, |
---|
[7908ba5b] | 618 | proc_ptr new_handler, |
---|
| 619 | proc_ptr *old_handler |
---|
| 620 | ); |
---|
| 621 | |
---|
| 622 | /* |
---|
| 623 | * _CPU_Thread_Idle_body |
---|
| 624 | * |
---|
| 625 | * Use the halt instruction of low power mode of a particular i386 model. |
---|
| 626 | */ |
---|
| 627 | |
---|
| 628 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
---|
| 629 | |
---|
[cca8379] | 630 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
[7908ba5b] | 631 | |
---|
| 632 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
---|
| 633 | |
---|
| 634 | /* |
---|
| 635 | * _CPU_Context_switch |
---|
| 636 | * |
---|
| 637 | * This routine switches from the run context to the heir context. |
---|
| 638 | */ |
---|
| 639 | |
---|
| 640 | void _CPU_Context_switch( |
---|
| 641 | Context_Control *run, |
---|
| 642 | Context_Control *heir |
---|
| 643 | ); |
---|
| 644 | |
---|
| 645 | /* |
---|
| 646 | * _CPU_Context_restore |
---|
| 647 | * |
---|
| 648 | * This routine is generally used only to restart self in an |
---|
| 649 | * efficient manner and avoid stack conflicts. |
---|
| 650 | */ |
---|
| 651 | |
---|
| 652 | void _CPU_Context_restore( |
---|
| 653 | Context_Control *new_context |
---|
[143696a] | 654 | ) RTEMS_NO_RETURN; |
---|
[7908ba5b] | 655 | |
---|
| 656 | /* |
---|
| 657 | * _CPU_Context_save_fp |
---|
| 658 | * |
---|
| 659 | * This routine saves the floating point context passed to it. |
---|
| 660 | */ |
---|
| 661 | |
---|
[b02f4cc1] | 662 | #ifdef __SSE__ |
---|
| 663 | #define _CPU_Context_save_fp(fp_context_pp) \ |
---|
| 664 | do { \ |
---|
| 665 | __asm__ __volatile__( \ |
---|
| 666 | "fstcw %0" \ |
---|
| 667 | :"=m"((*(fp_context_pp))->fpucw) \ |
---|
| 668 | ); \ |
---|
| 669 | __asm__ __volatile__( \ |
---|
| 670 | "stmxcsr %0" \ |
---|
| 671 | :"=m"((*(fp_context_pp))->mxcsr) \ |
---|
| 672 | ); \ |
---|
| 673 | } while (0) |
---|
| 674 | #else |
---|
[7908ba5b] | 675 | void _CPU_Context_save_fp( |
---|
[3c86f88] | 676 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 677 | ); |
---|
[b02f4cc1] | 678 | #endif |
---|
[7908ba5b] | 679 | |
---|
| 680 | /* |
---|
| 681 | * _CPU_Context_restore_fp |
---|
| 682 | * |
---|
| 683 | * This routine restores the floating point context passed to it. |
---|
| 684 | */ |
---|
[b02f4cc1] | 685 | #ifdef __SSE__ |
---|
| 686 | #define _CPU_Context_restore_fp(fp_context_pp) \ |
---|
| 687 | do { \ |
---|
| 688 | __asm__ __volatile__( \ |
---|
| 689 | "fldcw %0" \ |
---|
| 690 | ::"m"((*(fp_context_pp))->fpucw) \ |
---|
| 691 | :"fpcr" \ |
---|
| 692 | ); \ |
---|
| 693 | __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ |
---|
| 694 | } while (0) |
---|
| 695 | #else |
---|
[7908ba5b] | 696 | void _CPU_Context_restore_fp( |
---|
[3c86f88] | 697 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 698 | ); |
---|
[b02f4cc1] | 699 | #endif |
---|
| 700 | |
---|
| 701 | #ifdef __SSE__ |
---|
| 702 | #define _CPU_Context_Initialization_at_thread_begin() \ |
---|
| 703 | do { \ |
---|
| 704 | __asm__ __volatile__( \ |
---|
| 705 | "finit" \ |
---|
| 706 | : \ |
---|
| 707 | : \ |
---|
| 708 | :"st","st(1)","st(2)","st(3)", \ |
---|
| 709 | "st(4)","st(5)","st(6)","st(7)", \ |
---|
| 710 | "fpsr","fpcr" \ |
---|
| 711 | ); \ |
---|
| 712 | if ( _Thread_Executing->fp_context ) { \ |
---|
| 713 | _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ |
---|
| 714 | } \ |
---|
| 715 | } while (0) |
---|
| 716 | #endif |
---|
[7908ba5b] | 717 | |
---|
[39993d6] | 718 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
| 719 | { |
---|
| 720 | /* TODO */ |
---|
| 721 | } |
---|
| 722 | |
---|
| 723 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
| 724 | { |
---|
| 725 | while (1) { |
---|
| 726 | /* TODO */ |
---|
| 727 | } |
---|
| 728 | } |
---|
| 729 | |
---|
[815994f] | 730 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
| 731 | |
---|
[24bf11e] | 732 | typedef uint32_t CPU_Counter_ticks; |
---|
| 733 | |
---|
| 734 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
| 735 | |
---|
| 736 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 737 | CPU_Counter_ticks second, |
---|
| 738 | CPU_Counter_ticks first |
---|
| 739 | ) |
---|
| 740 | { |
---|
| 741 | return second - first; |
---|
| 742 | } |
---|
| 743 | |
---|
[a6d48e3] | 744 | #endif /* ASM */ |
---|
| 745 | |
---|
[7908ba5b] | 746 | #ifdef __cplusplus |
---|
| 747 | } |
---|
| 748 | #endif |
---|
| 749 | |
---|
| 750 | #endif |
---|