[7908ba5b] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Intel |
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| 4 | * i386 processor. |
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| 5 | * |
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[08311cc3] | 6 | * COPYRIGHT (c) 1989-1999. |
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[7908ba5b] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * http://www.OARcorp.com/rtems/license.html. |
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| 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __CPU_h |
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| 17 | #define __CPU_h |
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| 18 | |
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| 19 | #ifdef __cplusplus |
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| 20 | extern "C" { |
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| 21 | #endif |
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| 22 | |
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| 23 | #include <rtems/score/i386.h> /* pick up machine definitions */ |
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| 24 | |
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| 25 | #ifndef ASM |
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[8c82fa79] | 26 | #include <rtems/score/types.h> |
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[a324355] | 27 | #include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ |
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| 28 | #include <rtems/score/registers.h> /* formerly part of libcpu */ |
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[7908ba5b] | 29 | #endif |
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| 30 | |
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| 31 | /* conditional compilation parameters */ |
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| 32 | |
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| 33 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 34 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 35 | |
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| 36 | /* |
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| 37 | * i386 has an RTEMS allocated and managed interrupt stack. |
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| 38 | */ |
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| 39 | |
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| 40 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 41 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 42 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 43 | |
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| 44 | /* |
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| 45 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 46 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 47 | * number (0)? |
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| 48 | */ |
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| 49 | |
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| 50 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 51 | |
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| 52 | /* |
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| 53 | * Some family members have no FP, some have an FPU such as the i387 |
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| 54 | * for the i386, others have it built in (i486DX, Pentium). |
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| 55 | */ |
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| 56 | |
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| 57 | #if ( I386_HAS_FPU == 1 ) |
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| 58 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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| 59 | #else |
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| 60 | #define CPU_HARDWARE_FP FALSE |
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| 61 | #endif |
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[17508d02] | 62 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 63 | |
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| 64 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 65 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 66 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 67 | |
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| 68 | #define CPU_STACK_GROWS_UP FALSE |
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| 69 | #define CPU_STRUCTURE_ALIGNMENT |
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| 70 | |
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| 71 | /* |
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| 72 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 73 | * |
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| 74 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 75 | * must be provided and is the default IDLE thread body instead of |
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| 76 | * _CPU_Thread_Idle_body. |
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| 77 | * |
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| 78 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 79 | * not provide one. |
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| 80 | */ |
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| 81 | |
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| 82 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 83 | |
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| 84 | /* |
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| 85 | * Define what is required to specify how the network to host conversion |
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| 86 | * routines are handled. |
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| 87 | */ |
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| 88 | |
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[6805640e] | 89 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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[7908ba5b] | 90 | #define CPU_BIG_ENDIAN FALSE |
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| 91 | #define CPU_LITTLE_ENDIAN TRUE |
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| 92 | |
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| 93 | /* structures */ |
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| 94 | |
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| 95 | /* |
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| 96 | * Basic integer context for the i386 family. |
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| 97 | */ |
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| 98 | |
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| 99 | typedef struct { |
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| 100 | unsigned32 eflags; /* extended flags register */ |
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| 101 | void *esp; /* extended stack pointer register */ |
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| 102 | void *ebp; /* extended base pointer register */ |
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| 103 | unsigned32 ebx; /* extended bx register */ |
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| 104 | unsigned32 esi; /* extended source index register */ |
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| 105 | unsigned32 edi; /* extended destination index flags register */ |
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| 106 | } Context_Control; |
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| 107 | |
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| 108 | /* |
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| 109 | * FP context save area for the i387 numeric coprocessors. |
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| 110 | */ |
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| 111 | |
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| 112 | typedef struct { |
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| 113 | unsigned8 fp_save_area[108]; /* context size area for I80387 */ |
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| 114 | /* 28 bytes for environment */ |
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| 115 | } Context_Control_fp; |
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| 116 | |
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| 117 | |
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| 118 | /* |
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| 119 | * The following structure defines the set of information saved |
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| 120 | * on the current stack by RTEMS upon receipt of execptions. |
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| 121 | * |
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| 122 | * idtIndex is either the interrupt number or the trap/exception number. |
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| 123 | * faultCode is the code pushed by the processor on some exceptions. |
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| 124 | */ |
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| 125 | |
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| 126 | typedef struct { |
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| 127 | unsigned32 edi; |
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| 128 | unsigned32 esi; |
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| 129 | unsigned32 ebp; |
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| 130 | unsigned32 esp0; |
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| 131 | unsigned32 ebx; |
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| 132 | unsigned32 edx; |
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| 133 | unsigned32 ecx; |
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| 134 | unsigned32 eax; |
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| 135 | unsigned32 idtIndex; |
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| 136 | unsigned32 faultCode; |
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| 137 | unsigned32 eip; |
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| 138 | unsigned32 cs; |
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| 139 | unsigned32 eflags; |
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| 140 | } CPU_Exception_frame; |
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| 141 | |
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| 142 | typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); |
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| 143 | extern cpuExcHandlerType _currentExcHandler; |
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| 144 | extern void rtems_exception_init_mngt(); |
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| 145 | |
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| 146 | /* |
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| 147 | * The following structure defines the set of information saved |
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| 148 | * on the current stack by RTEMS upon receipt of each interrupt |
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| 149 | * that will lead to re-enter the kernel to signal the thread. |
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| 150 | */ |
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| 151 | |
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| 152 | typedef CPU_Exception_frame CPU_Interrupt_frame; |
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| 153 | |
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| 154 | typedef enum { |
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| 155 | I386_EXCEPTION_DIVIDE_BY_ZERO = 0, |
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| 156 | I386_EXCEPTION_DEBUG = 1, |
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| 157 | I386_EXCEPTION_NMI = 2, |
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| 158 | I386_EXCEPTION_BREAKPOINT = 3, |
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| 159 | I386_EXCEPTION_OVERFLOW = 4, |
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| 160 | I386_EXCEPTION_BOUND = 5, |
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| 161 | I386_EXCEPTION_ILLEGAL_INSTR = 6, |
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| 162 | I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, |
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| 163 | I386_EXCEPTION_DOUBLE_FAULT = 8, |
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| 164 | I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, |
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| 165 | I386_EXCEPTION_INVALID_TSS = 10, |
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| 166 | I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, |
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| 167 | I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, |
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| 168 | I386_EXCEPTION_GENERAL_PROT_ERR = 13, |
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| 169 | I386_EXCEPTION_PAGE_FAULT = 14, |
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| 170 | I386_EXCEPTION_INTEL_RES15 = 15, |
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| 171 | I386_EXCEPTION_FLOAT_ERROR = 16, |
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| 172 | I386_EXCEPTION_ALIGN_CHECK = 17, |
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| 173 | I386_EXCEPTION_MACHINE_CHECK = 18, |
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| 174 | I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ |
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| 175 | |
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| 176 | } Intel_symbolic_exception_name; |
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| 177 | |
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| 178 | |
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| 179 | /* |
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| 180 | * The following table contains the information required to configure |
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| 181 | * the i386 specific parameters. |
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| 182 | */ |
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| 183 | |
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| 184 | typedef struct { |
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| 185 | void (*pretasking_hook)( void ); |
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| 186 | void (*predriver_hook)( void ); |
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| 187 | void (*postdriver_hook)( void ); |
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| 188 | void (*idle_task)( void ); |
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| 189 | boolean do_zero_of_workspace; |
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| 190 | unsigned32 idle_task_stack_size; |
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| 191 | unsigned32 interrupt_stack_size; |
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| 192 | unsigned32 extra_mpci_receive_server_stack; |
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| 193 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 194 | void (*stack_free_hook)( void* ); |
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| 195 | /* end of fields required on all CPUs */ |
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| 196 | |
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| 197 | unsigned32 interrupt_table_segment; |
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| 198 | void *interrupt_table_offset; |
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| 199 | } rtems_cpu_table; |
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| 200 | |
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[458bd34] | 201 | /* |
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| 202 | * Macros to access required entires in the CPU Table are in |
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| 203 | * the file rtems/system.h. |
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| 204 | */ |
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| 205 | |
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| 206 | /* |
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| 207 | * Macros to access i386 specific additions to the CPU Table |
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| 208 | */ |
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| 209 | |
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| 210 | #define rtems_cpu_configuration_get_interrupt_table_segment() \ |
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| 211 | (_CPU_Table.interrupt_table_segment) |
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| 212 | |
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| 213 | #define rtems_cpu_configuration_get_interrupt_table_offset() \ |
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| 214 | (_CPU_Table.interrupt_table_offset) |
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| 215 | |
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[7908ba5b] | 216 | /* |
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| 217 | * context size area for floating point |
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| 218 | * |
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| 219 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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| 220 | */ |
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| 221 | |
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| 222 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 223 | |
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| 224 | /* variables */ |
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| 225 | |
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| 226 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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| 227 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 228 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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| 229 | |
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| 230 | /* constants */ |
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| 231 | |
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| 232 | /* |
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| 233 | * This defines the number of levels and the mask used to pick those |
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| 234 | * bits out of a thread mode. |
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| 235 | */ |
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| 236 | |
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| 237 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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| 238 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 239 | |
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| 240 | /* |
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| 241 | * extra stack required by the MPCI receive server thread |
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| 242 | */ |
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| 243 | |
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| 244 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 245 | |
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| 246 | /* |
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| 247 | * i386 family supports 256 distinct vectors. |
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| 248 | */ |
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| 249 | |
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| 250 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 251 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 252 | |
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[4db30283] | 253 | /* |
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| 254 | * This is defined if the port has a special way to report the ISR nesting |
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| 255 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 256 | */ |
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| 257 | |
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| 258 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 259 | |
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[7908ba5b] | 260 | /* |
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| 261 | * Minimum size of a thread's stack. |
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| 262 | */ |
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| 263 | |
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| 264 | #define CPU_STACK_MINIMUM_SIZE 1024 |
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| 265 | |
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| 266 | /* |
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| 267 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 268 | */ |
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| 269 | |
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| 270 | #define CPU_ALIGNMENT 4 |
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| 271 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 272 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 273 | |
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| 274 | /* |
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| 275 | * On i386 thread stacks require no further alignment after allocation |
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| 276 | * from the Workspace. |
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| 277 | */ |
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| 278 | |
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| 279 | #define CPU_STACK_ALIGNMENT 0 |
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| 280 | |
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| 281 | /* macros */ |
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| 282 | |
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| 283 | /* |
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| 284 | * ISR handler macros |
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| 285 | * |
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| 286 | * These macros perform the following functions: |
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[effa6593] | 287 | * + initialize the RTEMS vector table |
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[7908ba5b] | 288 | * + disable all maskable CPU interrupts |
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| 289 | * + restore previous interrupt level (enable) |
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| 290 | * + temporarily restore interrupts (flash) |
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| 291 | * + set a particular level |
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| 292 | */ |
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| 293 | |
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[effa6593] | 294 | #define _CPU_Initialize_vectors() |
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| 295 | |
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[7908ba5b] | 296 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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| 297 | |
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| 298 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 299 | |
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| 300 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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| 301 | |
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| 302 | #define _CPU_ISR_Set_level( _new_level ) \ |
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| 303 | { \ |
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| 304 | if ( _new_level ) asm volatile ( "cli" ); \ |
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| 305 | else asm volatile ( "sti" ); \ |
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| 306 | } |
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| 307 | |
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| 308 | unsigned32 _CPU_ISR_Get_level( void ); |
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| 309 | |
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| 310 | /* end of ISR handler macros */ |
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| 311 | |
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| 312 | /* |
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| 313 | * Context handler macros |
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| 314 | * |
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| 315 | * These macros perform the following functions: |
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| 316 | * + initialize a context area |
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| 317 | * + restart the current thread |
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| 318 | * + calculate the initial pointer into a FP context area |
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| 319 | * + initialize an FP context area |
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| 320 | */ |
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| 321 | |
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| 322 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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| 323 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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| 324 | |
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| 325 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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| 326 | _isr, _entry_point, _is_fp ) \ |
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| 327 | do { \ |
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| 328 | unsigned32 _stack; \ |
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| 329 | \ |
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| 330 | if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ |
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| 331 | else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ |
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| 332 | \ |
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| 333 | _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ |
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| 334 | \ |
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| 335 | *((proc_ptr *)(_stack)) = (_entry_point); \ |
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| 336 | (_the_context)->ebp = (void *) _stack; \ |
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| 337 | (_the_context)->esp = (void *) _stack; \ |
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| 338 | } while (0) |
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| 339 | |
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| 340 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 341 | _CPU_Context_restore( (_the_context) ); |
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| 342 | |
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| 343 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 344 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 345 | |
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| 346 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 347 | { \ |
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| 348 | unsigned32 *_source = (unsigned32 *) &_CPU_Null_fp_context; \ |
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| 349 | unsigned32 *_destination = *(_fp_area); \ |
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| 350 | unsigned32 _index; \ |
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| 351 | \ |
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| 352 | for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \ |
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| 353 | *_destination++ = *_source++; \ |
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| 354 | } |
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| 355 | |
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| 356 | /* end of Context handler macros */ |
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| 357 | |
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| 358 | /* |
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| 359 | * Fatal Error manager macros |
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| 360 | * |
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| 361 | * These macros perform the following functions: |
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| 362 | * + disable interrupts and halt the CPU |
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| 363 | */ |
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| 364 | |
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| 365 | #define _CPU_Fatal_halt( _error ) \ |
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| 366 | { \ |
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| 367 | asm volatile ( "cli ; \ |
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| 368 | movl %0,%%eax ; \ |
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| 369 | hlt" \ |
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| 370 | : "=r" ((_error)) : "0" ((_error)) \ |
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| 371 | ); \ |
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| 372 | } |
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| 373 | |
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| 374 | /* end of Fatal Error manager macros */ |
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| 375 | |
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| 376 | /* |
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| 377 | * Bitfield handler macros |
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| 378 | * |
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| 379 | * These macros perform the following functions: |
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| 380 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 381 | */ |
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| 382 | |
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| 383 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 384 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 385 | |
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| 386 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 387 | { \ |
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| 388 | register unsigned16 __value_in_register = (_value); \ |
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| 389 | \ |
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| 390 | _output = 0; \ |
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| 391 | \ |
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| 392 | asm volatile ( "bsfw %0,%1 " \ |
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| 393 | : "=r" (__value_in_register), "=r" (_output) \ |
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| 394 | : "0" (__value_in_register), "1" (_output) \ |
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| 395 | ); \ |
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| 396 | } |
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| 397 | |
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| 398 | /* end of Bitfield handler macros */ |
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| 399 | |
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| 400 | /* |
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| 401 | * Priority handler macros |
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| 402 | * |
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| 403 | * These macros perform the following functions: |
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| 404 | * + return a mask with the bit for this major/minor portion of |
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| 405 | * of thread priority set. |
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| 406 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 407 | * into an index into the thread ready chain bit maps |
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| 408 | */ |
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| 409 | |
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| 410 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 411 | ( 1 << (_bit_number) ) |
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| 412 | |
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| 413 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 414 | (_priority) |
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| 415 | |
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| 416 | /* functions */ |
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| 417 | |
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| 418 | /* |
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| 419 | * _CPU_Initialize |
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| 420 | * |
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| 421 | * This routine performs CPU dependent initialization. |
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| 422 | */ |
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| 423 | |
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| 424 | void _CPU_Initialize( |
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| 425 | rtems_cpu_table *cpu_table, |
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| 426 | void (*thread_dispatch) |
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| 427 | ); |
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| 428 | |
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| 429 | /* |
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| 430 | * _CPU_ISR_install_raw_handler |
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| 431 | * |
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| 432 | * This routine installs a "raw" interrupt handler directly into the |
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| 433 | * processor's vector table. |
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| 434 | */ |
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| 435 | |
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| 436 | void _CPU_ISR_install_raw_handler( |
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| 437 | unsigned32 vector, |
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| 438 | proc_ptr new_handler, |
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| 439 | proc_ptr *old_handler |
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| 440 | ); |
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| 441 | |
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| 442 | /* |
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| 443 | * _CPU_ISR_install_vector |
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| 444 | * |
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| 445 | * This routine installs an interrupt vector. |
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| 446 | */ |
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| 447 | |
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| 448 | void _CPU_ISR_install_vector( |
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| 449 | unsigned32 vector, |
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| 450 | proc_ptr new_handler, |
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| 451 | proc_ptr *old_handler |
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| 452 | ); |
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| 453 | |
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| 454 | /* |
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| 455 | * _CPU_Thread_Idle_body |
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| 456 | * |
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| 457 | * Use the halt instruction of low power mode of a particular i386 model. |
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| 458 | */ |
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| 459 | |
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| 460 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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| 461 | |
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| 462 | void _CPU_Thread_Idle_body( void ); |
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| 463 | |
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| 464 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
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| 465 | |
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| 466 | /* |
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| 467 | * _CPU_Context_switch |
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| 468 | * |
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| 469 | * This routine switches from the run context to the heir context. |
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| 470 | */ |
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| 471 | |
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| 472 | void _CPU_Context_switch( |
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| 473 | Context_Control *run, |
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| 474 | Context_Control *heir |
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| 475 | ); |
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| 476 | |
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| 477 | /* |
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| 478 | * _CPU_Context_restore |
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| 479 | * |
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| 480 | * This routine is generally used only to restart self in an |
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| 481 | * efficient manner and avoid stack conflicts. |
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| 482 | */ |
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| 483 | |
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| 484 | void _CPU_Context_restore( |
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| 485 | Context_Control *new_context |
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| 486 | ); |
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| 487 | |
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| 488 | /* |
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| 489 | * _CPU_Context_save_fp |
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| 490 | * |
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| 491 | * This routine saves the floating point context passed to it. |
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| 492 | */ |
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| 493 | |
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| 494 | void _CPU_Context_save_fp( |
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| 495 | void **fp_context_ptr |
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| 496 | ); |
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| 497 | |
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| 498 | /* |
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| 499 | * _CPU_Context_restore_fp |
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| 500 | * |
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| 501 | * This routine restores the floating point context passed to it. |
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| 502 | */ |
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| 503 | |
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| 504 | void _CPU_Context_restore_fp( |
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| 505 | void **fp_context_ptr |
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| 506 | ); |
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| 507 | |
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| 508 | #ifdef __cplusplus |
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| 509 | } |
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| 510 | #endif |
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| 511 | |
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| 512 | #endif |
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| 513 | /* end of include file */ |
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