1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @brief Intel I386 Interrupt Macros |
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7 | * |
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8 | * Formerly contained in and extracted from libcpu/i386/cpu.h |
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9 | * |
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10 | * Applications must not include this file directly. |
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11 | */ |
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12 | |
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13 | /* |
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14 | * COPYRIGHT (c) 1998 valette@crf.canon.fr |
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15 | * |
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16 | * Redistribution and use in source and binary forms, with or without |
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17 | * modification, are permitted provided that the following conditions |
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18 | * are met: |
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19 | * 1. Redistributions of source code must retain the above copyright |
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20 | * notice, this list of conditions and the following disclaimer. |
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21 | * 2. Redistributions in binary form must reproduce the above copyright |
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22 | * notice, this list of conditions and the following disclaimer in the |
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23 | * documentation and/or other materials provided with the distribution. |
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24 | * |
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25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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28 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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29 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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35 | * POSSIBILITY OF SUCH DAMAGE. |
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36 | */ |
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37 | |
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38 | /** |
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39 | * @defgroup RTEMSScoreCPUi386Interrupt Processor Dependent Interrupt Management |
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40 | * |
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41 | * @ingroup RTEMSScoreCPUi386 |
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42 | * |
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43 | * @brief i386 Interrupt Management |
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44 | */ |
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45 | /**@{**/ |
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46 | |
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47 | #ifndef _RTEMS_SCORE_INTERRUPTS_H |
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48 | #define _RTEMS_SCORE_INTERRUPTS_H |
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49 | |
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50 | #ifndef ASM |
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51 | |
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52 | struct __rtems_raw_irq_connect_data__; |
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53 | |
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54 | typedef void (*rtems_raw_irq_hdl) (void); |
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55 | typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*); |
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56 | typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*); |
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57 | typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*); |
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58 | |
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59 | /** |
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60 | * @name Interrupt Level Macros |
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61 | * |
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62 | */ |
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63 | /**@{**/ |
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64 | #if !defined(I386_DISABLE_INLINE_ISR_DISABLE_ENABLE) |
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65 | #define i386_disable_interrupts( _level ) \ |
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66 | { \ |
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67 | __asm__ volatile ( "pushf ; \ |
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68 | cli ; \ |
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69 | pop %0" \ |
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70 | : "=rm" ((_level)) \ |
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71 | ); \ |
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72 | } |
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73 | |
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74 | #define i386_enable_interrupts( _level ) \ |
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75 | { \ |
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76 | __asm__ volatile ( "push %0 ; \ |
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77 | popf" \ |
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78 | : : "rm" ((_level)) : "cc" \ |
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79 | ); \ |
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80 | } |
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81 | |
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82 | #define i386_flash_interrupts( _level ) \ |
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83 | { \ |
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84 | __asm__ volatile ( "push %0 ; \ |
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85 | popf ; \ |
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86 | cli" \ |
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87 | : : "rm" ((_level)) : "cc" \ |
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88 | ); \ |
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89 | } |
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90 | |
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91 | #define i386_get_interrupt_level( _level ) \ |
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92 | do { \ |
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93 | uint32_t _eflags; \ |
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94 | \ |
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95 | __asm__ volatile ( "pushf ; \ |
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96 | pop %0" \ |
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97 | : "=rm" ((_eflags)) \ |
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98 | ); \ |
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99 | \ |
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100 | _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \ |
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101 | } while (0) |
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102 | #else |
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103 | uint32_t i386_disable_interrupts( void ); |
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104 | void i386_enable_interrupts(uint32_t level); |
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105 | void i386_flash_interrupts(uint32_t level); |
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106 | void i386_set_interrupt_level(uint32_t new_level); |
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107 | uint32_t i386_get_interrupt_level( void ); |
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108 | #endif /* PARAVIRT */ |
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109 | |
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110 | /** @} */ |
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111 | |
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112 | /**@}**/ |
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113 | #endif |
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114 | #endif |
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