source: rtems/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h @ 5d4a1edc

5
Last change on this file since 5d4a1edc was 5d4a1edc, checked in by Jan Sommer <jan.sommer@…>, on May 31, 2020 at 2:22:55 PM

bsp/pc386: Define interrupt stack frame for smp

  • Defines CPU_Interrupt_frame in cpu_impl.h
  • Updates isq_asm.S to save/restore registers in matching order to

interrupt frame

  • Property mode set to 100644
File size: 1.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 2013 embedded brains GmbH
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef _RTEMS_SCORE_CPUIMPL_H
16#define _RTEMS_SCORE_CPUIMPL_H
17
18#include <rtems/score/cpu.h>
19
20/**
21 * @defgroup RTEMSScoreCPUi386 i386
22 *
23 * @ingroup RTEMSScoreCPU
24 *
25 * @brief i386 Architecture Support
26 *
27 * @{
28 */
29
30#define CPU_PER_CPU_CONTROL_SIZE 0
31
32#define CPU_INTERRUPT_FRAME_SIZE 52
33
34#ifndef ASM
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
41{
42  /* TODO */
43}
44
45RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
46{
47  while (1) {
48    /* TODO */
49  }
50}
51
52RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
53{
54  __asm__ volatile ( ".word 0" );
55}
56
57RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
58{
59  __asm__ volatile ( "nop" );
60}
61
62#ifdef __cplusplus
63}
64#endif
65
66#endif /* ASM */
67
68/** @} */
69
70#endif /* _RTEMS_SCORE_CPUIMPL_H */
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