1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @brief CPU Port Implementation API |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH & Co. KG |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the distribution. |
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20 | * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | * POSSIBILITY OF SUCH DAMAGE. |
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32 | */ |
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33 | |
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34 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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35 | #define _RTEMS_SCORE_CPUIMPL_H |
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36 | |
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37 | #include <rtems/score/cpu.h> |
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38 | |
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39 | /** |
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40 | * @defgroup RTEMSScoreCPUi386 i386 |
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41 | * |
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42 | * @ingroup RTEMSScoreCPU |
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43 | * |
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44 | * @brief i386 Architecture Support |
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45 | * |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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50 | |
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51 | #define CPU_INTERRUPT_FRAME_SIZE 52 |
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52 | |
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53 | #define CPU_THREAD_LOCAL_STORAGE_VARIANT 20 |
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54 | |
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55 | #ifndef ASM |
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56 | |
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57 | #ifdef __cplusplus |
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58 | extern "C" { |
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59 | #endif |
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60 | |
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61 | RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); |
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62 | |
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63 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
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64 | { |
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65 | (void) pattern; |
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66 | |
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67 | /* TODO */ |
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68 | } |
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69 | |
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70 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
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71 | { |
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72 | (void) pattern; |
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73 | |
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74 | while (1) { |
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75 | /* TODO */ |
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76 | } |
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77 | } |
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78 | |
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79 | static inline void _CPU_Instruction_illegal( void ) |
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80 | { |
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81 | __asm__ volatile ( ".word 0" ); |
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82 | } |
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83 | |
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84 | static inline void _CPU_Instruction_no_operation( void ) |
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85 | { |
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86 | __asm__ volatile ( "nop" ); |
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87 | } |
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88 | |
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89 | static inline void _CPU_Use_thread_local_storage( |
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90 | const Context_Control *context |
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91 | ) |
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92 | { |
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93 | uint32_t tmp; |
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94 | uint32_t cpu_index; |
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95 | |
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96 | #ifdef RTEMS_SMP |
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97 | cpu_index = _CPU_SMP_Get_current_processor(); |
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98 | #else |
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99 | cpu_index = 0; |
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100 | #endif |
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101 | |
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102 | __asm__ volatile ( |
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103 | "movl " RTEMS_XSTRING( I386_CONTEXT_CONTROL_GS_0_OFFSET ) "(%2), %0\n" |
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104 | "movl %0, _Global_descriptor_table+24(,%1,8)\n" |
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105 | "movl " RTEMS_XSTRING( I386_CONTEXT_CONTROL_GS_1_OFFSET ) "(%2), %0\n" |
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106 | "movl %0, _Global_descriptor_table+28(,%1,8)\n" |
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107 | "leal 24(,%1,8), %0\n" |
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108 | "movl %0, %%gs\n" |
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109 | : "=&r" ( tmp ) |
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110 | : "r" ( cpu_index ), "r" ( context ) |
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111 | : "memory" |
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112 | ); |
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113 | } |
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114 | |
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115 | static inline void *_CPU_Get_TLS_thread_pointer( |
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116 | const Context_Control *context |
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117 | ) |
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118 | { |
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119 | return (void *) &context->gs; |
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120 | } |
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121 | |
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122 | #ifdef __cplusplus |
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123 | } |
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124 | #endif |
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125 | |
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126 | #endif /* ASM */ |
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127 | |
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128 | /** @} */ |
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129 | |
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130 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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