source: rtems/cpukit/score/cpu/i386/include/rtems/score/cpu.h @ 7c39cab

5
Last change on this file since 7c39cab was 7c39cab, checked in by Joel Sherrill <joel@…>, on Mar 12, 2018 at 7:46:29 PM

Rework i386 Paravirtualization to have paravirt.h

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1/**
2 * @file
3 *
4 * @brief Intel I386 CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Intel
7 * i386 processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifndef ASM
23#include <string.h> /* for memcpy */
24#endif
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <rtems/score/basedefs.h>
31#if defined(RTEMS_PARAVIRT)
32#include <rtems/score/paravirt.h>
33#endif
34#include <rtems/score/i386.h>
35
36/* conditional compilation parameters */
37
38/*
39 *  Does the CPU follow the simple vectored interrupt model?
40 *
41 *  If TRUE, then RTEMS allocates the vector table it internally manages.
42 *  If FALSE, then the BSP is assumed to allocate and manage the vector
43 *  table
44 *
45 *  PowerPC Specific Information:
46 *
47 *  The PowerPC and x86 were the first to use the PIC interrupt model.
48 *  They do not use the simple vectored interrupt model.
49 */
50#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
51
52/*
53 *  i386 has an RTEMS allocated and managed interrupt stack.
54 */
55
56#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
57#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
58#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
59
60/*
61 *  Does the RTEMS invoke the user's ISR with the vector number and
62 *  a pointer to the saved interrupt frame (1) or just the vector
63 *  number (0)?
64 */
65
66#define CPU_ISR_PASSES_FRAME_POINTER FALSE
67
68/*
69 *  Some family members have no FP, some have an FPU such as the i387
70 *  for the i386, others have it built in (i486DX, Pentium).
71 */
72
73#ifdef __SSE__
74#define CPU_HARDWARE_FP                  TRUE
75#define CPU_SOFTWARE_FP                  FALSE
76
77#define CPU_ALL_TASKS_ARE_FP             TRUE
78#define CPU_IDLE_TASK_IS_FP              TRUE
79#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
80#else /* __SSE__ */
81
82#if ( I386_HAS_FPU == 1 )
83#define CPU_HARDWARE_FP     TRUE    /* i387 for i386 */
84#else
85#define CPU_HARDWARE_FP     FALSE
86#endif
87#define CPU_SOFTWARE_FP     FALSE
88
89#define CPU_ALL_TASKS_ARE_FP             FALSE
90#define CPU_IDLE_TASK_IS_FP              FALSE
91#if defined(RTEMS_SMP)
92  #define CPU_USE_DEFERRED_FP_SWITCH     FALSE
93#else
94  #define CPU_USE_DEFERRED_FP_SWITCH     TRUE
95#endif
96#endif /* __SSE__ */
97
98#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
99
100#define CPU_STACK_GROWS_UP               FALSE
101
102/* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */
103#define CPU_CACHE_LINE_BYTES 64
104
105#define CPU_STRUCTURE_ALIGNMENT
106
107/*
108 *  Does this port provide a CPU dependent IDLE task implementation?
109 *
110 *  If TRUE, then the routine _CPU_Thread_Idle_body
111 *  must be provided and is the default IDLE thread body instead of
112 *  _CPU_Thread_Idle_body.
113 *
114 *  If FALSE, then use the generic IDLE thread body if the BSP does
115 *  not provide one.
116 */
117
118#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
119
120#define CPU_MAXIMUM_PROCESSORS 32
121
122#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0
123#define I386_CONTEXT_CONTROL_ESP_OFFSET 4
124#define I386_CONTEXT_CONTROL_EBP_OFFSET 8
125#define I386_CONTEXT_CONTROL_EBX_OFFSET 12
126#define I386_CONTEXT_CONTROL_ESI_OFFSET 16
127#define I386_CONTEXT_CONTROL_EDI_OFFSET 20
128#define I386_CONTEXT_CONTROL_GS_0_OFFSET 24
129#define I386_CONTEXT_CONTROL_GS_1_OFFSET 28
130
131#ifdef RTEMS_SMP
132  #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32
133#endif
134
135/* structures */
136
137#ifndef ASM
138
139/*
140 *  Basic integer context for the i386 family.
141 */
142
143typedef struct {
144  uint32_t    eflags;     /* extended flags register                   */
145  void       *esp;        /* extended stack pointer register           */
146  void       *ebp;        /* extended base pointer register            */
147  uint32_t    ebx;        /* extended bx register                      */
148  uint32_t    esi;        /* extended source index register            */
149  uint32_t    edi;        /* extended destination index flags register */
150  segment_descriptors gs; /* gs segment descriptor                     */
151#ifdef RTEMS_SMP
152  volatile bool is_executing;
153#endif
154}   Context_Control;
155
156#define _CPU_Context_Get_SP( _context ) \
157  (_context)->esp
158
159#ifdef RTEMS_SMP
160  static inline bool _CPU_Context_Get_is_executing(
161    const Context_Control *context
162  )
163  {
164    return context->is_executing;
165  }
166
167  static inline void _CPU_Context_Set_is_executing(
168    Context_Control *context,
169    bool is_executing
170  )
171  {
172    context->is_executing = is_executing;
173  }
174#endif
175
176/*
177 *  FP context save area for the i387 numeric coprocessors.
178 */
179#ifdef __SSE__
180/* All FPU and SSE registers are volatile; hence, as long
181 * as we are within normally executing C code (including
182 * a task switch) there is no need for saving/restoring
183 * any of those registers.
184 * We must save/restore the full FPU/SSE context across
185 * interrupts and exceptions, however:
186 *   -  after ISR execution a _Thread_Dispatch() may happen
187 *      and it is therefore necessary to save the FPU/SSE
188 *      registers to be restored when control is returned
189 *      to the interrupted task.
190 *   -  gcc may implicitly use FPU/SSE instructions in
191 *      an ISR.
192 *
193 * Even though there is no explicit mentioning of the FPU
194 * control word in the SYSV ABI (i386) being non-volatile
195 * we maintain MXCSR and the FPU control-word for each task.
196 */
197typedef struct {
198        uint32_t  mxcsr;
199        uint16_t  fpucw;
200} Context_Control_fp;
201
202#else
203
204typedef struct {
205  uint8_t     fp_save_area[108];    /* context size area for I80387 */
206                                    /*  28 bytes for environment    */
207} Context_Control_fp;
208
209#endif
210
211
212/*
213 *  The following structure defines the set of information saved
214 *  on the current stack by RTEMS upon receipt of execptions.
215 *
216 * idtIndex is either the interrupt number or the trap/exception number.
217 * faultCode is the code pushed by the processor on some exceptions.
218 *
219 * Since the first registers are directly pushed by the CPU they
220 * may not respect 16-byte stack alignment, which is, however,
221 * mandatory for the SSE register area.
222 * Therefore, these registers are stored at an aligned address
223 * and a pointer is stored in the CPU_Exception_frame.
224 * If the executive was compiled without SSE support then
225 * this pointer is NULL.
226 */
227
228struct Context_Control_sse;
229
230typedef struct {
231  struct Context_Control_sse *fp_ctxt;
232  uint32_t    edi;
233  uint32_t    esi;
234  uint32_t    ebp;
235  uint32_t    esp0;
236  uint32_t    ebx;
237  uint32_t    edx;
238  uint32_t    ecx;
239  uint32_t    eax;
240  uint32_t    idtIndex;
241  uint32_t    faultCode;
242  uint32_t    eip;
243  uint32_t    cs;
244  uint32_t    eflags;
245} CPU_Exception_frame;
246
247#ifdef __SSE__
248typedef struct Context_Control_sse {
249  uint16_t  fcw;
250  uint16_t  fsw;
251  uint8_t   ftw;
252  uint8_t   res_1;
253  uint16_t  fop;
254  uint32_t  fpu_ip;
255  uint16_t  cs;
256  uint16_t  res_2;
257  uint32_t  fpu_dp;
258  uint16_t  ds;
259  uint16_t  res_3;
260  uint32_t  mxcsr;
261  uint32_t  mxcsr_mask;
262  struct {
263        uint8_t fpreg[10];
264        uint8_t res_4[ 6];
265  } fp_mmregs[8];
266  uint8_t   xmmregs[8][16];
267  uint8_t   res_5[224];
268} Context_Control_sse
269__attribute__((aligned(16)))
270;
271#endif
272
273typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
274extern cpuExcHandlerType _currentExcHandler;
275extern void rtems_exception_init_mngt(void);
276
277/*
278 * This port does not pass any frame info to the
279 * interrupt handler.
280 */
281
282typedef void CPU_Interrupt_frame;
283
284typedef enum {
285  I386_EXCEPTION_DIVIDE_BY_ZERO      = 0,
286  I386_EXCEPTION_DEBUG               = 1,
287  I386_EXCEPTION_NMI                 = 2,
288  I386_EXCEPTION_BREAKPOINT          = 3,
289  I386_EXCEPTION_OVERFLOW            = 4,
290  I386_EXCEPTION_BOUND               = 5,
291  I386_EXCEPTION_ILLEGAL_INSTR       = 6,
292  I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
293  I386_EXCEPTION_DOUBLE_FAULT        = 8,
294  I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
295  I386_EXCEPTION_INVALID_TSS         = 10,
296  I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
297  I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
298  I386_EXCEPTION_GENERAL_PROT_ERR    = 13,
299  I386_EXCEPTION_PAGE_FAULT          = 14,
300  I386_EXCEPTION_INTEL_RES15         = 15,
301  I386_EXCEPTION_FLOAT_ERROR         = 16,
302  I386_EXCEPTION_ALIGN_CHECK         = 17,
303  I386_EXCEPTION_MACHINE_CHECK       = 18,
304  I386_EXCEPTION_ENTER_RDBG          = 50     /* to enter manually RDBG */
305
306} Intel_symbolic_exception_name;
307
308
309/*
310 *  context size area for floating point
311 *
312 *  NOTE:  This is out of place on the i386 to avoid a forward reference.
313 */
314
315#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
316
317/* variables */
318
319extern Context_Control_fp _CPU_Null_fp_context;
320
321#endif /* ASM */
322
323/* constants */
324
325/*
326 *  This defines the number of levels and the mask used to pick those
327 *  bits out of a thread mode.
328 */
329
330#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
331#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
332
333/*
334 *  extra stack required by the MPCI receive server thread
335 */
336
337#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
338
339/*
340 *  This is defined if the port has a special way to report the ISR nesting
341 *  level.  Most ports maintain the variable _ISR_Nest_level.
342 */
343
344#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
345
346/*
347 *  Minimum size of a thread's stack.
348 */
349
350#define CPU_STACK_MINIMUM_SIZE          4096
351
352#define CPU_SIZEOF_POINTER 4
353
354/*
355 *  i386 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
356 */
357
358#define CPU_ALIGNMENT                    4
359#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
360#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
361
362/*
363 *  On i386 thread stacks require no further alignment after allocation
364 *  from the Workspace. However, since gcc maintains 16-byte alignment
365 *  we try to respect that. If you find an option to let gcc squeeze
366 *  the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still
367 *  doesn't waste much space since this only determines the *initial*
368 *  alignment.
369 */
370
371#define CPU_STACK_ALIGNMENT             16
372
373/* macros */
374
375#ifndef ASM
376/*
377 *  ISR handler macros
378 *
379 *  These macros perform the following functions:
380 *     + initialize the RTEMS vector table
381 *     + disable all maskable CPU interrupts
382 *     + restore previous interrupt level (enable)
383 *     + temporarily restore interrupts (flash)
384 *     + set a particular level
385 */
386
387#if !defined(I386_DISABLE_INLINE_ISR_DISABLE_ENABLE)
388#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
389
390#define _CPU_ISR_Enable( _level )  i386_enable_interrupts( _level )
391
392#define _CPU_ISR_Flash( _level )   i386_flash_interrupts( _level )
393
394#define _CPU_ISR_Set_level( _new_level ) \
395  { \
396    if ( _new_level ) __asm__ volatile ( "cli" ); \
397    else              __asm__ volatile ( "sti" ); \
398  }
399#else
400#define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts()
401#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
402#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level )
403#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level)
404#endif
405
406RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
407{
408  return ( level & EFLAGS_INTR_ENABLE ) != 0;
409}
410
411uint32_t   _CPU_ISR_Get_level( void );
412
413/*  Make sure interrupt stack has space for ISR
414 *  'vector' arg at the top and that it is aligned
415 *  properly.
416 */
417
418#define _CPU_Interrupt_stack_setup( _lo, _hi )  \
419        do {                                        \
420                _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \
421        } while (0)
422
423#endif /* ASM */
424
425/* end of ISR handler macros */
426
427/*
428 *  Context handler macros
429 *
430 *  These macros perform the following functions:
431 *     + initialize a context area
432 *     + restart the current thread
433 *     + calculate the initial pointer into a FP context area
434 *     + initialize an FP context area
435 */
436
437#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
438#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
439
440#ifndef ASM
441
442void _CPU_Context_Initialize(
443  Context_Control *the_context,
444  void *stack_area_begin,
445  size_t stack_area_size,
446  uint32_t new_level,
447  void (*entry_point)( void ),
448  bool is_fp,
449  void *tls_area
450);
451
452#define _CPU_Context_Restart_self( _the_context ) \
453   _CPU_Context_restore( (_the_context) );
454
455#if defined(RTEMS_SMP)
456  uint32_t _CPU_SMP_Initialize( void );
457
458  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
459
460  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
461
462  /* Nothing to do */
463  #define _CPU_SMP_Prepare_start_multitasking() do { } while ( 0 )
464
465  uint32_t _CPU_SMP_Get_current_processor( void );
466
467  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
468
469  static inline void _CPU_SMP_Processor_event_broadcast( void )
470  {
471    __asm__ volatile ( "" : : : "memory" );
472  }
473
474  static inline void _CPU_SMP_Processor_event_receive( void )
475  {
476    __asm__ volatile ( "" : : : "memory" );
477  }
478#endif
479
480#define _CPU_Context_Initialize_fp( _fp_area ) \
481  { \
482    memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \
483  }
484
485/* end of Context handler macros */
486
487/*
488 *  Fatal Error manager macros
489 *
490 *  These macros perform the following functions:
491 *    + disable interrupts and halt the CPU
492 */
493
494extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
495  RTEMS_NO_RETURN;
496
497#endif /* ASM */
498
499/* end of Fatal Error manager macros */
500
501/*
502 *  Bitfield handler macros
503 *
504 *  These macros perform the following functions:
505 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
506 */
507
508#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
509
510#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
511  { \
512    register uint16_t __value_in_register = ( _value ); \
513    uint16_t          __output = 0; \
514    __asm__ volatile ( "bsfw    %0,%1 " \
515                    : "=r" ( __value_in_register ), "=r" ( __output ) \
516                    : "0"  ( __value_in_register ), "1"  ( __output ) \
517    ); \
518    ( _output ) = __output; \
519  }
520
521/* end of Bitfield handler macros */
522
523/*
524 *  Priority handler macros
525 *
526 *  These macros perform the following functions:
527 *    + return a mask with the bit for this major/minor portion of
528 *      of thread priority set.
529 *    + translate the bit number returned by "Bitfield_find_first_bit"
530 *      into an index into the thread ready chain bit maps
531 */
532
533#define _CPU_Priority_Mask( _bit_number ) \
534  ( 1 << (_bit_number) )
535
536#define _CPU_Priority_bits_index( _priority ) \
537  (_priority)
538
539/* functions */
540
541#ifndef ASM
542/*
543 *  _CPU_Initialize
544 *
545 *  This routine performs CPU dependent initialization.
546 */
547
548void _CPU_Initialize(void);
549
550/*
551 *  _CPU_ISR_install_raw_handler
552 *
553 *  This routine installs a "raw" interrupt handler directly into the
554 *  processor's vector table.
555 */
556
557void _CPU_ISR_install_raw_handler(
558  uint32_t    vector,
559  proc_ptr    new_handler,
560  proc_ptr   *old_handler
561);
562
563/*
564 *  _CPU_ISR_install_vector
565 *
566 *  This routine installs an interrupt vector.
567 */
568
569void _CPU_ISR_install_vector(
570  uint32_t    vector,
571  proc_ptr    new_handler,
572  proc_ptr   *old_handler
573);
574
575/*
576 *  _CPU_Thread_Idle_body
577 *
578 *  Use the halt instruction of low power mode of a particular i386 model.
579 */
580
581#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
582
583void *_CPU_Thread_Idle_body( uintptr_t ignored );
584
585#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
586
587/*
588 *  _CPU_Context_switch
589 *
590 *  This routine switches from the run context to the heir context.
591 */
592
593void _CPU_Context_switch(
594  Context_Control  *run,
595  Context_Control  *heir
596);
597
598/*
599 *  _CPU_Context_restore
600 *
601 *  This routine is generally used only to restart self in an
602 *  efficient manner and avoid stack conflicts.
603 */
604
605void _CPU_Context_restore(
606  Context_Control *new_context
607) RTEMS_NO_RETURN;
608
609/*
610 *  _CPU_Context_save_fp
611 *
612 *  This routine saves the floating point context passed to it.
613 */
614
615#ifdef __SSE__
616#define _CPU_Context_save_fp(fp_context_pp) \
617  do {                                      \
618    __asm__ __volatile__(                   \
619      "fstcw %0"                            \
620      :"=m"((*(fp_context_pp))->fpucw)      \
621    );                                      \
622        __asm__ __volatile__(                   \
623      "stmxcsr %0"                          \
624      :"=m"((*(fp_context_pp))->mxcsr)      \
625    );                                      \
626  } while (0)
627#else
628void _CPU_Context_save_fp(
629  Context_Control_fp **fp_context_ptr
630);
631#endif
632
633/*
634 *  _CPU_Context_restore_fp
635 *
636 *  This routine restores the floating point context passed to it.
637 */
638#ifdef __SSE__
639#define _CPU_Context_restore_fp(fp_context_pp) \
640  do {                                         \
641    __asm__ __volatile__(                      \
642      "fldcw %0"                               \
643      ::"m"((*(fp_context_pp))->fpucw)         \
644      :"fpcr"                                  \
645    );                                         \
646    __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr);  \
647  } while (0)
648#else
649void _CPU_Context_restore_fp(
650  Context_Control_fp **fp_context_ptr
651);
652#endif
653
654#ifdef __SSE__
655#define _CPU_Context_Initialization_at_thread_begin() \
656  do {                                                \
657    __asm__ __volatile__(                             \
658      "finit"                                         \
659      :                                               \
660      :                                               \
661      :"st","st(1)","st(2)","st(3)",                  \
662       "st(4)","st(5)","st(6)","st(7)",               \
663       "fpsr","fpcr"                                  \
664    );                                                \
665        if ( _Thread_Executing->fp_context ) {            \
666          _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \
667   }                                                  \
668  } while (0)
669#endif
670
671static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
672{
673  /* TODO */
674}
675
676static inline void _CPU_Context_validate( uintptr_t pattern )
677{
678  while (1) {
679    /* TODO */
680  }
681}
682
683void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
684
685typedef uint32_t CPU_Counter_ticks;
686
687CPU_Counter_ticks _CPU_Counter_read( void );
688
689static inline CPU_Counter_ticks _CPU_Counter_difference(
690  CPU_Counter_ticks second,
691  CPU_Counter_ticks first
692)
693{
694  return second - first;
695}
696
697/** Type that can store a 32-bit integer or a pointer. */
698typedef uintptr_t CPU_Uint32ptr;
699
700#endif /* ASM */
701
702#ifdef __cplusplus
703}
704#endif
705
706#endif
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