[6d6891e] | 1 | /** |
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[d9e0006] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief Intel I386 CPU Dependent Source |
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| 5 | * |
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| 6 | * This include file contains information pertaining to the Intel |
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| 7 | * i386 processor. |
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[6d6891e] | 8 | */ |
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| 9 | |
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| 10 | /* |
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[06dcaf0] | 11 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_CPU_H |
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| 20 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 21 | |
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[a6d48e3] | 22 | #ifndef ASM |
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[af063f6] | 23 | #include <string.h> /* for memcpy */ |
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[a6d48e3] | 24 | #endif |
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[af063f6] | 25 | |
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[7908ba5b] | 26 | #ifdef __cplusplus |
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| 27 | extern "C" { |
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| 28 | #endif |
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| 29 | |
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[a1df2fdc] | 30 | #include <rtems/score/basedefs.h> |
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[89b85e51] | 31 | #include <rtems/score/i386.h> |
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[7908ba5b] | 32 | |
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| 33 | /* conditional compilation parameters */ |
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| 34 | |
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[562cadfa] | 35 | /* |
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| 36 | * Does the CPU follow the simple vectored interrupt model? |
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| 37 | * |
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| 38 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 39 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 40 | * table |
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| 41 | * |
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| 42 | * PowerPC Specific Information: |
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| 43 | * |
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| 44 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
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| 45 | * They do not use the simple vectored interrupt model. |
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| 46 | */ |
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| 47 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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| 48 | |
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[7908ba5b] | 49 | /* |
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| 50 | * i386 has an RTEMS allocated and managed interrupt stack. |
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| 51 | */ |
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| 52 | |
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| 53 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 54 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 55 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 56 | |
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| 57 | /* |
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| 58 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[84c53452] | 59 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 60 | * number (0)? |
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| 61 | */ |
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| 62 | |
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[141e16d] | 63 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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[7908ba5b] | 64 | |
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| 65 | /* |
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| 66 | * Some family members have no FP, some have an FPU such as the i387 |
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| 67 | * for the i386, others have it built in (i486DX, Pentium). |
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| 68 | */ |
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| 69 | |
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[b02f4cc1] | 70 | #ifdef __SSE__ |
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| 71 | #define CPU_HARDWARE_FP TRUE |
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| 72 | #define CPU_SOFTWARE_FP FALSE |
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| 73 | |
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| 74 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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| 75 | #define CPU_IDLE_TASK_IS_FP TRUE |
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| 76 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 77 | #else /* __SSE__ */ |
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| 78 | |
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[7908ba5b] | 79 | #if ( I386_HAS_FPU == 1 ) |
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| 80 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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| 81 | #else |
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| 82 | #define CPU_HARDWARE_FP FALSE |
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| 83 | #endif |
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[17508d02] | 84 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 85 | |
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| 86 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 87 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[965ef82] | 88 | #if defined(RTEMS_SMP) |
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| 89 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 90 | #else |
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| 91 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 92 | #endif |
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[b02f4cc1] | 93 | #endif /* __SSE__ */ |
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[7908ba5b] | 94 | |
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[84e6f15] | 95 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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| 96 | |
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[7908ba5b] | 97 | #define CPU_STACK_GROWS_UP FALSE |
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[a8865f8] | 98 | |
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| 99 | /* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */ |
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| 100 | #define CPU_CACHE_LINE_BYTES 64 |
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| 101 | |
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[7908ba5b] | 102 | #define CPU_STRUCTURE_ALIGNMENT |
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| 103 | |
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| 104 | /* |
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| 105 | * Does this port provide a CPU dependent IDLE task implementation? |
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[84c53452] | 106 | * |
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[7908ba5b] | 107 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 108 | * must be provided and is the default IDLE thread body instead of |
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| 109 | * _CPU_Thread_Idle_body. |
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| 110 | * |
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| 111 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 112 | * not provide one. |
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| 113 | */ |
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[84c53452] | 114 | |
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[fd05a05] | 115 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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[7908ba5b] | 116 | |
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[decff899] | 117 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 118 | |
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[38b59a6] | 119 | #define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 |
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| 120 | #define I386_CONTEXT_CONTROL_ESP_OFFSET 4 |
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| 121 | #define I386_CONTEXT_CONTROL_EBP_OFFSET 8 |
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| 122 | #define I386_CONTEXT_CONTROL_EBX_OFFSET 12 |
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| 123 | #define I386_CONTEXT_CONTROL_ESI_OFFSET 16 |
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| 124 | #define I386_CONTEXT_CONTROL_EDI_OFFSET 20 |
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[7b0c74ff] | 125 | #define I386_CONTEXT_CONTROL_GS_0_OFFSET 24 |
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| 126 | #define I386_CONTEXT_CONTROL_GS_1_OFFSET 28 |
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[38b59a6] | 127 | |
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| 128 | #ifdef RTEMS_SMP |
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[7b0c74ff] | 129 | #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32 |
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[38b59a6] | 130 | #endif |
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| 131 | |
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[7908ba5b] | 132 | /* structures */ |
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| 133 | |
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[a6d48e3] | 134 | #ifndef ASM |
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| 135 | |
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[7908ba5b] | 136 | /* |
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| 137 | * Basic integer context for the i386 family. |
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| 138 | */ |
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| 139 | |
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| 140 | typedef struct { |
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[7b0c74ff] | 141 | uint32_t eflags; /* extended flags register */ |
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| 142 | void *esp; /* extended stack pointer register */ |
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| 143 | void *ebp; /* extended base pointer register */ |
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| 144 | uint32_t ebx; /* extended bx register */ |
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| 145 | uint32_t esi; /* extended source index register */ |
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| 146 | uint32_t edi; /* extended destination index flags register */ |
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| 147 | segment_descriptors gs; /* gs segment descriptor */ |
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[38b59a6] | 148 | #ifdef RTEMS_SMP |
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| 149 | volatile bool is_executing; |
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| 150 | #endif |
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[7908ba5b] | 151 | } Context_Control; |
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| 152 | |
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[0ca6d0d9] | 153 | #define _CPU_Context_Get_SP( _context ) \ |
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| 154 | (_context)->esp |
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| 155 | |
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[38b59a6] | 156 | #ifdef RTEMS_SMP |
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[11b05f1] | 157 | static inline bool _CPU_Context_Get_is_executing( |
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| 158 | const Context_Control *context |
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| 159 | ) |
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| 160 | { |
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| 161 | return context->is_executing; |
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| 162 | } |
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| 163 | |
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| 164 | static inline void _CPU_Context_Set_is_executing( |
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| 165 | Context_Control *context, |
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| 166 | bool is_executing |
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| 167 | ) |
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| 168 | { |
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| 169 | context->is_executing = is_executing; |
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| 170 | } |
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[38b59a6] | 171 | #endif |
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| 172 | |
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[7908ba5b] | 173 | /* |
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| 174 | * FP context save area for the i387 numeric coprocessors. |
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| 175 | */ |
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[b02f4cc1] | 176 | #ifdef __SSE__ |
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| 177 | /* All FPU and SSE registers are volatile; hence, as long |
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| 178 | * as we are within normally executing C code (including |
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| 179 | * a task switch) there is no need for saving/restoring |
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| 180 | * any of those registers. |
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| 181 | * We must save/restore the full FPU/SSE context across |
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| 182 | * interrupts and exceptions, however: |
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| 183 | * - after ISR execution a _Thread_Dispatch() may happen |
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| 184 | * and it is therefore necessary to save the FPU/SSE |
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| 185 | * registers to be restored when control is returned |
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| 186 | * to the interrupted task. |
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| 187 | * - gcc may implicitly use FPU/SSE instructions in |
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| 188 | * an ISR. |
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| 189 | * |
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| 190 | * Even though there is no explicit mentioning of the FPU |
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| 191 | * control word in the SYSV ABI (i386) being non-volatile |
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| 192 | * we maintain MXCSR and the FPU control-word for each task. |
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| 193 | */ |
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| 194 | typedef struct { |
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| 195 | uint32_t mxcsr; |
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| 196 | uint16_t fpucw; |
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| 197 | } Context_Control_fp; |
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| 198 | |
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| 199 | #else |
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[7908ba5b] | 200 | |
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| 201 | typedef struct { |
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[e6aeabd] | 202 | uint8_t fp_save_area[108]; /* context size area for I80387 */ |
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[7908ba5b] | 203 | /* 28 bytes for environment */ |
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| 204 | } Context_Control_fp; |
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| 205 | |
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[b02f4cc1] | 206 | #endif |
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| 207 | |
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[7908ba5b] | 208 | |
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| 209 | /* |
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| 210 | * The following structure defines the set of information saved |
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| 211 | * on the current stack by RTEMS upon receipt of execptions. |
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| 212 | * |
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| 213 | * idtIndex is either the interrupt number or the trap/exception number. |
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| 214 | * faultCode is the code pushed by the processor on some exceptions. |
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[b02f4cc1] | 215 | * |
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| 216 | * Since the first registers are directly pushed by the CPU they |
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| 217 | * may not respect 16-byte stack alignment, which is, however, |
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| 218 | * mandatory for the SSE register area. |
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| 219 | * Therefore, these registers are stored at an aligned address |
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| 220 | * and a pointer is stored in the CPU_Exception_frame. |
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| 221 | * If the executive was compiled without SSE support then |
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| 222 | * this pointer is NULL. |
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[7908ba5b] | 223 | */ |
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| 224 | |
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[b02f4cc1] | 225 | struct Context_Control_sse; |
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| 226 | |
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[7908ba5b] | 227 | typedef struct { |
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[b02f4cc1] | 228 | struct Context_Control_sse *fp_ctxt; |
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[e6aeabd] | 229 | uint32_t edi; |
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| 230 | uint32_t esi; |
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| 231 | uint32_t ebp; |
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| 232 | uint32_t esp0; |
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| 233 | uint32_t ebx; |
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| 234 | uint32_t edx; |
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| 235 | uint32_t ecx; |
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| 236 | uint32_t eax; |
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| 237 | uint32_t idtIndex; |
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| 238 | uint32_t faultCode; |
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| 239 | uint32_t eip; |
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| 240 | uint32_t cs; |
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| 241 | uint32_t eflags; |
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[7908ba5b] | 242 | } CPU_Exception_frame; |
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| 243 | |
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[b02f4cc1] | 244 | #ifdef __SSE__ |
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| 245 | typedef struct Context_Control_sse { |
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| 246 | uint16_t fcw; |
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| 247 | uint16_t fsw; |
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| 248 | uint8_t ftw; |
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| 249 | uint8_t res_1; |
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| 250 | uint16_t fop; |
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| 251 | uint32_t fpu_ip; |
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| 252 | uint16_t cs; |
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| 253 | uint16_t res_2; |
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| 254 | uint32_t fpu_dp; |
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| 255 | uint16_t ds; |
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| 256 | uint16_t res_3; |
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| 257 | uint32_t mxcsr; |
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| 258 | uint32_t mxcsr_mask; |
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| 259 | struct { |
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| 260 | uint8_t fpreg[10]; |
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| 261 | uint8_t res_4[ 6]; |
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| 262 | } fp_mmregs[8]; |
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| 263 | uint8_t xmmregs[8][16]; |
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| 264 | uint8_t res_5[224]; |
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| 265 | } Context_Control_sse |
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| 266 | __attribute__((aligned(16))) |
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| 267 | ; |
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| 268 | #endif |
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| 269 | |
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[7908ba5b] | 270 | typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); |
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| 271 | extern cpuExcHandlerType _currentExcHandler; |
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[1b502424] | 272 | extern void rtems_exception_init_mngt(void); |
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[7908ba5b] | 273 | |
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| 274 | /* |
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[78667e3] | 275 | * This port does not pass any frame info to the |
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| 276 | * interrupt handler. |
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[7908ba5b] | 277 | */ |
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| 278 | |
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[78667e3] | 279 | typedef void CPU_Interrupt_frame; |
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[7908ba5b] | 280 | |
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| 281 | typedef enum { |
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| 282 | I386_EXCEPTION_DIVIDE_BY_ZERO = 0, |
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| 283 | I386_EXCEPTION_DEBUG = 1, |
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| 284 | I386_EXCEPTION_NMI = 2, |
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| 285 | I386_EXCEPTION_BREAKPOINT = 3, |
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| 286 | I386_EXCEPTION_OVERFLOW = 4, |
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| 287 | I386_EXCEPTION_BOUND = 5, |
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| 288 | I386_EXCEPTION_ILLEGAL_INSTR = 6, |
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| 289 | I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, |
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| 290 | I386_EXCEPTION_DOUBLE_FAULT = 8, |
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| 291 | I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, |
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| 292 | I386_EXCEPTION_INVALID_TSS = 10, |
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| 293 | I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, |
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| 294 | I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, |
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| 295 | I386_EXCEPTION_GENERAL_PROT_ERR = 13, |
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| 296 | I386_EXCEPTION_PAGE_FAULT = 14, |
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| 297 | I386_EXCEPTION_INTEL_RES15 = 15, |
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| 298 | I386_EXCEPTION_FLOAT_ERROR = 16, |
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| 299 | I386_EXCEPTION_ALIGN_CHECK = 17, |
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| 300 | I386_EXCEPTION_MACHINE_CHECK = 18, |
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| 301 | I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ |
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| 302 | |
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| 303 | } Intel_symbolic_exception_name; |
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[84c53452] | 304 | |
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[7908ba5b] | 305 | |
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| 306 | /* |
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| 307 | * context size area for floating point |
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| 308 | * |
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| 309 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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| 310 | */ |
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| 311 | |
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| 312 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 313 | |
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| 314 | /* variables */ |
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| 315 | |
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[deaf716] | 316 | extern Context_Control_fp _CPU_Null_fp_context; |
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[7908ba5b] | 317 | |
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[a6d48e3] | 318 | #endif /* ASM */ |
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| 319 | |
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[7908ba5b] | 320 | /* constants */ |
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| 321 | |
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| 322 | /* |
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| 323 | * This defines the number of levels and the mask used to pick those |
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| 324 | * bits out of a thread mode. |
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| 325 | */ |
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| 326 | |
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| 327 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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| 328 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 329 | |
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| 330 | /* |
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| 331 | * extra stack required by the MPCI receive server thread |
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| 332 | */ |
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| 333 | |
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| 334 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 335 | |
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[4db30283] | 336 | /* |
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| 337 | * This is defined if the port has a special way to report the ISR nesting |
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| 338 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 339 | */ |
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| 340 | |
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| 341 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 342 | |
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[7908ba5b] | 343 | /* |
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| 344 | * Minimum size of a thread's stack. |
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| 345 | */ |
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| 346 | |
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[6952f3d] | 347 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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[7908ba5b] | 348 | |
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[f1738ed] | 349 | #define CPU_SIZEOF_POINTER 4 |
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| 350 | |
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[7908ba5b] | 351 | /* |
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| 352 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 353 | */ |
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| 354 | |
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| 355 | #define CPU_ALIGNMENT 4 |
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| 356 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 357 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 358 | |
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| 359 | /* |
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| 360 | * On i386 thread stacks require no further alignment after allocation |
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[a6d48e3] | 361 | * from the Workspace. However, since gcc maintains 16-byte alignment |
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| 362 | * we try to respect that. If you find an option to let gcc squeeze |
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| 363 | * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still |
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| 364 | * doesn't waste much space since this only determines the *initial* |
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| 365 | * alignment. |
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[7908ba5b] | 366 | */ |
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| 367 | |
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[a6d48e3] | 368 | #define CPU_STACK_ALIGNMENT 16 |
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[7908ba5b] | 369 | |
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| 370 | /* macros */ |
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| 371 | |
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[a6d48e3] | 372 | #ifndef ASM |
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[7908ba5b] | 373 | /* |
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| 374 | * ISR handler macros |
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| 375 | * |
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| 376 | * These macros perform the following functions: |
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[effa6593] | 377 | * + initialize the RTEMS vector table |
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[7908ba5b] | 378 | * + disable all maskable CPU interrupts |
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| 379 | * + restore previous interrupt level (enable) |
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| 380 | * + temporarily restore interrupts (flash) |
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| 381 | * + set a particular level |
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| 382 | */ |
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| 383 | |
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[3267f95] | 384 | #if !defined(RTEMS_PARAVIRT) |
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[7908ba5b] | 385 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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| 386 | |
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| 387 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 388 | |
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| 389 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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| 390 | |
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| 391 | #define _CPU_ISR_Set_level( _new_level ) \ |
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| 392 | { \ |
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[c05f6238] | 393 | if ( _new_level ) __asm__ volatile ( "cli" ); \ |
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| 394 | else __asm__ volatile ( "sti" ); \ |
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[7908ba5b] | 395 | } |
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[3267f95] | 396 | #else |
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[dda25b1] | 397 | #define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts() |
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[3267f95] | 398 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 399 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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[dda25b1] | 400 | #define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) |
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[3267f95] | 401 | #endif |
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[7908ba5b] | 402 | |
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[408609f6] | 403 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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| 404 | { |
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| 405 | return ( level & EFLAGS_INTR_ENABLE ) != 0; |
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| 406 | } |
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| 407 | |
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[e6aeabd] | 408 | uint32_t _CPU_ISR_Get_level( void ); |
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[7908ba5b] | 409 | |
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[42e243e] | 410 | /* Make sure interrupt stack has space for ISR |
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[b01d7c7] | 411 | * 'vector' arg at the top and that it is aligned |
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| 412 | * properly. |
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| 413 | */ |
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| 414 | |
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| 415 | #define _CPU_Interrupt_stack_setup( _lo, _hi ) \ |
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| 416 | do { \ |
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| 417 | _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ |
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| 418 | } while (0) |
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| 419 | |
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[a6d48e3] | 420 | #endif /* ASM */ |
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| 421 | |
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[7908ba5b] | 422 | /* end of ISR handler macros */ |
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| 423 | |
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| 424 | /* |
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| 425 | * Context handler macros |
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| 426 | * |
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| 427 | * These macros perform the following functions: |
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| 428 | * + initialize a context area |
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| 429 | * + restart the current thread |
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| 430 | * + calculate the initial pointer into a FP context area |
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| 431 | * + initialize an FP context area |
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| 432 | */ |
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| 433 | |
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| 434 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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| 435 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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| 436 | |
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[a6d48e3] | 437 | #ifndef ASM |
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| 438 | |
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[cb0d9a0] | 439 | void _CPU_Context_Initialize( |
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| 440 | Context_Control *the_context, |
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| 441 | void *stack_area_begin, |
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| 442 | size_t stack_area_size, |
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| 443 | uint32_t new_level, |
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| 444 | void (*entry_point)( void ), |
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| 445 | bool is_fp, |
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| 446 | void *tls_area |
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| 447 | ); |
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[7908ba5b] | 448 | |
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| 449 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 450 | _CPU_Context_restore( (_the_context) ); |
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| 451 | |
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[06dcaf0] | 452 | #if defined(RTEMS_SMP) |
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[53e008b] | 453 | uint32_t _CPU_SMP_Initialize( void ); |
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| 454 | |
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| 455 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 456 | |
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| 457 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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[4627fcd] | 458 | |
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[0a5aa2d] | 459 | /* Nothing to do */ |
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| 460 | #define _CPU_SMP_Prepare_start_multitasking() do { } while ( 0 ) |
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[c34f94f7] | 461 | |
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[47d60134] | 462 | uint32_t _CPU_SMP_Get_current_processor( void ); |
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[39e51758] | 463 | |
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[ca63ae2] | 464 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 465 | |
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[07f6e419] | 466 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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[2f6108f9] | 467 | { |
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| 468 | __asm__ volatile ( "" : : : "memory" ); |
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| 469 | } |
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| 470 | |
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[f7740e97] | 471 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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[2f6108f9] | 472 | { |
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| 473 | __asm__ volatile ( "" : : : "memory" ); |
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| 474 | } |
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[06dcaf0] | 475 | #endif |
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| 476 | |
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[7908ba5b] | 477 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 478 | { \ |
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[af063f6] | 479 | memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ |
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[7908ba5b] | 480 | } |
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| 481 | |
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| 482 | /* end of Context handler macros */ |
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| 483 | |
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| 484 | /* |
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| 485 | * Fatal Error manager macros |
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| 486 | * |
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| 487 | * These macros perform the following functions: |
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| 488 | * + disable interrupts and halt the CPU |
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| 489 | */ |
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| 490 | |
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[505dc61] | 491 | extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) |
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| 492 | RTEMS_NO_RETURN; |
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[7908ba5b] | 493 | |
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[a6d48e3] | 494 | #endif /* ASM */ |
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| 495 | |
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[7908ba5b] | 496 | /* end of Fatal Error manager macros */ |
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| 497 | |
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| 498 | /* |
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| 499 | * Bitfield handler macros |
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| 500 | * |
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| 501 | * These macros perform the following functions: |
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| 502 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 503 | */ |
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| 504 | |
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| 505 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 506 | |
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| 507 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 508 | { \ |
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[3bf9fdb] | 509 | register uint16_t __value_in_register = ( _value ); \ |
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| 510 | uint16_t __output = 0; \ |
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[c05f6238] | 511 | __asm__ volatile ( "bsfw %0,%1 " \ |
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[3bf9fdb] | 512 | : "=r" ( __value_in_register ), "=r" ( __output ) \ |
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| 513 | : "0" ( __value_in_register ), "1" ( __output ) \ |
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[7908ba5b] | 514 | ); \ |
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[3bf9fdb] | 515 | ( _output ) = __output; \ |
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[7908ba5b] | 516 | } |
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| 517 | |
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| 518 | /* end of Bitfield handler macros */ |
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| 519 | |
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| 520 | /* |
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| 521 | * Priority handler macros |
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| 522 | * |
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| 523 | * These macros perform the following functions: |
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| 524 | * + return a mask with the bit for this major/minor portion of |
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| 525 | * of thread priority set. |
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| 526 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 527 | * into an index into the thread ready chain bit maps |
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| 528 | */ |
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| 529 | |
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| 530 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 531 | ( 1 << (_bit_number) ) |
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| 532 | |
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| 533 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 534 | (_priority) |
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| 535 | |
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| 536 | /* functions */ |
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| 537 | |
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[a6d48e3] | 538 | #ifndef ASM |
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[7908ba5b] | 539 | /* |
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| 540 | * _CPU_Initialize |
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| 541 | * |
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| 542 | * This routine performs CPU dependent initialization. |
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| 543 | */ |
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| 544 | |
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[c03e2bc] | 545 | void _CPU_Initialize(void); |
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[7908ba5b] | 546 | |
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| 547 | /* |
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| 548 | * _CPU_ISR_install_raw_handler |
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| 549 | * |
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[84c53452] | 550 | * This routine installs a "raw" interrupt handler directly into the |
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[7908ba5b] | 551 | * processor's vector table. |
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| 552 | */ |
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[84c53452] | 553 | |
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[7908ba5b] | 554 | void _CPU_ISR_install_raw_handler( |
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[e6aeabd] | 555 | uint32_t vector, |
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[7908ba5b] | 556 | proc_ptr new_handler, |
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| 557 | proc_ptr *old_handler |
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| 558 | ); |
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| 559 | |
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| 560 | /* |
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| 561 | * _CPU_ISR_install_vector |
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| 562 | * |
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| 563 | * This routine installs an interrupt vector. |
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| 564 | */ |
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| 565 | |
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| 566 | void _CPU_ISR_install_vector( |
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[e6aeabd] | 567 | uint32_t vector, |
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[7908ba5b] | 568 | proc_ptr new_handler, |
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| 569 | proc_ptr *old_handler |
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| 570 | ); |
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| 571 | |
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| 572 | /* |
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| 573 | * _CPU_Thread_Idle_body |
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| 574 | * |
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| 575 | * Use the halt instruction of low power mode of a particular i386 model. |
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| 576 | */ |
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| 577 | |
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| 578 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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| 579 | |
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[cca8379] | 580 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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[7908ba5b] | 581 | |
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| 582 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
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| 583 | |
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| 584 | /* |
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| 585 | * _CPU_Context_switch |
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| 586 | * |
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| 587 | * This routine switches from the run context to the heir context. |
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| 588 | */ |
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| 589 | |
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| 590 | void _CPU_Context_switch( |
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| 591 | Context_Control *run, |
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| 592 | Context_Control *heir |
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| 593 | ); |
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| 594 | |
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| 595 | /* |
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| 596 | * _CPU_Context_restore |
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| 597 | * |
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| 598 | * This routine is generally used only to restart self in an |
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| 599 | * efficient manner and avoid stack conflicts. |
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| 600 | */ |
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| 601 | |
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| 602 | void _CPU_Context_restore( |
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| 603 | Context_Control *new_context |
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[143696a] | 604 | ) RTEMS_NO_RETURN; |
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[7908ba5b] | 605 | |
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| 606 | /* |
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| 607 | * _CPU_Context_save_fp |
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| 608 | * |
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| 609 | * This routine saves the floating point context passed to it. |
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| 610 | */ |
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| 611 | |
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[b02f4cc1] | 612 | #ifdef __SSE__ |
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| 613 | #define _CPU_Context_save_fp(fp_context_pp) \ |
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| 614 | do { \ |
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| 615 | __asm__ __volatile__( \ |
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| 616 | "fstcw %0" \ |
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| 617 | :"=m"((*(fp_context_pp))->fpucw) \ |
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| 618 | ); \ |
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| 619 | __asm__ __volatile__( \ |
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| 620 | "stmxcsr %0" \ |
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| 621 | :"=m"((*(fp_context_pp))->mxcsr) \ |
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| 622 | ); \ |
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| 623 | } while (0) |
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| 624 | #else |
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[7908ba5b] | 625 | void _CPU_Context_save_fp( |
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[3c86f88] | 626 | Context_Control_fp **fp_context_ptr |
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[7908ba5b] | 627 | ); |
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[b02f4cc1] | 628 | #endif |
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[7908ba5b] | 629 | |
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| 630 | /* |
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| 631 | * _CPU_Context_restore_fp |
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| 632 | * |
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| 633 | * This routine restores the floating point context passed to it. |
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| 634 | */ |
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[b02f4cc1] | 635 | #ifdef __SSE__ |
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| 636 | #define _CPU_Context_restore_fp(fp_context_pp) \ |
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| 637 | do { \ |
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| 638 | __asm__ __volatile__( \ |
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| 639 | "fldcw %0" \ |
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| 640 | ::"m"((*(fp_context_pp))->fpucw) \ |
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| 641 | :"fpcr" \ |
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| 642 | ); \ |
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| 643 | __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ |
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| 644 | } while (0) |
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| 645 | #else |
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[7908ba5b] | 646 | void _CPU_Context_restore_fp( |
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[3c86f88] | 647 | Context_Control_fp **fp_context_ptr |
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[7908ba5b] | 648 | ); |
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[b02f4cc1] | 649 | #endif |
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| 650 | |
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| 651 | #ifdef __SSE__ |
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| 652 | #define _CPU_Context_Initialization_at_thread_begin() \ |
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| 653 | do { \ |
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| 654 | __asm__ __volatile__( \ |
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| 655 | "finit" \ |
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| 656 | : \ |
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| 657 | : \ |
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| 658 | :"st","st(1)","st(2)","st(3)", \ |
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| 659 | "st(4)","st(5)","st(6)","st(7)", \ |
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| 660 | "fpsr","fpcr" \ |
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| 661 | ); \ |
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| 662 | if ( _Thread_Executing->fp_context ) { \ |
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| 663 | _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ |
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| 664 | } \ |
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| 665 | } while (0) |
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| 666 | #endif |
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[7908ba5b] | 667 | |
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[39993d6] | 668 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
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| 669 | { |
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| 670 | /* TODO */ |
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| 671 | } |
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| 672 | |
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| 673 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
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| 674 | { |
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| 675 | while (1) { |
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| 676 | /* TODO */ |
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| 677 | } |
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| 678 | } |
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| 679 | |
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[815994f] | 680 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 681 | |
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[24bf11e] | 682 | typedef uint32_t CPU_Counter_ticks; |
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| 683 | |
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| 684 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 685 | |
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| 686 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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| 687 | CPU_Counter_ticks second, |
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| 688 | CPU_Counter_ticks first |
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| 689 | ) |
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| 690 | { |
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| 691 | return second - first; |
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| 692 | } |
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| 693 | |
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[a1df2fdc] | 694 | /** Type that can store a 32-bit integer or a pointer. */ |
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| 695 | typedef uintptr_t CPU_Uint32ptr; |
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| 696 | |
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[a6d48e3] | 697 | #endif /* ASM */ |
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| 698 | |
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[7908ba5b] | 699 | #ifdef __cplusplus |
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| 700 | } |
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| 701 | #endif |
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| 702 | |
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| 703 | #endif |
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