[6d6891e] | 1 | /** |
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[d9e0006] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief Intel I386 CPU Dependent Source |
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| 5 | * |
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| 6 | * This include file contains information pertaining to the Intel |
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| 7 | * i386 processor. |
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[6d6891e] | 8 | */ |
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| 9 | |
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| 10 | /* |
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[06dcaf0] | 11 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_CPU_H |
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| 20 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 21 | |
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[a6d48e3] | 22 | #ifndef ASM |
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[af063f6] | 23 | #include <string.h> /* for memcpy */ |
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[a6d48e3] | 24 | #endif |
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[af063f6] | 25 | |
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[7908ba5b] | 26 | #ifdef __cplusplus |
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| 27 | extern "C" { |
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| 28 | #endif |
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| 29 | |
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[a1df2fdc] | 30 | #include <rtems/score/basedefs.h> |
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[7c39cab] | 31 | #if defined(RTEMS_PARAVIRT) |
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| 32 | #include <rtems/score/paravirt.h> |
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| 33 | #endif |
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[89b85e51] | 34 | #include <rtems/score/i386.h> |
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[d670ef9] | 35 | |
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| 36 | /** |
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[4c20da4b] | 37 | * @defgroup RTEMSScoreCPUi386 i386 Specific Support |
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[d670ef9] | 38 | * |
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| 39 | * @ingroup RTEMSScoreCPUi386 |
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| 40 | * |
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| 41 | * @brief i386 specific support. |
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| 42 | */ |
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| 43 | /**@{**/ |
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[7908ba5b] | 44 | |
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| 45 | /* conditional compilation parameters */ |
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| 46 | |
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[562cadfa] | 47 | /* |
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| 48 | * Does the CPU follow the simple vectored interrupt model? |
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| 49 | * |
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| 50 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 51 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 52 | * table |
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| 53 | * |
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| 54 | * PowerPC Specific Information: |
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| 55 | * |
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| 56 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
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| 57 | * They do not use the simple vectored interrupt model. |
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| 58 | */ |
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| 59 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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| 60 | |
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[7908ba5b] | 61 | /* |
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| 62 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[84c53452] | 63 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 64 | * number (0)? |
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| 65 | */ |
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| 66 | |
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[141e16d] | 67 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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[7908ba5b] | 68 | |
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| 69 | /* |
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| 70 | * Some family members have no FP, some have an FPU such as the i387 |
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| 71 | * for the i386, others have it built in (i486DX, Pentium). |
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| 72 | */ |
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| 73 | |
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[b02f4cc1] | 74 | #ifdef __SSE__ |
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| 75 | #define CPU_HARDWARE_FP TRUE |
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| 76 | #define CPU_SOFTWARE_FP FALSE |
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| 77 | |
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| 78 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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| 79 | #define CPU_IDLE_TASK_IS_FP TRUE |
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| 80 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 81 | #else /* __SSE__ */ |
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| 82 | |
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[7908ba5b] | 83 | #if ( I386_HAS_FPU == 1 ) |
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| 84 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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| 85 | #else |
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| 86 | #define CPU_HARDWARE_FP FALSE |
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| 87 | #endif |
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[17508d02] | 88 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 89 | |
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| 90 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 91 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[965ef82] | 92 | #if defined(RTEMS_SMP) |
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| 93 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 94 | #else |
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| 95 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 96 | #endif |
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[b02f4cc1] | 97 | #endif /* __SSE__ */ |
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[7908ba5b] | 98 | |
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[84e6f15] | 99 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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| 100 | |
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[7908ba5b] | 101 | #define CPU_STACK_GROWS_UP FALSE |
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[a8865f8] | 102 | |
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| 103 | /* FIXME: The Pentium 4 used 128 bytes, it this processor still relevant? */ |
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| 104 | #define CPU_CACHE_LINE_BYTES 64 |
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| 105 | |
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[7908ba5b] | 106 | #define CPU_STRUCTURE_ALIGNMENT |
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| 107 | |
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[decff899] | 108 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 109 | |
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[38b59a6] | 110 | #define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 |
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| 111 | #define I386_CONTEXT_CONTROL_ESP_OFFSET 4 |
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| 112 | #define I386_CONTEXT_CONTROL_EBP_OFFSET 8 |
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| 113 | #define I386_CONTEXT_CONTROL_EBX_OFFSET 12 |
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| 114 | #define I386_CONTEXT_CONTROL_ESI_OFFSET 16 |
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| 115 | #define I386_CONTEXT_CONTROL_EDI_OFFSET 20 |
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[7b0c74ff] | 116 | #define I386_CONTEXT_CONTROL_GS_0_OFFSET 24 |
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| 117 | #define I386_CONTEXT_CONTROL_GS_1_OFFSET 28 |
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[8937f12] | 118 | #define I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32 |
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[38b59a6] | 119 | |
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| 120 | #ifdef RTEMS_SMP |
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[8937f12] | 121 | #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 36 |
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[38b59a6] | 122 | #endif |
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| 123 | |
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[7908ba5b] | 124 | /* structures */ |
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| 125 | |
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[a6d48e3] | 126 | #ifndef ASM |
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| 127 | |
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[7908ba5b] | 128 | /* |
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| 129 | * Basic integer context for the i386 family. |
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| 130 | */ |
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| 131 | |
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| 132 | typedef struct { |
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[7b0c74ff] | 133 | uint32_t eflags; /* extended flags register */ |
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| 134 | void *esp; /* extended stack pointer register */ |
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| 135 | void *ebp; /* extended base pointer register */ |
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| 136 | uint32_t ebx; /* extended bx register */ |
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| 137 | uint32_t esi; /* extended source index register */ |
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| 138 | uint32_t edi; /* extended destination index flags register */ |
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| 139 | segment_descriptors gs; /* gs segment descriptor */ |
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[8937f12] | 140 | uint32_t isr_dispatch_disable; |
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[38b59a6] | 141 | #ifdef RTEMS_SMP |
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| 142 | volatile bool is_executing; |
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| 143 | #endif |
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[7908ba5b] | 144 | } Context_Control; |
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| 145 | |
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[0ca6d0d9] | 146 | #define _CPU_Context_Get_SP( _context ) \ |
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| 147 | (_context)->esp |
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| 148 | |
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[38b59a6] | 149 | #ifdef RTEMS_SMP |
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[11b05f1] | 150 | static inline bool _CPU_Context_Get_is_executing( |
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| 151 | const Context_Control *context |
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| 152 | ) |
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| 153 | { |
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| 154 | return context->is_executing; |
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| 155 | } |
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| 156 | |
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| 157 | static inline void _CPU_Context_Set_is_executing( |
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| 158 | Context_Control *context, |
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| 159 | bool is_executing |
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| 160 | ) |
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| 161 | { |
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| 162 | context->is_executing = is_executing; |
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| 163 | } |
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[38b59a6] | 164 | #endif |
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| 165 | |
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[7908ba5b] | 166 | /* |
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| 167 | * FP context save area for the i387 numeric coprocessors. |
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| 168 | */ |
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[b02f4cc1] | 169 | #ifdef __SSE__ |
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| 170 | /* All FPU and SSE registers are volatile; hence, as long |
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| 171 | * as we are within normally executing C code (including |
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| 172 | * a task switch) there is no need for saving/restoring |
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| 173 | * any of those registers. |
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| 174 | * We must save/restore the full FPU/SSE context across |
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| 175 | * interrupts and exceptions, however: |
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| 176 | * - after ISR execution a _Thread_Dispatch() may happen |
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| 177 | * and it is therefore necessary to save the FPU/SSE |
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| 178 | * registers to be restored when control is returned |
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| 179 | * to the interrupted task. |
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| 180 | * - gcc may implicitly use FPU/SSE instructions in |
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| 181 | * an ISR. |
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| 182 | * |
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| 183 | * Even though there is no explicit mentioning of the FPU |
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| 184 | * control word in the SYSV ABI (i386) being non-volatile |
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| 185 | * we maintain MXCSR and the FPU control-word for each task. |
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| 186 | */ |
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| 187 | typedef struct { |
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| 188 | uint32_t mxcsr; |
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| 189 | uint16_t fpucw; |
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| 190 | } Context_Control_fp; |
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| 191 | |
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| 192 | #else |
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[7908ba5b] | 193 | |
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| 194 | typedef struct { |
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[e6aeabd] | 195 | uint8_t fp_save_area[108]; /* context size area for I80387 */ |
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[7908ba5b] | 196 | /* 28 bytes for environment */ |
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| 197 | } Context_Control_fp; |
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| 198 | |
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[b02f4cc1] | 199 | #endif |
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| 200 | |
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[7908ba5b] | 201 | |
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| 202 | /* |
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| 203 | * The following structure defines the set of information saved |
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| 204 | * on the current stack by RTEMS upon receipt of execptions. |
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| 205 | * |
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| 206 | * idtIndex is either the interrupt number or the trap/exception number. |
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| 207 | * faultCode is the code pushed by the processor on some exceptions. |
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[b02f4cc1] | 208 | * |
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| 209 | * Since the first registers are directly pushed by the CPU they |
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| 210 | * may not respect 16-byte stack alignment, which is, however, |
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| 211 | * mandatory for the SSE register area. |
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| 212 | * Therefore, these registers are stored at an aligned address |
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| 213 | * and a pointer is stored in the CPU_Exception_frame. |
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| 214 | * If the executive was compiled without SSE support then |
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| 215 | * this pointer is NULL. |
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[7908ba5b] | 216 | */ |
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| 217 | |
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[b02f4cc1] | 218 | struct Context_Control_sse; |
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| 219 | |
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[7908ba5b] | 220 | typedef struct { |
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[b02f4cc1] | 221 | struct Context_Control_sse *fp_ctxt; |
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[e6aeabd] | 222 | uint32_t edi; |
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| 223 | uint32_t esi; |
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| 224 | uint32_t ebp; |
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| 225 | uint32_t esp0; |
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| 226 | uint32_t ebx; |
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| 227 | uint32_t edx; |
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| 228 | uint32_t ecx; |
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| 229 | uint32_t eax; |
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| 230 | uint32_t idtIndex; |
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| 231 | uint32_t faultCode; |
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| 232 | uint32_t eip; |
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| 233 | uint32_t cs; |
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| 234 | uint32_t eflags; |
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[7908ba5b] | 235 | } CPU_Exception_frame; |
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| 236 | |
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[b02f4cc1] | 237 | #ifdef __SSE__ |
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| 238 | typedef struct Context_Control_sse { |
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| 239 | uint16_t fcw; |
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| 240 | uint16_t fsw; |
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| 241 | uint8_t ftw; |
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| 242 | uint8_t res_1; |
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| 243 | uint16_t fop; |
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| 244 | uint32_t fpu_ip; |
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| 245 | uint16_t cs; |
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| 246 | uint16_t res_2; |
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| 247 | uint32_t fpu_dp; |
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| 248 | uint16_t ds; |
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| 249 | uint16_t res_3; |
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| 250 | uint32_t mxcsr; |
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| 251 | uint32_t mxcsr_mask; |
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| 252 | struct { |
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| 253 | uint8_t fpreg[10]; |
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| 254 | uint8_t res_4[ 6]; |
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| 255 | } fp_mmregs[8]; |
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| 256 | uint8_t xmmregs[8][16]; |
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| 257 | uint8_t res_5[224]; |
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| 258 | } Context_Control_sse |
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| 259 | __attribute__((aligned(16))) |
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| 260 | ; |
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| 261 | #endif |
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| 262 | |
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[7908ba5b] | 263 | typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); |
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| 264 | extern cpuExcHandlerType _currentExcHandler; |
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[1b502424] | 265 | extern void rtems_exception_init_mngt(void); |
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[7908ba5b] | 266 | |
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[e9fb3133] | 267 | #ifdef RTEMS_SMP |
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| 268 | /* Throw compile-time error to indicate incomplete support */ |
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| 269 | #error "i386 targets do not support SMP.\ |
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| 270 | See: https://devel.rtems.org/ticket/3335" |
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| 271 | |
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| 272 | /* |
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| 273 | * This size must match the size of the CPU_Interrupt_frame, which must be |
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| 274 | * used in the SMP context switch code, which is incomplete at the moment. |
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| 275 | */ |
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| 276 | #define CPU_INTERRUPT_FRAME_SIZE 4 |
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| 277 | #endif |
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| 278 | |
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[7908ba5b] | 279 | /* |
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[78667e3] | 280 | * This port does not pass any frame info to the |
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| 281 | * interrupt handler. |
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[7908ba5b] | 282 | */ |
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| 283 | |
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[e9fb3133] | 284 | typedef struct { |
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| 285 | uint32_t todo_replace_with_apt_registers; |
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| 286 | } CPU_Interrupt_frame; |
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[7908ba5b] | 287 | |
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| 288 | typedef enum { |
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| 289 | I386_EXCEPTION_DIVIDE_BY_ZERO = 0, |
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| 290 | I386_EXCEPTION_DEBUG = 1, |
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| 291 | I386_EXCEPTION_NMI = 2, |
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| 292 | I386_EXCEPTION_BREAKPOINT = 3, |
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| 293 | I386_EXCEPTION_OVERFLOW = 4, |
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| 294 | I386_EXCEPTION_BOUND = 5, |
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| 295 | I386_EXCEPTION_ILLEGAL_INSTR = 6, |
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| 296 | I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, |
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| 297 | I386_EXCEPTION_DOUBLE_FAULT = 8, |
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| 298 | I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, |
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| 299 | I386_EXCEPTION_INVALID_TSS = 10, |
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| 300 | I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, |
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| 301 | I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, |
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| 302 | I386_EXCEPTION_GENERAL_PROT_ERR = 13, |
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| 303 | I386_EXCEPTION_PAGE_FAULT = 14, |
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| 304 | I386_EXCEPTION_INTEL_RES15 = 15, |
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| 305 | I386_EXCEPTION_FLOAT_ERROR = 16, |
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| 306 | I386_EXCEPTION_ALIGN_CHECK = 17, |
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| 307 | I386_EXCEPTION_MACHINE_CHECK = 18, |
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| 308 | I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ |
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| 309 | |
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| 310 | } Intel_symbolic_exception_name; |
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[84c53452] | 311 | |
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[7908ba5b] | 312 | |
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| 313 | /* |
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| 314 | * context size area for floating point |
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| 315 | * |
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| 316 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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| 317 | */ |
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| 318 | |
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| 319 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 320 | |
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| 321 | /* variables */ |
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| 322 | |
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[deaf716] | 323 | extern Context_Control_fp _CPU_Null_fp_context; |
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[7908ba5b] | 324 | |
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[a6d48e3] | 325 | #endif /* ASM */ |
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| 326 | |
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[7908ba5b] | 327 | /* constants */ |
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| 328 | |
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| 329 | /* |
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| 330 | * This defines the number of levels and the mask used to pick those |
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| 331 | * bits out of a thread mode. |
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| 332 | */ |
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| 333 | |
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| 334 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 335 | |
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| 336 | /* |
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| 337 | * extra stack required by the MPCI receive server thread |
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| 338 | */ |
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| 339 | |
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| 340 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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| 341 | |
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[4db30283] | 342 | /* |
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| 343 | * This is defined if the port has a special way to report the ISR nesting |
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| 344 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 345 | */ |
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| 346 | |
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| 347 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 348 | |
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[7908ba5b] | 349 | /* |
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| 350 | * Minimum size of a thread's stack. |
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| 351 | */ |
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| 352 | |
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[6952f3d] | 353 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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[7908ba5b] | 354 | |
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[f1738ed] | 355 | #define CPU_SIZEOF_POINTER 4 |
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| 356 | |
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[7908ba5b] | 357 | /* |
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| 358 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 359 | */ |
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| 360 | |
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| 361 | #define CPU_ALIGNMENT 4 |
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| 362 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 363 | |
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| 364 | /* |
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| 365 | * On i386 thread stacks require no further alignment after allocation |
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[a6d48e3] | 366 | * from the Workspace. However, since gcc maintains 16-byte alignment |
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| 367 | * we try to respect that. If you find an option to let gcc squeeze |
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| 368 | * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still |
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| 369 | * doesn't waste much space since this only determines the *initial* |
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| 370 | * alignment. |
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[7908ba5b] | 371 | */ |
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| 372 | |
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[a6d48e3] | 373 | #define CPU_STACK_ALIGNMENT 16 |
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[7908ba5b] | 374 | |
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[c8df844] | 375 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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| 376 | |
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[7908ba5b] | 377 | /* macros */ |
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| 378 | |
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[a6d48e3] | 379 | #ifndef ASM |
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[7908ba5b] | 380 | /* |
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| 381 | * ISR handler macros |
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| 382 | * |
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| 383 | * These macros perform the following functions: |
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[effa6593] | 384 | * + initialize the RTEMS vector table |
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[7908ba5b] | 385 | * + disable all maskable CPU interrupts |
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| 386 | * + restore previous interrupt level (enable) |
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| 387 | * + temporarily restore interrupts (flash) |
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| 388 | * + set a particular level |
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| 389 | */ |
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| 390 | |
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[7c39cab] | 391 | #if !defined(I386_DISABLE_INLINE_ISR_DISABLE_ENABLE) |
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[7908ba5b] | 392 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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| 393 | |
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| 394 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 395 | |
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| 396 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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| 397 | |
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| 398 | #define _CPU_ISR_Set_level( _new_level ) \ |
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| 399 | { \ |
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[c05f6238] | 400 | if ( _new_level ) __asm__ volatile ( "cli" ); \ |
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| 401 | else __asm__ volatile ( "sti" ); \ |
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[7908ba5b] | 402 | } |
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[3267f95] | 403 | #else |
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[dda25b1] | 404 | #define _CPU_ISR_Disable( _level ) _level = i386_disable_interrupts() |
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[3267f95] | 405 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 406 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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[dda25b1] | 407 | #define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level) |
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[3267f95] | 408 | #endif |
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[7908ba5b] | 409 | |
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[408609f6] | 410 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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| 411 | { |
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| 412 | return ( level & EFLAGS_INTR_ENABLE ) != 0; |
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| 413 | } |
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| 414 | |
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[e6aeabd] | 415 | uint32_t _CPU_ISR_Get_level( void ); |
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[7908ba5b] | 416 | |
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[42e243e] | 417 | /* Make sure interrupt stack has space for ISR |
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[b01d7c7] | 418 | * 'vector' arg at the top and that it is aligned |
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| 419 | * properly. |
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| 420 | */ |
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| 421 | |
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| 422 | #define _CPU_Interrupt_stack_setup( _lo, _hi ) \ |
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| 423 | do { \ |
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| 424 | _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ |
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| 425 | } while (0) |
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| 426 | |
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[a6d48e3] | 427 | #endif /* ASM */ |
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| 428 | |
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[7908ba5b] | 429 | /* end of ISR handler macros */ |
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| 430 | |
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| 431 | /* |
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| 432 | * Context handler macros |
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| 433 | * |
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| 434 | * These macros perform the following functions: |
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| 435 | * + initialize a context area |
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| 436 | * + restart the current thread |
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| 437 | * + calculate the initial pointer into a FP context area |
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| 438 | * + initialize an FP context area |
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| 439 | */ |
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| 440 | |
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| 441 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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| 442 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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| 443 | |
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[a6d48e3] | 444 | #ifndef ASM |
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| 445 | |
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[cb0d9a0] | 446 | void _CPU_Context_Initialize( |
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| 447 | Context_Control *the_context, |
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| 448 | void *stack_area_begin, |
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| 449 | size_t stack_area_size, |
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| 450 | uint32_t new_level, |
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| 451 | void (*entry_point)( void ), |
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| 452 | bool is_fp, |
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| 453 | void *tls_area |
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| 454 | ); |
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[7908ba5b] | 455 | |
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| 456 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 457 | _CPU_Context_restore( (_the_context) ); |
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| 458 | |
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[06dcaf0] | 459 | #if defined(RTEMS_SMP) |
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[53e008b] | 460 | uint32_t _CPU_SMP_Initialize( void ); |
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| 461 | |
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| 462 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 463 | |
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| 464 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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[4627fcd] | 465 | |
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[efa0039e] | 466 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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[c34f94f7] | 467 | |
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[47d60134] | 468 | uint32_t _CPU_SMP_Get_current_processor( void ); |
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[39e51758] | 469 | |
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[ca63ae2] | 470 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 471 | |
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[07f6e419] | 472 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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[2f6108f9] | 473 | { |
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| 474 | __asm__ volatile ( "" : : : "memory" ); |
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| 475 | } |
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| 476 | |
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[f7740e97] | 477 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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[2f6108f9] | 478 | { |
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| 479 | __asm__ volatile ( "" : : : "memory" ); |
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| 480 | } |
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[06dcaf0] | 481 | #endif |
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| 482 | |
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[7908ba5b] | 483 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 484 | { \ |
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[af063f6] | 485 | memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ |
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[7908ba5b] | 486 | } |
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| 487 | |
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| 488 | /* end of Context handler macros */ |
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| 489 | |
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| 490 | /* |
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| 491 | * Fatal Error manager macros |
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| 492 | * |
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| 493 | * These macros perform the following functions: |
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| 494 | * + disable interrupts and halt the CPU |
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| 495 | */ |
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| 496 | |
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[505dc61] | 497 | extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) |
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| 498 | RTEMS_NO_RETURN; |
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[7908ba5b] | 499 | |
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[a6d48e3] | 500 | #endif /* ASM */ |
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| 501 | |
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[7908ba5b] | 502 | /* end of Fatal Error manager macros */ |
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| 503 | |
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| 504 | /* |
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| 505 | * Bitfield handler macros |
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| 506 | * |
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| 507 | * These macros perform the following functions: |
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| 508 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 509 | */ |
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| 510 | |
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| 511 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 512 | |
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| 513 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 514 | { \ |
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[f35c3be9] | 515 | uint16_t __value_in_register = ( _value ); \ |
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| 516 | uint16_t __output = 0; \ |
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[c05f6238] | 517 | __asm__ volatile ( "bsfw %0,%1 " \ |
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[3bf9fdb] | 518 | : "=r" ( __value_in_register ), "=r" ( __output ) \ |
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| 519 | : "0" ( __value_in_register ), "1" ( __output ) \ |
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[7908ba5b] | 520 | ); \ |
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[3bf9fdb] | 521 | ( _output ) = __output; \ |
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[7908ba5b] | 522 | } |
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| 523 | |
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| 524 | /* end of Bitfield handler macros */ |
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| 525 | |
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| 526 | /* |
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| 527 | * Priority handler macros |
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| 528 | * |
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| 529 | * These macros perform the following functions: |
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| 530 | * + return a mask with the bit for this major/minor portion of |
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| 531 | * of thread priority set. |
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| 532 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 533 | * into an index into the thread ready chain bit maps |
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| 534 | */ |
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| 535 | |
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| 536 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 537 | ( 1 << (_bit_number) ) |
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| 538 | |
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| 539 | #define _CPU_Priority_bits_index( _priority ) \ |
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| 540 | (_priority) |
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| 541 | |
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| 542 | /* functions */ |
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| 543 | |
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[a6d48e3] | 544 | #ifndef ASM |
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[7908ba5b] | 545 | /* |
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| 546 | * _CPU_Initialize |
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| 547 | * |
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| 548 | * This routine performs CPU dependent initialization. |
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| 549 | */ |
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| 550 | |
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[c03e2bc] | 551 | void _CPU_Initialize(void); |
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[7908ba5b] | 552 | |
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[3c6a6e8] | 553 | typedef void ( *CPU_ISR_handler )( void ); |
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[7908ba5b] | 554 | |
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| 555 | void _CPU_ISR_install_vector( |
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[3c6a6e8] | 556 | uint32_t vector, |
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| 557 | CPU_ISR_handler new_handler, |
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| 558 | CPU_ISR_handler *old_handler |
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[7908ba5b] | 559 | ); |
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| 560 | |
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[cca8379] | 561 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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[7908ba5b] | 562 | |
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| 563 | /* |
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| 564 | * _CPU_Context_switch |
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| 565 | * |
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| 566 | * This routine switches from the run context to the heir context. |
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| 567 | */ |
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| 568 | |
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| 569 | void _CPU_Context_switch( |
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| 570 | Context_Control *run, |
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| 571 | Context_Control *heir |
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| 572 | ); |
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| 573 | |
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| 574 | /* |
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| 575 | * _CPU_Context_restore |
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| 576 | * |
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| 577 | * This routine is generally used only to restart self in an |
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| 578 | * efficient manner and avoid stack conflicts. |
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| 579 | */ |
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| 580 | |
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| 581 | void _CPU_Context_restore( |
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| 582 | Context_Control *new_context |
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[143696a] | 583 | ) RTEMS_NO_RETURN; |
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[7908ba5b] | 584 | |
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| 585 | /* |
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| 586 | * _CPU_Context_save_fp |
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| 587 | * |
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| 588 | * This routine saves the floating point context passed to it. |
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| 589 | */ |
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| 590 | |
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[b02f4cc1] | 591 | #ifdef __SSE__ |
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| 592 | #define _CPU_Context_save_fp(fp_context_pp) \ |
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| 593 | do { \ |
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| 594 | __asm__ __volatile__( \ |
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| 595 | "fstcw %0" \ |
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| 596 | :"=m"((*(fp_context_pp))->fpucw) \ |
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| 597 | ); \ |
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| 598 | __asm__ __volatile__( \ |
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| 599 | "stmxcsr %0" \ |
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| 600 | :"=m"((*(fp_context_pp))->mxcsr) \ |
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| 601 | ); \ |
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| 602 | } while (0) |
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| 603 | #else |
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[7908ba5b] | 604 | void _CPU_Context_save_fp( |
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[3c86f88] | 605 | Context_Control_fp **fp_context_ptr |
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[7908ba5b] | 606 | ); |
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[b02f4cc1] | 607 | #endif |
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[7908ba5b] | 608 | |
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| 609 | /* |
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| 610 | * _CPU_Context_restore_fp |
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| 611 | * |
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| 612 | * This routine restores the floating point context passed to it. |
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| 613 | */ |
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[b02f4cc1] | 614 | #ifdef __SSE__ |
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| 615 | #define _CPU_Context_restore_fp(fp_context_pp) \ |
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| 616 | do { \ |
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| 617 | __asm__ __volatile__( \ |
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| 618 | "fldcw %0" \ |
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| 619 | ::"m"((*(fp_context_pp))->fpucw) \ |
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| 620 | :"fpcr" \ |
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| 621 | ); \ |
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| 622 | __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ |
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| 623 | } while (0) |
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| 624 | #else |
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[7908ba5b] | 625 | void _CPU_Context_restore_fp( |
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[3c86f88] | 626 | Context_Control_fp **fp_context_ptr |
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[7908ba5b] | 627 | ); |
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[b02f4cc1] | 628 | #endif |
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| 629 | |
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| 630 | #ifdef __SSE__ |
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| 631 | #define _CPU_Context_Initialization_at_thread_begin() \ |
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| 632 | do { \ |
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| 633 | __asm__ __volatile__( \ |
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| 634 | "finit" \ |
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| 635 | : \ |
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| 636 | : \ |
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| 637 | :"st","st(1)","st(2)","st(3)", \ |
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| 638 | "st(4)","st(5)","st(6)","st(7)", \ |
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| 639 | "fpsr","fpcr" \ |
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| 640 | ); \ |
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| 641 | if ( _Thread_Executing->fp_context ) { \ |
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| 642 | _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ |
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| 643 | } \ |
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| 644 | } while (0) |
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| 645 | #endif |
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[7908ba5b] | 646 | |
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[815994f] | 647 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 648 | |
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[24bf11e] | 649 | typedef uint32_t CPU_Counter_ticks; |
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| 650 | |
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[65f868c] | 651 | uint32_t _CPU_Counter_frequency( void ); |
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| 652 | |
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[24bf11e] | 653 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 654 | |
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| 655 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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| 656 | CPU_Counter_ticks second, |
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| 657 | CPU_Counter_ticks first |
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| 658 | ) |
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| 659 | { |
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| 660 | return second - first; |
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| 661 | } |
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| 662 | |
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[d670ef9] | 663 | /**@}**/ |
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| 664 | |
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[a1df2fdc] | 665 | /** Type that can store a 32-bit integer or a pointer. */ |
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| 666 | typedef uintptr_t CPU_Uint32ptr; |
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| 667 | |
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[a6d48e3] | 668 | #endif /* ASM */ |
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| 669 | |
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[7908ba5b] | 670 | #ifdef __cplusplus |
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| 671 | } |
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| 672 | #endif |
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| 673 | |
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| 674 | #endif |
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