source: rtems/cpukit/score/cpu/i386/cpu.c @ a1df2fdc

5
Last change on this file since a1df2fdc was a1df2fdc, checked in by Joel Sherrill <joel@…>, on Mar 8, 2018 at 7:09:17 PM

i386/include/rtems/score/types.h: Eliminate this file

Updates #3327.

  • Property mode set to 100644
File size: 9.4 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief Intel i386 Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#ifdef HAVE_CONFIG_H
17#include "config.h"
18#endif
19
20#include <inttypes.h>
21
22#include <rtems.h>
23#include <rtems/system.h>
24#include <rtems/score/isr.h>
25#include <rtems/score/idtr.h>
26#include <rtems/score/tls.h>
27
28#include <rtems/bspIo.h>
29#include <rtems/score/percpu.h>
30#include <rtems/score/thread.h>
31
32#define I386_ASSERT_OFFSET(field, off) \
33  RTEMS_STATIC_ASSERT( \
34    offsetof(Context_Control, field) \
35      == I386_CONTEXT_CONTROL_ ## off ## _OFFSET, \
36    Context_Control_ ## field \
37  )
38
39I386_ASSERT_OFFSET(eflags, EFLAGS);
40I386_ASSERT_OFFSET(esp, ESP);
41I386_ASSERT_OFFSET(ebp, EBP);
42I386_ASSERT_OFFSET(ebx, EBX);
43I386_ASSERT_OFFSET(esi, ESI);
44I386_ASSERT_OFFSET(edi, EDI);
45
46RTEMS_STATIC_ASSERT(
47  offsetof(Context_Control, gs)
48    == I386_CONTEXT_CONTROL_GS_0_OFFSET,
49  Context_Control_gs_0
50);
51
52#ifdef RTEMS_SMP
53  I386_ASSERT_OFFSET(is_executing, IS_EXECUTING);
54#endif
55
56#if CPU_HARDWARE_FP
57Context_Control_fp _CPU_Null_fp_context;
58#endif
59
60void _CPU_Initialize(void)
61{
62#if CPU_HARDWARE_FP
63  register uint16_t             fp_status __asm__ ("ax");
64  register Context_Control_fp  *fp_context;
65#endif
66
67  /*
68   *  The following code saves a NULL i387 context which is given
69   *  to each task at start and restart time.  The following code
70   *  is based upon that provided in the i386 Programmer's
71   *  Manual and should work on any coprocessor greater than
72   *  the i80287.
73   *
74   *  NOTE: The NO WAIT form of the coprocessor instructions
75   *        MUST be used in case there is not a coprocessor
76   *        to wait for.
77   */
78
79#if CPU_HARDWARE_FP
80  fp_status = 0xa5a5;
81  __asm__ volatile( "fninit" );
82  __asm__ volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
83
84  if ( fp_status ==  0 ) {
85
86    fp_context = &_CPU_Null_fp_context;
87
88#ifdef __SSE__
89        asm volatile( "fstcw %0":"=m"(fp_context->fpucw) );
90#else
91    __asm__ volatile( "fsave (%0)" : "=r" (fp_context)
92                               : "0"  (fp_context)
93                );
94#endif
95  }
96#endif
97
98#ifdef __SSE__
99
100  __asm__ volatile("stmxcsr %0":"=m"(fp_context->mxcsr));
101
102  /* The BSP must enable the SSE extensions (early).
103   * If any SSE instruction was already attempted
104   * then that crashed the system.
105   * As a courtesy, we double-check here but it
106   * may be too late (which is also why we don't
107   * enable SSE here).
108   */
109  {
110  uint32_t cr4;
111    __asm__ __volatile__("mov %%cr4, %0":"=r"(cr4));
112    if ( 0x600 != (cr4 & 0x600) ) {
113      printk("PANIC: RTEMS was compiled for SSE but BSP did not enable it"
114             "(CR4: 0%" PRIu32 ")\n", cr4);
115      while ( 1 ) {
116        __asm__ __volatile__("hlt");
117          }
118        }
119  }
120#endif
121}
122
123/*
124 * Stack alignment note:
125 *
126 * We want the stack to look to the '_entry_point' routine
127 * like an ordinary stack frame as if '_entry_point' was
128 * called from C-code.
129 * Note that '_entry_point' is jumped-to by the 'ret'
130 * instruction returning from _CPU_Context_switch() or
131 * _CPU_Context_restore() thus popping the _entry_point
132 * from the stack.
133 * However, _entry_point expects a frame to look like this:
134 *
135 *      args        [_Thread_Handler expects no args, however]
136 *      ------      (alignment boundary)
137 * SP-> return_addr return here when _entry_point returns which (never happens)
138 *
139 *
140 * Hence we must initialize the stack as follows
141 *
142 *         [arg1          ]:  n/a
143 *         [arg0 (aligned)]:  n/a
144 *         [ret. addr     ]:  NULL
145 * SP->    [jump-target   ]:  _entry_point
146 *
147 * When Context_switch returns it pops the _entry_point from
148 * the stack which then finds a standard layout.
149 */
150
151void _CPU_Context_Initialize(
152  Context_Control *the_context,
153  void *_stack_base,
154  size_t _size,
155  uint32_t _isr,
156  void (*_entry_point)( void ),
157  bool is_fp,
158  void *tls_area
159)
160{
161  uint32_t _stack;
162  uint32_t tcb;
163
164  (void) is_fp; /* avoid warning for being unused */
165
166  if ( _isr ) {
167    the_context->eflags = CPU_EFLAGS_INTERRUPTS_OFF;
168  } else {
169    the_context->eflags = CPU_EFLAGS_INTERRUPTS_ON;
170  }
171
172  _stack  = ((uint32_t)(_stack_base)) + (_size);
173  _stack &= ~ (CPU_STACK_ALIGNMENT - 1);
174  _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */
175  *((proc_ptr *)(_stack)) = (_entry_point);
176  the_context->ebp     = (void *) 0;
177  the_context->esp     = (void *) _stack;
178
179  if ( tls_area != NULL ) {
180    tcb = (uint32_t) _TLS_TCB_after_TLS_block_initialize( tls_area );
181  } else {
182    tcb = 0;
183  }
184
185  the_context->gs.limit_15_0 = 0xffff;
186  the_context->gs.base_address_15_0 = (tcb >> 0) & 0xffff;
187  the_context->gs.type = 0x2;
188  the_context->gs.descriptor_type = 0x1;
189  the_context->gs.limit_19_16 = 0xf;
190  the_context->gs.present = 0x1;
191  the_context->gs.operation_size = 0x1;
192  the_context->gs.granularity = 0x1;
193  the_context->gs.base_address_23_16 = (tcb >> 16) & 0xff;
194  the_context->gs.base_address_31_24 = (tcb >> 24) & 0xff;
195}
196
197uint32_t   _CPU_ISR_Get_level( void )
198{
199  uint32_t   level;
200
201#if !defined(RTEMS_PARAVIRT)
202  i386_get_interrupt_level( level );
203#else
204  level = i386_get_interrupt_level();
205#endif
206
207  return level;
208}
209
210struct Frame_ {
211        struct Frame_  *up;
212        uintptr_t               pc;
213};
214
215void _CPU_Exception_frame_print (const CPU_Exception_frame *ctx)
216{
217  unsigned int faultAddr = 0;
218  printk("----------------------------------------------------------\n");
219  printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %" PRId32 "\n",
220         ctx->idtIndex,
221         ctx->eip,
222         _Thread_Executing->Object.id);
223  printk("----------------------------------------------------------\n");
224  printk("Processor execution context at time of the fault was  :\n");
225  printk("----------------------------------------------------------\n");
226  printk(" EAX = %" PRIx32 "    EBX = %" PRIx32 "       ECX = %" PRIx32 "       EDX = %" PRIx32 "\n",
227         ctx->eax, ctx->ebx, ctx->ecx, ctx->edx);
228  printk(" ESI = %" PRIx32 "    EDI = %" PRIx32 "       EBP = %" PRIx32 "       ESP = %" PRIx32 "\n",
229         ctx->esi, ctx->edi, ctx->ebp, ctx->esp0);
230  printk("----------------------------------------------------------\n");
231  printk("Error code pushed by processor itself (if not 0) = %" PRIx32 "\n",
232         ctx->faultCode);
233  printk("----------------------------------------------------------\n");
234  if (ctx->idtIndex == I386_EXCEPTION_PAGE_FAULT){
235    faultAddr = i386_get_cr2();
236    printk("Page fault linear address (CR2) = %x\n", faultAddr);
237    printk("----------------------------------------------------------\n\n");
238  }
239 if (_ISR_Nest_level > 0) {
240    /*
241     * In this case we shall not delete the task interrupted as
242     * it has nothing to do with the fault. We cannot return either
243     * because the eip points to the faulty instruction so...
244     */
245    printk("Exception while executing ISR!!!. System locked\n");
246  }
247  else {
248        struct Frame_ *fp = (struct Frame_*)ctx->ebp;
249        int           i;
250
251        printk("Call Stack Trace of EIP:\n");
252        if ( fp ) {
253                for ( i=1; fp->up; fp=fp->up, i++ ) {
254                        printk("0x%08" PRIx32 " ",fp->pc);
255                        if ( ! (i&3) )
256                                printk("\n");
257                }
258        }
259        printk("\n");
260    /*
261     * OK I could probably use a simplified version but at least this
262     * should work.
263     */
264#if 0
265    printk(" ************ FAULTY THREAD WILL BE SUSPENDED **************\n");
266    rtems_task_suspend(_Thread_Executing->Object.id);
267#endif
268  }
269}
270
271static void _defaultExcHandler (CPU_Exception_frame *ctx)
272{
273  rtems_fatal(
274    RTEMS_FATAL_SOURCE_EXCEPTION,
275    (rtems_fatal_code) ctx
276  );
277}
278
279cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
280
281extern void rtems_exception_prologue_0(void);
282extern void rtems_exception_prologue_1(void);
283extern void rtems_exception_prologue_2(void);
284extern void rtems_exception_prologue_3(void);
285extern void rtems_exception_prologue_4(void);
286extern void rtems_exception_prologue_5(void);
287extern void rtems_exception_prologue_6(void);
288extern void rtems_exception_prologue_7(void);
289extern void rtems_exception_prologue_8(void);
290extern void rtems_exception_prologue_9(void);
291extern void rtems_exception_prologue_10(void);
292extern void rtems_exception_prologue_11(void);
293extern void rtems_exception_prologue_12(void);
294extern void rtems_exception_prologue_13(void);
295extern void rtems_exception_prologue_14(void);
296extern void rtems_exception_prologue_16(void);
297extern void rtems_exception_prologue_17(void);
298extern void rtems_exception_prologue_18(void);
299#ifdef __SSE__
300extern void rtems_exception_prologue_19(void);
301#endif
302
303static rtems_raw_irq_hdl tbl[] = {
304         rtems_exception_prologue_0,
305         rtems_exception_prologue_1,
306         rtems_exception_prologue_2,
307         rtems_exception_prologue_3,
308         rtems_exception_prologue_4,
309         rtems_exception_prologue_5,
310         rtems_exception_prologue_6,
311         rtems_exception_prologue_7,
312         rtems_exception_prologue_8,
313         rtems_exception_prologue_9,
314         rtems_exception_prologue_10,
315         rtems_exception_prologue_11,
316         rtems_exception_prologue_12,
317         rtems_exception_prologue_13,
318         rtems_exception_prologue_14,
319     0,
320         rtems_exception_prologue_16,
321         rtems_exception_prologue_17,
322         rtems_exception_prologue_18,
323#ifdef __SSE__
324         rtems_exception_prologue_19,
325#endif
326};
327
328void rtems_exception_init_mngt(void)
329{
330      size_t                     i,j;
331      interrupt_gate_descriptor  *currentIdtEntry;
332      unsigned                   limit;
333      unsigned                   level;
334
335      i = sizeof(tbl) / sizeof (rtems_raw_irq_hdl);
336
337      i386_get_info_from_IDTR (&currentIdtEntry, &limit);
338
339      _CPU_ISR_Disable(level);
340      for (j = 0; j < i; j++) {
341        create_interrupt_gate_descriptor (&currentIdtEntry[j], tbl[j]);
342      }
343      _CPU_ISR_Enable(level);
344}
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