1 | /* |
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2 | * Intel i386 Dependent Source |
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3 | * |
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4 | * |
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5 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * All rights assigned to U.S. Government, 1994. |
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8 | * |
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9 | * This material may be reproduced by or for the U.S. Government pursuant |
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10 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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11 | * notice must appear in all copies of this file and its derivatives. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | #include <rtems/system.h> |
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17 | #include <rtems/score/isr.h> |
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18 | |
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19 | /* _CPU_Initialize |
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20 | * |
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21 | * This routine performs processor dependent initialization. |
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22 | * |
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23 | * INPUT PARAMETERS: |
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24 | * cpu_table - CPU table to initialize |
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25 | * thread_dispatch - address of disptaching routine |
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26 | */ |
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27 | |
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28 | |
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29 | void _CPU_Initialize( |
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30 | rtems_cpu_table *cpu_table, |
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31 | void (*thread_dispatch) /* ignored on this CPU */ |
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32 | ) |
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33 | { |
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34 | register unsigned16 fp_status asm ("ax"); |
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35 | register void *fp_context; |
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36 | |
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37 | _CPU_Table = *cpu_table; |
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38 | |
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39 | /* |
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40 | * The following code saves a NULL i387 context which is given |
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41 | * to each task at start and restart time. The following code |
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42 | * is based upon that provided in the i386 Programmer's |
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43 | * Manual and should work on any coprocessor greater than |
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44 | * the i80287. |
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45 | * |
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46 | * NOTE: The NO RTEMS_WAIT form of the coprocessor instructions |
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47 | * MUST be used in case there is not a coprocessor |
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48 | * to wait for. |
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49 | */ |
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50 | |
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51 | fp_status = 0xa5a5; |
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52 | asm volatile( "fninit" ); |
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53 | asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) ); |
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54 | |
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55 | if ( fp_status == 0 ) { |
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56 | |
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57 | fp_context = &_CPU_Null_fp_context; |
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58 | |
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59 | asm volatile( "fsave (%0)" : "=r" (fp_context) |
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60 | : "0" (fp_context) |
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61 | ); |
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62 | } |
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63 | } |
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64 | |
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65 | /*PAGE |
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66 | * |
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67 | * _CPU_ISR_Get_level |
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68 | */ |
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69 | |
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70 | unsigned32 _CPU_ISR_Get_level( void ) |
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71 | { |
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72 | unsigned32 level; |
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73 | |
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74 | i386_get_interrupt_level( level ); |
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75 | |
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76 | return level; |
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77 | } |
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78 | |
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79 | /*PAGE |
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80 | * |
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81 | * _CPU_ISR_install_raw_handler |
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82 | */ |
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83 | |
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84 | #if __GO32__ |
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85 | #include <go32.h> |
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86 | #include <dpmi.h> |
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87 | #endif /* __GO32__ */ |
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88 | |
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89 | void _CPU_ISR_install_raw_handler( |
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90 | unsigned32 vector, |
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91 | proc_ptr new_handler, |
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92 | proc_ptr *old_handler |
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93 | ) |
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94 | { |
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95 | #if __GO32__ |
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96 | _go32_dpmi_seginfo handler_info; |
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97 | |
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98 | /* get the address of the old handler */ |
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99 | _go32_dpmi_get_protected_mode_interrupt_vector( vector, &handler_info); |
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100 | |
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101 | /* Notice how we're failing to save the pm_segment portion of the */ |
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102 | /* structure here? That means we might crash the system if we */ |
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103 | /* try to restore the ISR. Can't fix this until i386_isr is */ |
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104 | /* redefined. XXX [BHC]. */ |
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105 | *old_handler = (proc_ptr *) handler_info.pm_offset; |
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106 | |
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107 | handler_info.pm_offset = (u_long) new_handler; |
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108 | handler_info.pm_selector = _go32_my_cs(); |
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109 | |
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110 | /* install the IDT entry */ |
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111 | _go32_dpmi_set_protected_mode_interrupt_vector( vector, &handler_info ); |
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112 | #else |
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113 | i386_IDT_slot idt; |
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114 | unsigned32 handler; |
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115 | |
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116 | *old_handler = 0; /* XXX not supported */ |
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117 | |
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118 | handler = (unsigned32) new_handler; |
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119 | |
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120 | /* build the IDT entry */ |
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121 | idt.offset_0_15 = handler & 0xffff; |
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122 | idt.segment_selector = i386_get_cs(); |
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123 | idt.reserved = 0x00; |
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124 | idt.p_dpl = 0x8e; /* present, ISR */ |
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125 | idt.offset_16_31 = handler >> 16; |
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126 | |
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127 | /* install the IDT entry */ |
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128 | i386_Install_idt( |
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129 | (unsigned32) &idt, |
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130 | _CPU_Table.interrupt_table_segment, |
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131 | (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector) |
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132 | ); |
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133 | #endif |
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134 | } |
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135 | |
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136 | /*PAGE |
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137 | * |
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138 | * _CPU_ISR_install_vector |
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139 | * |
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140 | * This kernel routine installs the RTEMS handler for the |
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141 | * specified vector. |
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142 | * |
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143 | * Input parameters: |
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144 | * vector - interrupt vector number |
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145 | * old_handler - former ISR for this vector number |
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146 | * new_handler - replacement ISR for this vector number |
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147 | * |
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148 | * Output parameters: NONE |
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149 | * |
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150 | */ |
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151 | |
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152 | void _ISR_Handler_0(), _ISR_Handler_1(); |
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153 | |
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154 | #define PER_ISR_ENTRY \ |
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155 | (((unsigned32) _ISR_Handler_1 - (unsigned32) _ISR_Handler_0)) |
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156 | |
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157 | #define _Interrupt_Handler_entry( _vector ) \ |
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158 | (((unsigned32)_ISR_Handler_0) + ((_vector) * PER_ISR_ENTRY)) |
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159 | |
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160 | void _CPU_ISR_install_vector( |
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161 | unsigned32 vector, |
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162 | proc_ptr new_handler, |
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163 | proc_ptr *old_handler |
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164 | ) |
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165 | { |
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166 | proc_ptr ignored; |
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167 | unsigned32 unique_handler; |
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168 | |
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169 | *old_handler = _ISR_Vector_table[ vector ]; |
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170 | |
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171 | /* calculate the unique entry point for this vector */ |
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172 | unique_handler = _Interrupt_Handler_entry( vector ); |
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173 | |
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174 | _CPU_ISR_install_raw_handler( vector, (void *)unique_handler, &ignored ); |
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175 | |
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176 | _ISR_Vector_table[ vector ] = new_handler; |
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177 | } |
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