source: rtems/cpukit/score/cpu/i386/cpu.c @ 8bdcfc4

4.104.114.84.95
Last change on this file since 8bdcfc4 was c62d36f, checked in by Joel Sherrill <joel.sherrill@…>, on 10/06/95 at 20:01:20

SPARC merged and successfully tested w/o interrupt support

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 *  Intel i386 Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#include <rtems/system.h>
17#include <rtems/score/isr.h>
18
19/*  _CPU_Initialize
20 *
21 *  This routine performs processor dependent initialization.
22 *
23 *  INPUT PARAMETERS:
24 *    cpu_table       - CPU table to initialize
25 *    thread_dispatch - address of disptaching routine
26 */
27
28
29void _CPU_Initialize(
30  rtems_cpu_table  *cpu_table,
31  void      (*thread_dispatch)      /* ignored on this CPU */
32)
33{
34  register unsigned16  fp_status asm ("ax");
35  register void       *fp_context;
36
37  _CPU_Table = *cpu_table;
38
39  /*
40   *  The following code saves a NULL i387 context which is given
41   *  to each task at start and restart time.  The following code
42   *  is based upon that provided in the i386 Programmer's
43   *  Manual and should work on any coprocessor greater than
44   *  the i80287.
45   *
46   *  NOTE: The NO RTEMS_WAIT form of the coprocessor instructions
47   *        MUST be used in case there is not a coprocessor
48   *        to wait for.
49   */
50
51  fp_status = 0xa5a5;
52  asm volatile( "fninit" );
53  asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
54
55  if ( fp_status ==  0 ) {
56
57    fp_context = &_CPU_Null_fp_context;
58
59    asm volatile( "fsave (%0)" : "=r" (fp_context)
60                               : "0"  (fp_context)
61                );
62  }
63}
64
65/*PAGE
66 *
67 *  _CPU_ISR_Get_level
68 */
69 
70unsigned32 _CPU_ISR_Get_level( void )
71{
72  unsigned32 level;
73 
74  i386_get_interrupt_level( level );
75 
76  return level;
77}
78 
79/*PAGE
80 *
81 *  _CPU_ISR_install_raw_handler
82 */
83 
84#if __GO32__
85#include <go32.h>
86#include <dpmi.h>
87#endif /* __GO32__ */
88
89void _CPU_ISR_install_raw_handler(
90  unsigned32  vector,
91  proc_ptr    new_handler,
92  proc_ptr   *old_handler
93)
94{
95#if __GO32__
96    _go32_dpmi_seginfo handler_info;
97 
98    /* get the address of the old handler */
99    _go32_dpmi_get_protected_mode_interrupt_vector( vector, &handler_info);
100 
101    /* Notice how we're failing to save the pm_segment portion of the */
102    /* structure here?  That means we might crash the system if we  */
103    /* try to restore the ISR.  Can't fix this until i386_isr is  */
104    /* redefined.  XXX [BHC].           */
105    *old_handler = (proc_ptr *) handler_info.pm_offset;
106
107    handler_info.pm_offset = (u_long) new_handler;
108    handler_info.pm_selector = _go32_my_cs();
109
110    /* install the IDT entry */
111    _go32_dpmi_set_protected_mode_interrupt_vector( vector, &handler_info );
112#else
113  i386_IDT_slot idt;
114  unsigned32    handler;
115
116  *old_handler =  0;    /* XXX not supported */
117
118  handler = (unsigned32) new_handler;
119
120  /* build the IDT entry */
121  idt.offset_0_15      = handler & 0xffff;
122  idt.segment_selector = i386_get_cs();
123  idt.reserved         = 0x00;
124  idt.p_dpl            = 0x8e;         /* present, ISR */
125  idt.offset_16_31     = handler >> 16;
126
127  /* install the IDT entry */
128  i386_Install_idt(
129    (unsigned32) &idt,
130    _CPU_Table.interrupt_table_segment,
131    (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
132  );
133#endif
134}
135
136/*PAGE
137 *
138 *  _CPU_ISR_install_vector
139 *
140 *  This kernel routine installs the RTEMS handler for the
141 *  specified vector.
142 *
143 *  Input parameters:
144 *    vector      - interrupt vector number
145 *    old_handler - former ISR for this vector number
146 *    new_handler - replacement ISR for this vector number
147 *
148 *  Output parameters:  NONE
149 *
150 */
151
152void _ISR_Handler_0(), _ISR_Handler_1();
153
154#define PER_ISR_ENTRY \
155    (((unsigned32) _ISR_Handler_1 - (unsigned32) _ISR_Handler_0))
156
157#define _Interrupt_Handler_entry( _vector ) \
158   (((unsigned32)_ISR_Handler_0) + ((_vector) * PER_ISR_ENTRY))
159
160void _CPU_ISR_install_vector(
161  unsigned32  vector,
162  proc_ptr    new_handler,
163  proc_ptr   *old_handler
164)
165{
166  proc_ptr      ignored;
167  unsigned32    unique_handler;
168
169  *old_handler = _ISR_Vector_table[ vector ];
170
171  /* calculate the unique entry point for this vector */
172  unique_handler = _Interrupt_Handler_entry( vector );
173
174  _CPU_ISR_install_raw_handler( vector, (void *)unique_handler, &ignored );
175
176  _ISR_Vector_table[ vector ] = new_handler;
177}
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