source: rtems/cpukit/score/cpu/i386/cpu.c @ 7549e14

4.104.114.84.95
Last change on this file since 7549e14 was 67a2288, checked in by Joel Sherrill <joel.sherrill@…>, on 07/23/98 at 22:02:34

Patch from Eric VALETTE <valette@…>:

Here is a enhanced version of my previous patch. This patch enables
to potentially share the new interrupt management code for all Intel targets
(pc386, go32 and force386) bsp.

Note : this patch is complete only for pc386. It still needs to

be completed for go32 and force386. I carrefully checked
that anything needed is in for force386 (only some function
name changes for IDT manipulation and GDT segment
manipulation). But anyway I will not be able to test any
of theses targets...

  • Property mode set to 100644
File size: 1.7 KB
Line 
1/*
2 *  Intel i386 Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1998.
6 *  On-Line Applications Research Corporation (OAR).
7 *  Copyright assigned to U.S. Government, 1994.
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#include <rtems/system.h>
17#include <rtems/score/isr.h>
18
19/*  _CPU_Initialize
20 *
21 *  This routine performs processor dependent initialization.
22 *
23 *  INPUT PARAMETERS:
24 *    cpu_table       - CPU table to initialize
25 *    thread_dispatch - address of disptaching routine
26 */
27
28
29void _CPU_Initialize(
30  rtems_cpu_table  *cpu_table,
31  void      (*thread_dispatch)      /* ignored on this CPU */
32)
33{
34  register unsigned16  fp_status asm ("ax");
35  register void       *fp_context;
36
37  _CPU_Table = *cpu_table;
38
39  /*
40   *  The following code saves a NULL i387 context which is given
41   *  to each task at start and restart time.  The following code
42   *  is based upon that provided in the i386 Programmer's
43   *  Manual and should work on any coprocessor greater than
44   *  the i80287.
45   *
46   *  NOTE: The NO RTEMS_WAIT form of the coprocessor instructions
47   *        MUST be used in case there is not a coprocessor
48   *        to wait for.
49   */
50
51  fp_status = 0xa5a5;
52  asm volatile( "fninit" );
53  asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
54
55  if ( fp_status ==  0 ) {
56
57    fp_context = &_CPU_Null_fp_context;
58
59    asm volatile( "fsave (%0)" : "=r" (fp_context)
60                               : "0"  (fp_context)
61                );
62  }
63}
64
65/*PAGE
66 *
67 *  _CPU_ISR_Get_level
68 */
69 
70unsigned32 _CPU_ISR_Get_level( void )
71{
72  unsigned32 level;
73 
74  i386_get_interrupt_level( level );
75 
76  return level;
77}
78 
Note: See TracBrowser for help on using the repository browser.