source: rtems/cpukit/score/cpu/i386/cpu.c @ 3652ad35

4.104.114.84.95
Last change on this file since 3652ad35 was 3652ad35, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 19, 1995 at 2:53:29 PM

Minor bug fixes to get all targets compilable and running. The
single biggest changes were the expansion of the workspace size
macro to include other types of objects and the increase in the
minimum stack size for most CPUs.

  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 *  Intel i386 Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#include <rtems/system.h>
17#include <rtems/fatal.h>
18#include <rtems/core/isr.h>
19#include <rtems/core/wkspace.h>
20
21/*  _CPU_Initialize
22 *
23 *  This routine performs processor dependent initialization.
24 *
25 *  INPUT PARAMETERS:
26 *    cpu_table       - CPU table to initialize
27 *    thread_dispatch - address of disptaching routine
28 */
29
30
31void _CPU_Initialize(
32  rtems_cpu_table  *cpu_table,
33  void      (*thread_dispatch)      /* ignored on this CPU */
34)
35{
36  register unsigned16  fp_status asm ("ax");
37  register void       *fp_context;
38
39  _CPU_Table = *cpu_table;
40
41  /*
42   *  The following code saves a NULL i387 context which is given
43   *  to each task at start and restart time.  The following code
44   *  is based upon that provided in the i386 Programmer's
45   *  Manual and should work on any coprocessor greater than
46   *  the i80287.
47   *
48   *  NOTE: The NO RTEMS_WAIT form of the coprocessor instructions
49   *        MUST be used in case there is not a coprocessor
50   *        to wait for.
51   */
52
53  fp_status = 0xa5a5;
54  asm volatile( "fninit" );
55  asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
56
57  if ( fp_status ==  0 ) {
58
59    fp_context = &_CPU_Null_fp_context;
60
61    asm volatile( "fsave (%0)" : "=r" (fp_context)
62                               : "0"  (fp_context)
63                );
64  }
65}
66
67/*PAGE
68 *
69 *  _CPU_ISR_Get_level
70 */
71 
72unsigned32 _CPU_ISR_Get_level( void )
73{
74  unsigned32 level;
75 
76  i386_get_interrupt_level( level );
77 
78  return level;
79}
80 
81/*PAGE
82 *
83 *  _CPU_ISR_install_raw_handler
84 */
85 
86#if __GO32__
87#include <go32.h>
88#include <dpmi.h>
89#endif /* __GO32__ */
90
91void _CPU_ISR_install_raw_handler(
92  unsigned32  vector,
93  proc_ptr    new_handler,
94  proc_ptr   *old_handler
95)
96{
97#if __GO32__
98    _go32_dpmi_seginfo handler_info;
99 
100    /* get the address of the old handler */
101    _go32_dpmi_get_protected_mode_interrupt_vector( vector, &handler_info);
102 
103    /* Notice how we're failing to save the pm_segment portion of the */
104    /* structure here?  That means we might crash the system if we  */
105    /* try to restore the ISR.  Can't fix this until i386_isr is  */
106    /* redefined.  XXX [BHC].           */
107    *old_handler = (proc_ptr *) handler_info.pm_offset;
108
109    handler_info.pm_offset = (u_long) new_handler;
110    handler_info.pm_selector = _go32_my_cs();
111
112    /* install the IDT entry */
113    _go32_dpmi_set_protected_mode_interrupt_vector( vector, &handler_info );
114#else
115  i386_IDT_slot idt;
116  unsigned32    handler;
117
118  *old_handler =  0;    /* XXX not supported */
119
120  handler = (unsigned32) new_handler;
121
122  /* build the IDT entry */
123  idt.offset_0_15      = handler & 0xffff;
124  idt.segment_selector = i386_get_cs();
125  idt.reserved         = 0x00;
126  idt.p_dpl            = 0x8e;         /* present, ISR */
127  idt.offset_16_31     = handler >> 16;
128
129  /* install the IDT entry */
130  i386_Install_idt(
131    (unsigned32) &idt,
132    _CPU_Table.interrupt_table_segment,
133    (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
134  );
135#endif
136}
137
138/*PAGE
139 *
140 *  _CPU_ISR_install_vector
141 *
142 *  This kernel routine installs the RTEMS handler for the
143 *  specified vector.
144 *
145 *  Input parameters:
146 *    vector      - interrupt vector number
147 *    old_handler - former ISR for this vector number
148 *    new_handler - replacement ISR for this vector number
149 *
150 *  Output parameters:  NONE
151 *
152 */
153
154void _ISR_Handler_0(), _ISR_Handler_1();
155
156#define PER_ISR_ENTRY \
157    (((unsigned32) _ISR_Handler_1 - (unsigned32) _ISR_Handler_0))
158
159#define _Interrupt_Handler_entry( _vector ) \
160   (((unsigned32)_ISR_Handler_0) + ((_vector) * PER_ISR_ENTRY))
161
162void _CPU_ISR_install_vector(
163  unsigned32  vector,
164  proc_ptr    new_handler,
165  proc_ptr   *old_handler
166)
167{
168  proc_ptr      ignored;
169  unsigned32    unique_handler;
170
171  *old_handler = _ISR_Vector_table[ vector ];
172
173  /* calculate the unique entry point for this vector */
174  unique_handler = _Interrupt_Handler_entry( vector );
175
176  _CPU_ISR_install_raw_handler( vector, (void *)unique_handler, &ignored );
177
178  _ISR_Vector_table[ vector ] = new_handler;
179}
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