1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Intel i386 Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-1999. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifdef HAVE_CONFIG_H |
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17 | #include "config.h" |
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18 | #endif |
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19 | |
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20 | #include <inttypes.h> |
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21 | |
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22 | #include <rtems.h> |
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23 | #include <rtems/system.h> |
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24 | #include <rtems/score/types.h> |
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25 | #include <rtems/score/isr.h> |
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26 | #include <rtems/score/idtr.h> |
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27 | #include <rtems/score/tls.h> |
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28 | |
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29 | #include <rtems/bspIo.h> |
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30 | #include <rtems/score/percpu.h> |
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31 | #include <rtems/score/thread.h> |
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32 | |
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33 | #define I386_ASSERT_OFFSET(field, off) \ |
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34 | RTEMS_STATIC_ASSERT( \ |
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35 | offsetof(Context_Control, field) \ |
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36 | == I386_CONTEXT_CONTROL_ ## off ## _OFFSET, \ |
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37 | Context_Control_ ## field \ |
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38 | ) |
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39 | |
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40 | I386_ASSERT_OFFSET(eflags, EFLAGS); |
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41 | I386_ASSERT_OFFSET(esp, ESP); |
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42 | I386_ASSERT_OFFSET(ebp, EBP); |
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43 | I386_ASSERT_OFFSET(ebx, EBX); |
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44 | I386_ASSERT_OFFSET(esi, ESI); |
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45 | I386_ASSERT_OFFSET(edi, EDI); |
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46 | |
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47 | RTEMS_STATIC_ASSERT( |
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48 | offsetof(Context_Control, gs) |
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49 | == I386_CONTEXT_CONTROL_GS_0_OFFSET, |
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50 | Context_Control_gs_0 |
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51 | ); |
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52 | |
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53 | #ifdef RTEMS_SMP |
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54 | I386_ASSERT_OFFSET(is_executing, IS_EXECUTING); |
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55 | #endif |
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56 | |
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57 | #if CPU_HARDWARE_FP |
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58 | Context_Control_fp _CPU_Null_fp_context; |
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59 | #endif |
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60 | |
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61 | void _CPU_Initialize(void) |
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62 | { |
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63 | #if CPU_HARDWARE_FP |
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64 | register uint16_t fp_status __asm__ ("ax"); |
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65 | register Context_Control_fp *fp_context; |
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66 | #endif |
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67 | |
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68 | /* |
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69 | * The following code saves a NULL i387 context which is given |
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70 | * to each task at start and restart time. The following code |
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71 | * is based upon that provided in the i386 Programmer's |
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72 | * Manual and should work on any coprocessor greater than |
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73 | * the i80287. |
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74 | * |
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75 | * NOTE: The NO WAIT form of the coprocessor instructions |
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76 | * MUST be used in case there is not a coprocessor |
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77 | * to wait for. |
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78 | */ |
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79 | |
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80 | #if CPU_HARDWARE_FP |
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81 | fp_status = 0xa5a5; |
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82 | __asm__ volatile( "fninit" ); |
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83 | __asm__ volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) ); |
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84 | |
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85 | if ( fp_status == 0 ) { |
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86 | |
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87 | fp_context = &_CPU_Null_fp_context; |
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88 | |
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89 | #ifdef __SSE__ |
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90 | asm volatile( "fstcw %0":"=m"(fp_context->fpucw) ); |
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91 | #else |
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92 | __asm__ volatile( "fsave (%0)" : "=r" (fp_context) |
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93 | : "0" (fp_context) |
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94 | ); |
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95 | #endif |
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96 | } |
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97 | #endif |
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98 | |
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99 | #ifdef __SSE__ |
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100 | |
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101 | __asm__ volatile("stmxcsr %0":"=m"(fp_context->mxcsr)); |
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102 | |
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103 | /* The BSP must enable the SSE extensions (early). |
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104 | * If any SSE instruction was already attempted |
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105 | * then that crashed the system. |
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106 | * As a courtesy, we double-check here but it |
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107 | * may be too late (which is also why we don't |
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108 | * enable SSE here). |
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109 | */ |
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110 | { |
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111 | uint32_t cr4; |
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112 | __asm__ __volatile__("mov %%cr4, %0":"=r"(cr4)); |
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113 | if ( 0x600 != (cr4 & 0x600) ) { |
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114 | printk("PANIC: RTEMS was compiled for SSE but BSP did not enable it" |
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115 | "(CR4: 0%" PRIu32 ")\n", cr4); |
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116 | while ( 1 ) { |
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117 | __asm__ __volatile__("hlt"); |
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118 | } |
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119 | } |
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120 | } |
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121 | #endif |
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122 | } |
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123 | |
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124 | /* |
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125 | * Stack alignment note: |
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126 | * |
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127 | * We want the stack to look to the '_entry_point' routine |
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128 | * like an ordinary stack frame as if '_entry_point' was |
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129 | * called from C-code. |
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130 | * Note that '_entry_point' is jumped-to by the 'ret' |
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131 | * instruction returning from _CPU_Context_switch() or |
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132 | * _CPU_Context_restore() thus popping the _entry_point |
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133 | * from the stack. |
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134 | * However, _entry_point expects a frame to look like this: |
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135 | * |
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136 | * args [_Thread_Handler expects no args, however] |
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137 | * ------ (alignment boundary) |
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138 | * SP-> return_addr return here when _entry_point returns which (never happens) |
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139 | * |
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140 | * |
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141 | * Hence we must initialize the stack as follows |
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142 | * |
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143 | * [arg1 ]: n/a |
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144 | * [arg0 (aligned)]: n/a |
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145 | * [ret. addr ]: NULL |
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146 | * SP-> [jump-target ]: _entry_point |
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147 | * |
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148 | * When Context_switch returns it pops the _entry_point from |
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149 | * the stack which then finds a standard layout. |
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150 | */ |
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151 | |
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152 | void _CPU_Context_Initialize( |
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153 | Context_Control *the_context, |
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154 | void *_stack_base, |
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155 | size_t _size, |
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156 | uint32_t _isr, |
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157 | void (*_entry_point)( void ), |
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158 | bool is_fp, |
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159 | void *tls_area |
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160 | ) |
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161 | { |
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162 | uint32_t _stack; |
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163 | uint32_t tcb; |
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164 | |
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165 | (void) is_fp; /* avoid warning for being unused */ |
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166 | |
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167 | if ( _isr ) { |
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168 | the_context->eflags = CPU_EFLAGS_INTERRUPTS_OFF; |
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169 | } else { |
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170 | the_context->eflags = CPU_EFLAGS_INTERRUPTS_ON; |
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171 | } |
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172 | |
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173 | _stack = ((uint32_t)(_stack_base)) + (_size); |
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174 | _stack &= ~ (CPU_STACK_ALIGNMENT - 1); |
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175 | _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ |
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176 | *((proc_ptr *)(_stack)) = (_entry_point); |
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177 | the_context->ebp = (void *) 0; |
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178 | the_context->esp = (void *) _stack; |
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179 | |
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180 | if ( tls_area != NULL ) { |
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181 | tcb = (uint32_t) _TLS_TCB_after_TLS_block_initialize( tls_area ); |
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182 | } else { |
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183 | tcb = 0; |
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184 | } |
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185 | |
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186 | the_context->gs.limit_15_0 = 0xffff; |
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187 | the_context->gs.base_address_15_0 = (tcb >> 0) & 0xffff; |
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188 | the_context->gs.type = 0x2; |
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189 | the_context->gs.descriptor_type = 0x1; |
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190 | the_context->gs.limit_19_16 = 0xf; |
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191 | the_context->gs.present = 0x1; |
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192 | the_context->gs.operation_size = 0x1; |
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193 | the_context->gs.granularity = 0x1; |
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194 | the_context->gs.base_address_23_16 = (tcb >> 16) & 0xff; |
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195 | the_context->gs.base_address_31_24 = (tcb >> 24) & 0xff; |
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196 | } |
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197 | |
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198 | uint32_t _CPU_ISR_Get_level( void ) |
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199 | { |
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200 | uint32_t level; |
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201 | |
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202 | #if !defined(RTEMS_PARAVIRT) |
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203 | i386_get_interrupt_level( level ); |
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204 | #else |
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205 | level = i386_get_interrupt_level(); |
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206 | #endif |
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207 | |
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208 | return level; |
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209 | } |
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210 | |
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211 | struct Frame_ { |
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212 | struct Frame_ *up; |
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213 | uintptr_t pc; |
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214 | }; |
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215 | |
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216 | void _CPU_Exception_frame_print (const CPU_Exception_frame *ctx) |
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217 | { |
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218 | unsigned int faultAddr = 0; |
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219 | printk("----------------------------------------------------------\n"); |
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220 | printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %" PRId32 "\n", |
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221 | ctx->idtIndex, |
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222 | ctx->eip, |
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223 | _Thread_Executing->Object.id); |
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224 | printk("----------------------------------------------------------\n"); |
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225 | printk("Processor execution context at time of the fault was :\n"); |
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226 | printk("----------------------------------------------------------\n"); |
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227 | printk(" EAX = %" PRIx32 " EBX = %" PRIx32 " ECX = %" PRIx32 " EDX = %" PRIx32 "\n", |
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228 | ctx->eax, ctx->ebx, ctx->ecx, ctx->edx); |
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229 | printk(" ESI = %" PRIx32 " EDI = %" PRIx32 " EBP = %" PRIx32 " ESP = %" PRIx32 "\n", |
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230 | ctx->esi, ctx->edi, ctx->ebp, ctx->esp0); |
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231 | printk("----------------------------------------------------------\n"); |
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232 | printk("Error code pushed by processor itself (if not 0) = %" PRIx32 "\n", |
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233 | ctx->faultCode); |
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234 | printk("----------------------------------------------------------\n"); |
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235 | if (ctx->idtIndex == I386_EXCEPTION_PAGE_FAULT){ |
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236 | faultAddr = i386_get_cr2(); |
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237 | printk("Page fault linear address (CR2) = %x\n", faultAddr); |
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238 | printk("----------------------------------------------------------\n\n"); |
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239 | } |
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240 | if (_ISR_Nest_level > 0) { |
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241 | /* |
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242 | * In this case we shall not delete the task interrupted as |
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243 | * it has nothing to do with the fault. We cannot return either |
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244 | * because the eip points to the faulty instruction so... |
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245 | */ |
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246 | printk("Exception while executing ISR!!!. System locked\n"); |
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247 | } |
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248 | else { |
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249 | struct Frame_ *fp = (struct Frame_*)ctx->ebp; |
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250 | int i; |
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251 | |
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252 | printk("Call Stack Trace of EIP:\n"); |
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253 | if ( fp ) { |
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254 | for ( i=1; fp->up; fp=fp->up, i++ ) { |
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255 | printk("0x%08" PRIx32 " ",fp->pc); |
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256 | if ( ! (i&3) ) |
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257 | printk("\n"); |
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258 | } |
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259 | } |
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260 | printk("\n"); |
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261 | /* |
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262 | * OK I could probably use a simplified version but at least this |
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263 | * should work. |
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264 | */ |
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265 | #if 0 |
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266 | printk(" ************ FAULTY THREAD WILL BE SUSPENDED **************\n"); |
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267 | rtems_task_suspend(_Thread_Executing->Object.id); |
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268 | #endif |
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269 | } |
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270 | } |
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271 | |
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272 | static void _defaultExcHandler (CPU_Exception_frame *ctx) |
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273 | { |
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274 | rtems_fatal( |
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275 | RTEMS_FATAL_SOURCE_EXCEPTION, |
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276 | (rtems_fatal_code) ctx |
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277 | ); |
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278 | } |
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279 | |
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280 | cpuExcHandlerType _currentExcHandler = _defaultExcHandler; |
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281 | |
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282 | extern void rtems_exception_prologue_0(void); |
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283 | extern void rtems_exception_prologue_1(void); |
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284 | extern void rtems_exception_prologue_2(void); |
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285 | extern void rtems_exception_prologue_3(void); |
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286 | extern void rtems_exception_prologue_4(void); |
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287 | extern void rtems_exception_prologue_5(void); |
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288 | extern void rtems_exception_prologue_6(void); |
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289 | extern void rtems_exception_prologue_7(void); |
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290 | extern void rtems_exception_prologue_8(void); |
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291 | extern void rtems_exception_prologue_9(void); |
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292 | extern void rtems_exception_prologue_10(void); |
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293 | extern void rtems_exception_prologue_11(void); |
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294 | extern void rtems_exception_prologue_12(void); |
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295 | extern void rtems_exception_prologue_13(void); |
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296 | extern void rtems_exception_prologue_14(void); |
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297 | extern void rtems_exception_prologue_16(void); |
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298 | extern void rtems_exception_prologue_17(void); |
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299 | extern void rtems_exception_prologue_18(void); |
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300 | #ifdef __SSE__ |
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301 | extern void rtems_exception_prologue_19(void); |
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302 | #endif |
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303 | |
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304 | static rtems_raw_irq_hdl tbl[] = { |
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305 | rtems_exception_prologue_0, |
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306 | rtems_exception_prologue_1, |
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307 | rtems_exception_prologue_2, |
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308 | rtems_exception_prologue_3, |
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309 | rtems_exception_prologue_4, |
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310 | rtems_exception_prologue_5, |
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311 | rtems_exception_prologue_6, |
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312 | rtems_exception_prologue_7, |
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313 | rtems_exception_prologue_8, |
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314 | rtems_exception_prologue_9, |
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315 | rtems_exception_prologue_10, |
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316 | rtems_exception_prologue_11, |
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317 | rtems_exception_prologue_12, |
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318 | rtems_exception_prologue_13, |
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319 | rtems_exception_prologue_14, |
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320 | 0, |
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321 | rtems_exception_prologue_16, |
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322 | rtems_exception_prologue_17, |
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323 | rtems_exception_prologue_18, |
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324 | #ifdef __SSE__ |
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325 | rtems_exception_prologue_19, |
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326 | #endif |
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327 | }; |
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328 | |
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329 | void rtems_exception_init_mngt(void) |
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330 | { |
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331 | size_t i,j; |
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332 | interrupt_gate_descriptor *currentIdtEntry; |
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333 | unsigned limit; |
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334 | unsigned level; |
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335 | |
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336 | i = sizeof(tbl) / sizeof (rtems_raw_irq_hdl); |
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337 | |
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338 | i386_get_info_from_IDTR (¤tIdtEntry, &limit); |
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339 | |
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340 | _CPU_ISR_Disable(level); |
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341 | for (j = 0; j < i; j++) { |
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342 | create_interrupt_gate_descriptor (¤tIdtEntry[j], tbl[j]); |
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343 | } |
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344 | _CPU_ISR_Enable(level); |
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345 | } |
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