source: rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 32.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief Hitachi H8300 CPU Department Source
5 *
6 * This include file contains information pertaining to the H8300
7 *  processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2006.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/h8300.h>
28#ifndef ASM
29  #include <rtems/bspIo.h>
30#endif
31
32/* conditional compilation parameters */
33
34/*
35 *  Should the calls to _Thread_Enable_dispatch be inlined?
36 *
37 *  If TRUE, then they are inlined.
38 *  If FALSE, then a subroutine call is made.
39 *
40 *  Basically this is an example of the classic trade-off of size
41 *  versus speed.  Inlining the call (TRUE) typically increases the
42 *  size of RTEMS while speeding up the enabling of dispatching.
43 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
44 *  only be 0 or 1 unless you are in an interrupt handler and that
45 *  interrupt handler invokes the executive.]  When not inlined
46 *  something calls _Thread_Enable_dispatch which in turns calls
47 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
48 *  one subroutine call is avoided entirely.]
49 *
50 *  H8300 Specific Information:
51 *
52 *  XXX
53 */
54
55#define CPU_INLINE_ENABLE_DISPATCH       FALSE
56
57/*
58 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
59 *  be unrolled one time?  In unrolled each iteration of the loop examines
60 *  two "nodes" on the chain being searched.  Otherwise, only one node
61 *  is examined per iteration.
62 *
63 *  If TRUE, then the loops are unrolled.
64 *  If FALSE, then the loops are not unrolled.
65 *
66 *  The primary factor in making this decision is the cost of disabling
67 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
68 *  body of the loop.  On some CPUs, the flash is more expensive than
69 *  one iteration of the loop body.  In this case, it might be desirable
70 *  to unroll the loop.  It is important to note that on some CPUs, this
71 *  code is the longest interrupt disable period in RTEMS.  So it is
72 *  necessary to strike a balance when setting this parameter.
73 *
74 *  H8300 Specific Information:
75 *
76 *  XXX
77 */
78
79#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
80
81/*
82 *  Should this target use 16 or 32 bit object Ids?
83 *
84 */
85#define RTEMS_USE_16_BIT_OBJECT
86
87/*
88 *  Does RTEMS manage a dedicated interrupt stack in software?
89 *
90 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
91 *  If FALSE, nothing is done.
92 *
93 *  If the CPU supports a dedicated interrupt stack in hardware,
94 *  then it is generally the responsibility of the BSP to allocate it
95 *  and set it up.
96 *
97 *  If the CPU does not support a dedicated interrupt stack, then
98 *  the porter has two options: (1) execute interrupts on the
99 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
100 *  interrupt stack.
101 *
102 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
103 *
104 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
105 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
106 *  possible that both are FALSE for a particular CPU.  Although it
107 *  is unclear what that would imply about the interrupt processing
108 *  procedure on that CPU.
109 *
110 *  H8300 Specific Information:
111 *
112 *  XXX
113 */
114
115#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
116
117/*
118 *  Does the CPU follow the simple vectored interrupt model?
119 *
120 *  If TRUE, then RTEMS allocates the vector table it internally manages.
121 *  If FALSE, then the BSP is assumed to allocate and manage the vector
122 *  table
123 *
124 *  H8300 Specific Information:
125 *
126 *  XXX document implementation including references if appropriate
127 */
128#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
129
130/*
131 *  Does this CPU have hardware support for a dedicated interrupt stack?
132 *
133 *  If TRUE, then it must be installed during initialization.
134 *  If FALSE, then no installation is performed.
135 *
136 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
137 *
138 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
139 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
140 *  possible that both are FALSE for a particular CPU.  Although it
141 *  is unclear what that would imply about the interrupt processing
142 *  procedure on that CPU.
143 *
144 *  H8300 Specific Information:
145 *
146 *  XXX
147 */
148
149#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
150
151/*
152 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
153 *
154 *  If TRUE, then the memory is allocated during initialization.
155 *  If FALSE, then the memory is allocated during initialization.
156 *
157 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
158 *
159 *  H8300 Specific Information:
160 *
161 *  XXX
162 */
163
164#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
165
166/*
167 *  Does the CPU have hardware floating point?
168 *
169 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
170 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
171 *
172 *  If there is a FP coprocessor such as the i387 or mc68881, then
173 *  the answer is TRUE.
174 *
175 *  The macro name "H8300_HAS_FPU" should be made CPU specific.
176 *  It indicates whether or not this CPU model has FP support.  For
177 *  example, it would be possible to have an i386_nofp CPU model
178 *  which set this to false to indicate that you have an i386 without
179 *  an i387 and wish to leave floating point support out of RTEMS.
180 *
181 *  H8300 Specific Information:
182 *
183 *  XXX
184 */
185
186#define CPU_HARDWARE_FP     FALSE
187
188/*
189 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
190 *
191 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
192 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
193 *
194 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
195 *
196 *  H8300 Specific Information:
197 *
198 *  XXX
199 */
200
201#define CPU_ALL_TASKS_ARE_FP     FALSE
202
203/*
204 *  Should the IDLE task have a floating point context?
205 *
206 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
207 *  and it has a floating point context which is switched in and out.
208 *  If FALSE, then the IDLE task does not have a floating point context.
209 *
210 *  Setting this to TRUE negatively impacts the time required to preempt
211 *  the IDLE task from an interrupt because the floating point context
212 *  must be saved as part of the preemption.
213 *
214 *  H8300 Specific Information:
215 *
216 *  XXX
217 */
218
219#define CPU_IDLE_TASK_IS_FP      FALSE
220
221/*
222 *  Should the saving of the floating point registers be deferred
223 *  until a context switch is made to another different floating point
224 *  task?
225 *
226 *  If TRUE, then the floating point context will not be stored until
227 *  necessary.  It will remain in the floating point registers and not
228 *  disturned until another floating point task is switched to.
229 *
230 *  If FALSE, then the floating point context is saved when a floating
231 *  point task is switched out and restored when the next floating point
232 *  task is restored.  The state of the floating point registers between
233 *  those two operations is not specified.
234 *
235 *  If the floating point context does NOT have to be saved as part of
236 *  interrupt dispatching, then it should be safe to set this to TRUE.
237 *
238 *  Setting this flag to TRUE results in using a different algorithm
239 *  for deciding when to save and restore the floating point context.
240 *  The deferred FP switch algorithm minimizes the number of times
241 *  the FP context is saved and restored.  The FP context is not saved
242 *  until a context switch is made to another, different FP task.
243 *  Thus in a system with only one FP task, the FP context will never
244 *  be saved or restored.
245 *
246 *  H8300 Specific Information:
247 *
248 *  XXX
249 */
250
251#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
252
253/*
254 *  Does this port provide a CPU dependent IDLE task implementation?
255 *
256 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
257 *  must be provided and is the default IDLE thread body instead of
258 *  _Internal_threads_Idle_thread_body.
259 *
260 *  If FALSE, then use the generic IDLE thread body if the BSP does
261 *  not provide one.
262 *
263 *  This is intended to allow for supporting processors which have
264 *  a low power or idle mode.  When the IDLE thread is executed, then
265 *  the CPU can be powered down.
266 *
267 *  The order of precedence for selecting the IDLE thread body is:
268 *
269 *    1.  BSP provided
270 *    2.  CPU dependent (if provided)
271 *    3.  generic (if no BSP and no CPU dependent)
272 *
273 *  H8300 Specific Information:
274 *
275 *  XXX
276 *  The port initially called a BSP dependent routine called
277 *  IDLE_Monitor.  The idle task body can be overridden by
278 *  the BSP in newer versions of RTEMS.
279 */
280
281#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
282
283/*
284 *  Does the stack grow up (toward higher addresses) or down
285 *  (toward lower addresses)?
286 *
287 *  If TRUE, then the grows upward.
288 *  If FALSE, then the grows toward smaller addresses.
289 *
290 *  H8300 Specific Information:
291 *
292 *  XXX
293 */
294
295#define CPU_STACK_GROWS_UP               FALSE
296
297/*
298 *  The following is the variable attribute used to force alignment
299 *  of critical RTEMS structures.  On some processors it may make
300 *  sense to have these aligned on tighter boundaries than
301 *  the minimum requirements of the compiler in order to have as
302 *  much of the critical data area as possible in a cache line.
303 *
304 *  The placement of this macro in the declaration of the variables
305 *  is based on the syntactically requirements of the GNU C
306 *  "__attribute__" extension.  For example with GNU C, use
307 *  the following to force a structures to a 32 byte boundary.
308 *
309 *      __attribute__ ((aligned (32)))
310 *
311 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
312 *         To benefit from using this, the data must be heavily
313 *         used so it will stay in the cache and used frequently enough
314 *         in the executive to justify turning this on.
315 *
316 *  H8300 Specific Information:
317 *
318 *  XXX
319 */
320
321#define CPU_STRUCTURE_ALIGNMENT
322
323#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
324
325/*
326 *  Define what is required to specify how the network to host conversion
327 *  routines are handled.
328 */
329
330#define CPU_BIG_ENDIAN                           TRUE
331#define CPU_LITTLE_ENDIAN                        FALSE
332
333/*
334 *  The following defines the number of bits actually used in the
335 *  interrupt field of the task mode.  How those bits map to the
336 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
337 *
338 *  H8300 Specific Information:
339 *
340 *  XXX
341 */
342
343#define CPU_MODES_INTERRUPT_MASK   0x00000001
344
345#define CPU_PER_CPU_CONTROL_SIZE 0
346
347/*
348 *  Processor defined structures required for cpukit/score.
349 *
350 *  H8300 Specific Information:
351 *
352 *  XXX
353 */
354
355/* may need to put some structures here.  */
356
357/*
358 * Contexts
359 *
360 *  Generally there are 2 types of context to save.
361 *     1. Interrupt registers to save
362 *     2. Task level registers to save
363 *
364 *  This means we have the following 3 context items:
365 *     1. task level context stuff::  Context_Control
366 *     2. floating point task stuff:: Context_Control_fp
367 *     3. special interrupt level context :: Context_Control_interrupt
368 *
369 *  On some processors, it is cost-effective to save only the callee
370 *  preserved registers during a task context switch.  This means
371 *  that the ISR code needs to save those registers which do not
372 *  persist across function calls.  It is not mandatory to make this
373 *  distinctions between the caller/callee saves registers for the
374 *  purpose of minimizing context saved during task switch and on interrupts.
375 *  If the cost of saving extra registers is minimal, simplicity is the
376 *  choice.  Save the same context on interrupt entry as for tasks in
377 *  this case.
378 *
379 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
380 *  care should be used in designing the context area.
381 *
382 *  On some CPUs with hardware floating point support, the Context_Control_fp
383 *  structure will not be used or it simply consist of an array of a
384 *  fixed number of bytes.   This is done when the floating point context
385 *  is dumped by a "FP save context" type instruction and the format
386 *  is not really defined by the CPU.  In this case, there is no need
387 *  to figure out the exact format -- only the size.  Of course, although
388 *  this is enough information for RTEMS, it is probably not enough for
389 *  a debugger such as gdb.  But that is another problem.
390 *
391 *  H8300 Specific Information:
392 *
393 *  XXX
394 */
395
396#ifndef ASM
397
398typedef struct {
399  /* There is no CPU specific per-CPU state */
400} CPU_Per_CPU_control;
401
402#define nogap __attribute__ ((packed))
403
404typedef struct {
405    uint16_t    ccr nogap;
406    void        *er7 nogap;
407    void        *er6 nogap;
408    uint32_t    er5 nogap;
409    uint32_t    er4 nogap;
410    uint32_t    er3 nogap;
411    uint32_t    er2 nogap;
412    uint32_t    er1 nogap;
413    uint32_t    er0 nogap;
414    uint32_t    xxx nogap;
415} Context_Control;
416
417#define _CPU_Context_Get_SP( _context ) \
418  (_context)->er7
419
420typedef struct {
421    double      some_float_register[2];
422} Context_Control_fp;
423
424typedef struct {
425    uint32_t   special_interrupt_register;
426} CPU_Interrupt_frame;
427
428/*
429 *  This variable is optional.  It is used on CPUs on which it is difficult
430 *  to generate an "uninitialized" FP context.  It is filled in by
431 *  _CPU_Initialize and copied into the task's FP context area during
432 *  _CPU_Context_Initialize.
433 *
434 *  H8300 Specific Information:
435 *
436 *  XXX
437 */
438
439SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
440
441/*
442 *  Nothing prevents the porter from declaring more CPU specific variables.
443 *
444 *  H8300 Specific Information:
445 *
446 *  XXX
447 */
448
449/* XXX: if needed, put more variables here */
450
451/*
452 *  The size of the floating point context area.  On some CPUs this
453 *  will not be a "sizeof" because the format of the floating point
454 *  area is not defined -- only the size is.  This is usually on
455 *  CPUs with a "floating point save context" instruction.
456 *
457 *  H8300 Specific Information:
458 *
459 *  XXX
460 */
461
462#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
463
464#endif /* ASM */
465
466/*
467 *  Amount of extra stack (above minimum stack size) required by
468 *  system initialization thread.  Remember that in a multiprocessor
469 *  system the system intialization thread becomes the MP server thread.
470 *
471 *  H8300 Specific Information:
472 *
473 *  It is highly unlikely the H8300 will get used in a multiprocessor system.
474 */
475
476#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
477
478/*
479 *  This defines the number of entries in the ISR_Vector_table managed
480 *  by RTEMS.
481 *
482 *  H8300 Specific Information:
483 *
484 *  XXX
485 */
486
487#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
488#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
489
490/*
491 *  This is defined if the port has a special way to report the ISR nesting
492 *  level.  Most ports maintain the variable _ISR_Nest_level.
493 */
494
495#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
496
497/*
498 *  Should be large enough to run all RTEMS tests.  This ensures
499 *  that a "reasonable" small application should not have any problems.
500 *
501 *  H8300 Specific Information:
502 *
503 *  XXX
504 */
505
506#define CPU_STACK_MINIMUM_SIZE          (1536)
507
508#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
509  #define CPU_SIZEOF_POINTER 4
510#else
511  #define CPU_SIZEOF_POINTER 2
512#endif
513
514/*
515 *  CPU's worst alignment requirement for data types on a byte boundary.  This
516 *  alignment does not take into account the requirements for the stack.
517 *
518 *  H8300 Specific Information:
519 *
520 *  XXX
521 */
522
523#define CPU_ALIGNMENT              8
524
525/*
526 *  This number corresponds to the byte alignment requirement for the
527 *  heap handler.  This alignment requirement may be stricter than that
528 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
529 *  common for the heap to follow the same alignment requirement as
530 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
531 *  then this should be set to CPU_ALIGNMENT.
532 *
533 *  NOTE:  This does not have to be a power of 2.  It does have to
534 *         be greater or equal to than CPU_ALIGNMENT.
535 *
536 *  H8300 Specific Information:
537 *
538 *  XXX
539 */
540
541#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
542
543/*
544 *  This number corresponds to the byte alignment requirement for memory
545 *  buffers allocated by the partition manager.  This alignment requirement
546 *  may be stricter than that for the data types alignment specified by
547 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
548 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
549 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
550 *
551 *  NOTE:  This does not have to be a power of 2.  It does have to
552 *         be greater or equal to than CPU_ALIGNMENT.
553 *
554 *  H8300 Specific Information:
555 *
556 *  XXX
557 */
558
559#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
560
561/*
562 *  This number corresponds to the byte alignment requirement for the
563 *  stack.  This alignment requirement may be stricter than that for the
564 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
565 *  is strict enough for the stack, then this should be set to 0.
566 *
567 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
568 *
569 *  H8300 Specific Information:
570 *
571 *  XXX
572 */
573
574#define CPU_STACK_ALIGNMENT        2
575
576/*
577 *  ISR handler macros
578 */
579
580/*
581 *  Support routine to initialize the RTEMS vector table after it is allocated.
582 */
583
584#define _CPU_Initialize_vectors()
585
586/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
587   Note requires ISR_Level be uint16_t or assembler croaks.
588*/
589
590#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
591
592
593/*
594 *  Disable all interrupts for an RTEMS critical section.  The previous
595 *  level is returned in _level.
596 */
597
598#define _CPU_ISR_Disable( _isr_cookie ) \
599  do { \
600    __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
601  } while (0)
602
603
604/*
605 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
606 *  This indicates the end of an RTEMS critical section.  The parameter
607 *  _level is not modified.
608 */
609
610
611#define _CPU_ISR_Enable( _isr_cookie )  \
612  do { \
613    __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
614  } while (0)
615
616
617/*
618 *  This temporarily restores the interrupt to _level before immediately
619 *  disabling them again.  This is used to divide long RTEMS critical
620 *  sections into two or more parts.  The parameter _level is not
621 * modified.
622 */
623
624
625#define _CPU_ISR_Flash( _isr_cookie ) \
626  do { \
627    __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
628  } while (0)
629
630/* end of ISR handler macros */
631
632#else /* modern gcc version */
633
634/*
635 *  Disable all interrupts for an RTEMS critical section.  The previous
636 *  level is returned in _level.
637 *
638 *  H8300 Specific Information:
639 *
640 *  XXX
641 */
642
643#if defined(__H8300H__) || defined(__H8300S__)
644#define _CPU_ISR_Disable( _isr_cookie ) \
645  do { \
646    unsigned char __ccr; \
647    __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \
648             : "=m" (__ccr) /* : "0" (__ccr) */ ); \
649    (_isr_cookie) = __ccr; \
650  } while (0)
651#else
652#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
653#endif
654
655
656/*
657 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
658 *  This indicates the end of an RTEMS critical section.  The parameter
659 *  _level is not modified.
660 *
661 *  H8300 Specific Information:
662 *
663 *  XXX
664 */
665
666#if defined(__H8300H__) || defined(__H8300S__)
667#define _CPU_ISR_Enable( _isr_cookie )  \
668  do { \
669    unsigned char __ccr = (unsigned char) (_isr_cookie); \
670    __asm__ volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
671  } while (0)
672#else
673#define _CPU_ISR_Enable( _isr_cookie )
674#endif
675
676/*
677 *  This temporarily restores the interrupt to _level before immediately
678 *  disabling them again.  This is used to divide long RTEMS critical
679 *  sections into two or more parts.  The parameter _level is not
680 *  modified.
681 *
682 *  H8300 Specific Information:
683 *
684 *  XXX
685 */
686
687#if defined(__H8300H__) || defined(__H8300S__)
688#define _CPU_ISR_Flash( _isr_cookie ) \
689  do { \
690    unsigned char __ccr = (unsigned char) (_isr_cookie); \
691    __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
692  } while (0)
693#else
694#define _CPU_ISR_Flash( _isr_cookie )
695#endif
696
697#endif /* end of old gcc */
698
699
700/*
701 *  Map interrupt level in task mode onto the hardware that the CPU
702 *  actually provides.  Currently, interrupt levels which do not
703 *  map onto the CPU in a generic fashion are undefined.  Someday,
704 *  it would be nice if these were "mapped" by the application
705 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
706 *  8 - 255 would be available for bsp/application specific meaning.
707 *  This could be used to manage a programmable interrupt controller
708 *  via the rtems_task_mode directive.
709 *
710 *  H8300 Specific Information:
711 *
712 *  XXX
713 */
714
715#define _CPU_ISR_Set_level( _new_level ) \
716  { \
717    if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \
718    else              __asm__ volatile ( "andc #0x7f,ccr\n" ); \
719  }
720
721#ifndef ASM
722
723uint32_t   _CPU_ISR_Get_level( void );
724
725/* end of ISR handler macros */
726
727/* Context handler macros */
728
729/*
730 *  Initialize the context to a state suitable for starting a
731 *  task after a context restore operation.  Generally, this
732 *  involves:
733 *
734 *     - setting a starting address
735 *     - preparing the stack
736 *     - preparing the stack and frame pointers
737 *     - setting the proper interrupt level in the context
738 *     - initializing the floating point context
739 *
740 *  This routine generally does not set any unnecessary register
741 *  in the context.  The state of the "general data" registers is
742 *  undefined at task start time.
743 *
744 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
745 *        point thread.  This is typically only used on CPUs where the
746 *        FPU may be easily disabled by software such as on the SPARC
747 *        where the PSR contains an enable FPU bit.
748 *
749 *  H8300 Specific Information:
750 *
751 *  XXX
752 */
753
754
755#define CPU_CCR_INTERRUPTS_ON  0x80
756#define CPU_CCR_INTERRUPTS_OFF 0x00
757
758#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
759                                   _isr, _entry_point, _is_fp, _tls_area ) \
760  /* Locate Me */ \
761  do { \
762    uintptr_t   _stack; \
763    \
764    if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
765    else          (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
766    \
767    _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \
768    *((proc_ptr *)(_stack)) = (_entry_point); \
769     (_the_context)->er7     = (void *) _stack; \
770     (_the_context)->er6     = (void *) _stack; \
771     (_the_context)->er5     = 0; \
772     (_the_context)->er4     = 1; \
773     (_the_context)->er3     = 2; \
774  } while (0)
775
776
777/*
778 *  This routine is responsible for somehow restarting the currently
779 *  executing task.  If you are lucky, then all that is necessary
780 *  is restoring the context.  Otherwise, there will need to be
781 *  a special assembly routine which does something special in this
782 *  case.  Context_Restore should work most of the time.  It will
783 *  not work if restarting self conflicts with the stack frame
784 *  assumptions of restoring a context.
785 *
786 *  H8300 Specific Information:
787 *
788 *  XXX
789 */
790
791#define _CPU_Context_Restart_self( _the_context ) \
792   _CPU_Context_restore( (_the_context) );
793
794/*
795 *  The purpose of this macro is to allow the initial pointer into
796 *  a floating point context area (used to save the floating point
797 *  context) to be at an arbitrary place in the floating point
798 *  context area.
799 *
800 *  This is necessary because some FP units are designed to have
801 *  their context saved as a stack which grows into lower addresses.
802 *  Other FP units can be saved by simply moving registers into offsets
803 *  from the base of the context area.  Finally some FP units provide
804 *  a "dump context" instruction which could fill in from high to low
805 *  or low to high based on the whim of the CPU designers.
806 *
807 *  H8300 Specific Information:
808 *
809 *  XXX
810 */
811
812#define _CPU_Context_Fp_start( _base, _offset ) \
813   ( (void *) (_base) + (_offset) )
814
815/*
816 *  This routine initializes the FP context area passed to it to.
817 *  There are a few standard ways in which to initialize the
818 *  floating point context.  The code included for this macro assumes
819 *  that this is a CPU in which a "initial" FP context was saved into
820 *  _CPU_Null_fp_context and it simply copies it to the destination
821 *  context passed to it.
822 *
823 *  Other models include (1) not doing anything, and (2) putting
824 *  a "null FP status word" in the correct place in the FP context.
825 *
826 *  H8300 Specific Information:
827 *
828 *  XXX
829 */
830
831#define _CPU_Context_Initialize_fp( _destination ) \
832  { \
833   *(*(_destination)) = _CPU_Null_fp_context; \
834  }
835
836/* end of Context handler macros */
837
838/* Fatal Error manager macros */
839
840/*
841 *  This routine copies _error into a known place -- typically a stack
842 *  location or a register, optionally disables interrupts, and
843 *  halts/stops the CPU.
844 *
845 *  H8300 Specific Information:
846 *
847 *  XXX
848 */
849
850#define _CPU_Fatal_halt( _source, _error ) \
851        printk("Fatal Error %d.%d Halted\n",_source, _error); \
852        for(;;)
853
854
855/* end of Fatal Error manager macros */
856
857/* Bitfield handler macros */
858
859/*
860 *  This routine sets _output to the bit number of the first bit
861 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
862 *  This type may be either 16 or 32 bits wide although only the 16
863 *  least significant bits will be used.
864 *
865 *  There are a number of variables in using a "find first bit" type
866 *  instruction.
867 *
868 *    (1) What happens when run on a value of zero?
869 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
870 *    (3) The numbering may be zero or one based.
871 *    (4) The "find first bit" instruction may search from MSB or LSB.
872 *
873 *  RTEMS guarantees that (1) will never happen so it is not a concern.
874 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
875 *  _CPU_Priority_bits_index().  These three form a set of routines
876 *  which must logically operate together.  Bits in the _value are
877 *  set and cleared based on masks built by _CPU_Priority_mask().
878 *  The basic major and minor values calculated by _Priority_Major()
879 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
880 *  to properly range between the values returned by the "find first bit"
881 *  instruction.  This makes it possible for _Priority_Get_highest() to
882 *  calculate the major and directly index into the minor table.
883 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
884 *  is the first bit found.
885 *
886 *  This entire "find first bit" and mapping process depends heavily
887 *  on the manner in which a priority is broken into a major and minor
888 *  components with the major being the 4 MSB of a priority and minor
889 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
890 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
891 *  to the lowest priority.
892 *
893 *  If your CPU does not have a "find first bit" instruction, then
894 *  there are ways to make do without it.  Here are a handful of ways
895 *  to implement this in software:
896 *
897 *    - a series of 16 bit test instructions
898 *    - a "binary search using if's"
899 *    - _number = 0
900 *      if _value > 0x00ff
901 *        _value >>=8
902 *        _number = 8;
903 *
904 *      if _value > 0x0000f
905 *        _value >=8
906 *        _number += 4
907 *
908 *      _number += bit_set_table[ _value ]
909 *
910 *    where bit_set_table[ 16 ] has values which indicate the first
911 *      bit set
912 *
913 *  H8300 Specific Information:
914 *
915 *  XXX
916 */
917
918#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
919#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
920
921#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
922
923#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
924  { \
925    (_output) = 0;   /* do something to prevent warnings */ \
926  }
927
928#endif
929
930/* end of Bitfield handler macros */
931
932/*
933 *  This routine builds the mask which corresponds to the bit fields
934 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
935 *  for that routine.
936 *
937 *  H8300 Specific Information:
938 *
939 *  XXX
940 */
941
942#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
943
944#define _CPU_Priority_Mask( _bit_number ) \
945  ( 1 << (_bit_number) )
946
947#endif
948
949/*
950 *  This routine translates the bit numbers returned by
951 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
952 *  a major or minor component of a priority.  See the discussion
953 *  for that routine.
954 *
955 *  H8300 Specific Information:
956 *
957 *  XXX
958 */
959
960#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
961
962#define _CPU_Priority_bits_index( _priority ) \
963  (_priority)
964
965#endif
966
967/* end of Priority handler macros */
968
969/* functions */
970
971/*
972 *  _CPU_Initialize
973 *
974 *  This routine performs CPU dependent initialization.
975 *
976 *  H8300 Specific Information:
977 *
978 *  XXX
979 */
980
981void _CPU_Initialize(void);
982
983/*
984 *  _CPU_ISR_install_raw_handler
985 *
986 *  This routine installs a "raw" interrupt handler directly into the
987 *  processor's vector table.
988 *
989 *  H8300 Specific Information:
990 *
991 *  XXX
992 */
993
994void _CPU_ISR_install_raw_handler(
995  uint32_t    vector,
996  proc_ptr    new_handler,
997  proc_ptr   *old_handler
998);
999
1000/*
1001 *  _CPU_ISR_install_vector
1002 *
1003 *  This routine installs an interrupt vector.
1004 *
1005 *  H8300 Specific Information:
1006 *
1007 *  XXX
1008 */
1009
1010void _CPU_ISR_install_vector(
1011  uint32_t    vector,
1012  proc_ptr    new_handler,
1013  proc_ptr   *old_handler
1014);
1015
1016/*
1017 *  _CPU_Install_interrupt_stack
1018 *
1019 *  This routine installs the hardware interrupt stack pointer.
1020 *
1021 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1022 *         is TRUE.
1023 *
1024 *  H8300 Specific Information:
1025 *
1026 *  XXX
1027 */
1028
1029void _CPU_Install_interrupt_stack( void );
1030
1031/*
1032 *  _CPU_Internal_threads_Idle_thread_body
1033 *
1034 *  This routine is the CPU dependent IDLE thread body.
1035 *
1036 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1037 *         is TRUE.
1038 *
1039 *  H8300 Specific Information:
1040 *
1041 *  XXX
1042 */
1043
1044void *_CPU_Thread_Idle_body( uint32_t );
1045
1046/*
1047 *  _CPU_Context_switch
1048 *
1049 *  This routine switches from the run context to the heir context.
1050 *
1051 *  H8300 Specific Information:
1052 *
1053 *  XXX
1054 */
1055
1056void _CPU_Context_switch(
1057  Context_Control  *run,
1058  Context_Control  *heir
1059);
1060
1061/*
1062 *  _CPU_Context_restore
1063 *
1064 *  This routine is generallu used only to restart self in an
1065 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1066 *
1067 *  NOTE: May be unnecessary to reload some registers.
1068 *
1069 *  H8300 Specific Information:
1070 *
1071 *  XXX
1072 */
1073
1074void _CPU_Context_restore(
1075  Context_Control *new_context
1076) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1077
1078/*
1079 *  _CPU_Context_save_fp
1080 *
1081 *  This routine saves the floating point context passed to it.
1082 *
1083 *  H8300 Specific Information:
1084 *
1085 *  XXX
1086 */
1087
1088void _CPU_Context_save_fp(
1089  Context_Control_fp **fp_context_ptr
1090);
1091
1092/*
1093 *  _CPU_Context_restore_fp
1094 *
1095 *  This routine restores the floating point context passed to it.
1096 *
1097 *  H8300 Specific Information:
1098 *
1099 *  XXX
1100 */
1101
1102void _CPU_Context_restore_fp(
1103  Context_Control_fp **fp_context_ptr
1104);
1105
1106static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1107{
1108  /* TODO */
1109}
1110
1111static inline void _CPU_Context_validate( uintptr_t pattern )
1112{
1113  while (1) {
1114    /* TODO */
1115  }
1116}
1117
1118/* FIXME */
1119typedef CPU_Interrupt_frame CPU_Exception_frame;
1120
1121void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1122
1123/*  The following routine swaps the endian format of an unsigned int.
1124 *  It must be static because it is referenced indirectly.
1125 *
1126 *  This version will work on any processor, but if there is a better
1127 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1128 *
1129 *     swap least significant two bytes with 16-bit rotate
1130 *     swap upper and lower 16-bits
1131 *     swap most significant two bytes with 16-bit rotate
1132 *
1133 *  Some CPUs have special instructions which swap a 32-bit quantity in
1134 *  a single instruction (e.g. i486).  It is probably best to avoid
1135 *  an "endian swapping control bit" in the CPU.  One good reason is
1136 *  that interrupts would probably have to be disabled to ensure that
1137 *  an interrupt does not try to access the same "chunk" with the wrong
1138 *  endian.  Another good reason is that on some CPUs, the endian bit
1139 *  endianness for ALL fetches -- both code and data -- so the code
1140 *  will be fetched incorrectly.
1141 *
1142 *  H8300 Specific Information:
1143 *
1144 *  This is the generic implementation.
1145 */
1146
1147static inline uint32_t   CPU_swap_u32(
1148  uint32_t   value
1149)
1150{
1151  uint32_t   byte1, byte2, byte3, byte4, swapped;
1152
1153  byte4 = (value >> 24) & 0xff;
1154  byte3 = (value >> 16) & 0xff;
1155  byte2 = (value >> 8)  & 0xff;
1156  byte1 =  value        & 0xff;
1157
1158  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1159  return( swapped );
1160}
1161
1162#define CPU_swap_u16( value ) \
1163  (((value&0xff) << 8) | ((value >> 8)&0xff))
1164
1165typedef uint32_t CPU_Counter_ticks;
1166
1167CPU_Counter_ticks _CPU_Counter_read( void );
1168
1169static inline CPU_Counter_ticks _CPU_Counter_difference(
1170  CPU_Counter_ticks second,
1171  CPU_Counter_ticks first
1172)
1173{
1174  return second - first;
1175}
1176
1177/* to be provided by the BSP */
1178extern void H8BD_Install_IRQ(
1179  uint32_t      vector,
1180  proc_ptr      new_handler,
1181  proc_ptr      *old_handler );
1182
1183#endif /* ASM */
1184
1185#ifdef __cplusplus
1186}
1187#endif
1188
1189#endif
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