source: rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h @ eba52fd3

4.104.114.84.95
Last change on this file since eba52fd3 was eba52fd3, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 30, 2006 at 5:16:50 PM

2006-08-30 Joel Sherrill <joel@…>

  • rtems/score/cpu.h:
  • Property mode set to 100644
File size: 33.4 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the H8300
7 *  processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/h8300.h>               /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31#include <rtems/bspIo.h>        /* printk */
32
33/* conditional compilation parameters */
34
35/*
36 *  Should the calls to _Thread_Enable_dispatch be inlined?
37 *
38 *  If TRUE, then they are inlined.
39 *  If FALSE, then a subroutine call is made.
40 *
41 *  Basically this is an example of the classic trade-off of size
42 *  versus speed.  Inlining the call (TRUE) typically increases the
43 *  size of RTEMS while speeding up the enabling of dispatching.
44 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
45 *  only be 0 or 1 unless you are in an interrupt handler and that
46 *  interrupt handler invokes the executive.]  When not inlined
47 *  something calls _Thread_Enable_dispatch which in turns calls
48 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
49 *  one subroutine call is avoided entirely.]
50 *
51 *  H8300 Specific Information:
52 *
53 *  XXX
54 */
55
56#define CPU_INLINE_ENABLE_DISPATCH       FALSE
57
58/*
59 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
60 *  be unrolled one time?  In unrolled each iteration of the loop examines
61 *  two "nodes" on the chain being searched.  Otherwise, only one node
62 *  is examined per iteration.
63 *
64 *  If TRUE, then the loops are unrolled.
65 *  If FALSE, then the loops are not unrolled.
66 *
67 *  The primary factor in making this decision is the cost of disabling
68 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
69 *  body of the loop.  On some CPUs, the flash is more expensive than
70 *  one iteration of the loop body.  In this case, it might be desirable
71 *  to unroll the loop.  It is important to note that on some CPUs, this
72 *  code is the longest interrupt disable period in RTEMS.  So it is
73 *  necessary to strike a balance when setting this parameter.
74 *
75 *  H8300 Specific Information:
76 *
77 *  XXX
78 */
79
80#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
81
82/*
83 *  Does RTEMS manage a dedicated interrupt stack in software?
84 *
85 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
86 *  If FALSE, nothing is done.
87 *
88 *  If the CPU supports a dedicated interrupt stack in hardware,
89 *  then it is generally the responsibility of the BSP to allocate it
90 *  and set it up.
91 *
92 *  If the CPU does not support a dedicated interrupt stack, then
93 *  the porter has two options: (1) execute interrupts on the
94 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
95 *  interrupt stack.
96 *
97 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
98 *
99 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
100 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
101 *  possible that both are FALSE for a particular CPU.  Although it
102 *  is unclear what that would imply about the interrupt processing
103 *  procedure on that CPU.
104 *
105 *  H8300 Specific Information:
106 *
107 *  XXX
108 */
109
110#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
111
112/*
113 *  Does this CPU have hardware support for a dedicated interrupt stack?
114 *
115 *  If TRUE, then it must be installed during initialization.
116 *  If FALSE, then no installation is performed.
117 *
118 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
119 *
120 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
121 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
122 *  possible that both are FALSE for a particular CPU.  Although it
123 *  is unclear what that would imply about the interrupt processing
124 *  procedure on that CPU.
125 *
126 *  H8300 Specific Information:
127 *
128 *  XXX
129 */
130
131#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
132
133/*
134 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
135 *
136 *  If TRUE, then the memory is allocated during initialization.
137 *  If FALSE, then the memory is allocated during initialization.
138 *
139 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
140 *
141 *  H8300 Specific Information:
142 *
143 *  XXX
144 */
145
146#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
147
148/*
149 *  Does the CPU have hardware floating point?
150 *
151 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
152 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
153 *
154 *  If there is a FP coprocessor such as the i387 or mc68881, then
155 *  the answer is TRUE.
156 *
157 *  The macro name "H8300_HAS_FPU" should be made CPU specific.
158 *  It indicates whether or not this CPU model has FP support.  For
159 *  example, it would be possible to have an i386_nofp CPU model
160 *  which set this to false to indicate that you have an i386 without
161 *  an i387 and wish to leave floating point support out of RTEMS.
162 *
163 *  H8300 Specific Information:
164 *
165 *  XXX
166 */
167
168#define CPU_HARDWARE_FP     FALSE
169
170/*
171 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
172 *
173 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
174 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
175 *
176 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
177 *
178 *  H8300 Specific Information:
179 *
180 *  XXX
181 */
182
183#define CPU_ALL_TASKS_ARE_FP     FALSE
184
185/*
186 *  Should the IDLE task have a floating point context?
187 *
188 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
189 *  and it has a floating point context which is switched in and out.
190 *  If FALSE, then the IDLE task does not have a floating point context.
191 *
192 *  Setting this to TRUE negatively impacts the time required to preempt
193 *  the IDLE task from an interrupt because the floating point context
194 *  must be saved as part of the preemption.
195 *
196 *  H8300 Specific Information:
197 *
198 *  XXX
199 */
200
201#define CPU_IDLE_TASK_IS_FP      FALSE
202
203/*
204 *  Should the saving of the floating point registers be deferred
205 *  until a context switch is made to another different floating point
206 *  task?
207 *
208 *  If TRUE, then the floating point context will not be stored until
209 *  necessary.  It will remain in the floating point registers and not
210 *  disturned until another floating point task is switched to.
211 *
212 *  If FALSE, then the floating point context is saved when a floating
213 *  point task is switched out and restored when the next floating point
214 *  task is restored.  The state of the floating point registers between
215 *  those two operations is not specified.
216 *
217 *  If the floating point context does NOT have to be saved as part of
218 *  interrupt dispatching, then it should be safe to set this to TRUE.
219 *
220 *  Setting this flag to TRUE results in using a different algorithm
221 *  for deciding when to save and restore the floating point context.
222 *  The deferred FP switch algorithm minimizes the number of times
223 *  the FP context is saved and restored.  The FP context is not saved
224 *  until a context switch is made to another, different FP task.
225 *  Thus in a system with only one FP task, the FP context will never
226 *  be saved or restored.
227 *
228 *  H8300 Specific Information:
229 *
230 *  XXX
231 */
232
233#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
234
235/*
236 *  Does this port provide a CPU dependent IDLE task implementation?
237 *
238 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
239 *  must be provided and is the default IDLE thread body instead of
240 *  _Internal_threads_Idle_thread_body.
241 *
242 *  If FALSE, then use the generic IDLE thread body if the BSP does
243 *  not provide one.
244 *
245 *  This is intended to allow for supporting processors which have
246 *  a low power or idle mode.  When the IDLE thread is executed, then
247 *  the CPU can be powered down.
248 *
249 *  The order of precedence for selecting the IDLE thread body is:
250 *
251 *    1.  BSP provided
252 *    2.  CPU dependent (if provided)
253 *    3.  generic (if no BSP and no CPU dependent)
254 *
255 *  H8300 Specific Information:
256 *
257 *  XXX
258 *  The port initially called a BSP dependent routine called
259 *  IDLE_Monitor.  The idle task body can be overridden by
260 *  the BSP in newer versions of RTEMS.
261 */
262
263#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
264
265/*
266 *  Does the stack grow up (toward higher addresses) or down
267 *  (toward lower addresses)?
268 *
269 *  If TRUE, then the grows upward.
270 *  If FALSE, then the grows toward smaller addresses.
271 *
272 *  H8300 Specific Information:
273 *
274 *  XXX
275 */
276
277#define CPU_STACK_GROWS_UP               FALSE
278
279/*
280 *  The following is the variable attribute used to force alignment
281 *  of critical RTEMS structures.  On some processors it may make
282 *  sense to have these aligned on tighter boundaries than
283 *  the minimum requirements of the compiler in order to have as
284 *  much of the critical data area as possible in a cache line.
285 *
286 *  The placement of this macro in the declaration of the variables
287 *  is based on the syntactically requirements of the GNU C
288 *  "__attribute__" extension.  For example with GNU C, use
289 *  the following to force a structures to a 32 byte boundary.
290 *
291 *      __attribute__ ((aligned (32)))
292 *
293 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
294 *         To benefit from using this, the data must be heavily
295 *         used so it will stay in the cache and used frequently enough
296 *         in the executive to justify turning this on.
297 *
298 *  H8300 Specific Information:
299 *
300 *  XXX
301 */
302
303#define CPU_STRUCTURE_ALIGNMENT
304
305/*
306 *  Define what is required to specify how the network to host conversion
307 *  routines are handled.
308 */
309
310#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
311#define CPU_BIG_ENDIAN                           TRUE
312#define CPU_LITTLE_ENDIAN                        FALSE
313
314/*
315 *  The following defines the number of bits actually used in the
316 *  interrupt field of the task mode.  How those bits map to the
317 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
318 *
319 *  H8300 Specific Information:
320 *
321 *  XXX
322 */
323
324#define CPU_MODES_INTERRUPT_MASK   0x00000001
325
326/*
327 *  Processor defined structures required for cpukit/score.
328 *
329 *  H8300 Specific Information:
330 *
331 *  XXX
332 */
333
334/* may need to put some structures here.  */
335
336/*
337 * Contexts
338 *
339 *  Generally there are 2 types of context to save.
340 *     1. Interrupt registers to save
341 *     2. Task level registers to save
342 *
343 *  This means we have the following 3 context items:
344 *     1. task level context stuff::  Context_Control
345 *     2. floating point task stuff:: Context_Control_fp
346 *     3. special interrupt level context :: Context_Control_interrupt
347 *
348 *  On some processors, it is cost-effective to save only the callee
349 *  preserved registers during a task context switch.  This means
350 *  that the ISR code needs to save those registers which do not
351 *  persist across function calls.  It is not mandatory to make this
352 *  distinctions between the caller/callee saves registers for the
353 *  purpose of minimizing context saved during task switch and on interrupts.
354 *  If the cost of saving extra registers is minimal, simplicity is the
355 *  choice.  Save the same context on interrupt entry as for tasks in
356 *  this case.
357 *
358 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
359 *  care should be used in designing the context area.
360 *
361 *  On some CPUs with hardware floating point support, the Context_Control_fp
362 *  structure will not be used or it simply consist of an array of a
363 *  fixed number of bytes.   This is done when the floating point context
364 *  is dumped by a "FP save context" type instruction and the format
365 *  is not really defined by the CPU.  In this case, there is no need
366 *  to figure out the exact format -- only the size.  Of course, although
367 *  this is enough information for RTEMS, it is probably not enough for
368 *  a debugger such as gdb.  But that is another problem.
369 *
370 *  H8300 Specific Information:
371 *
372 *  XXX
373 */
374
375
376
377#define nogap __attribute__ ((packed))
378
379typedef struct {
380    uint16_t    ccr nogap;
381    void        *er7 nogap;
382    void        *er6 nogap;
383    uint32_t    er5 nogap;
384    uint32_t    er4 nogap;
385    uint32_t    er3 nogap;
386    uint32_t    er2 nogap;
387    uint32_t    er1 nogap;
388    uint32_t    er0 nogap;
389    uint32_t    xxx nogap;
390} Context_Control;
391
392typedef struct {
393    double      some_float_register[2];
394} Context_Control_fp;
395
396typedef struct {
397    uint32_t   special_interrupt_register;
398} CPU_Interrupt_frame;
399
400
401/*
402 *  The following table contains the information required to configure
403 *  the XXX processor specific parameters.
404 *
405 *  NOTE: The interrupt_stack_size field is required if
406 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
407 *
408 *        The pretasking_hook, predriver_hook, and postdriver_hook,
409 *        and the do_zero_of_workspace fields are required on ALL CPUs.
410 *
411 *  H8300 Specific Information:
412 *
413 *  XXX
414 */
415
416typedef struct {
417  void       (*pretasking_hook)( void );
418  void       (*predriver_hook)( void );
419  void       (*postdriver_hook)( void );
420  void       (*idle_task)( void );
421  boolean      do_zero_of_workspace;
422  uint32_t     idle_task_stack_size;
423  uint32_t     interrupt_stack_size;
424  uint32_t     extra_mpci_receive_server_stack;
425  void *     (*stack_allocate_hook)( uint32_t   );
426  void       (*stack_free_hook)( void* );
427}   rtems_cpu_table;
428
429/*
430 *  This variable is optional.  It is used on CPUs on which it is difficult
431 *  to generate an "uninitialized" FP context.  It is filled in by
432 *  _CPU_Initialize and copied into the task's FP context area during
433 *  _CPU_Context_Initialize.
434 *
435 *  H8300 Specific Information:
436 *
437 *  XXX
438 */
439
440SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
441
442/*
443 *  On some CPUs, RTEMS supports a software managed interrupt stack.
444 *  This stack is allocated by the Interrupt Manager and the switch
445 *  is performed in _ISR_Handler.  These variables contain pointers
446 *  to the lowest and highest addresses in the chunk of memory allocated
447 *  for the interrupt stack.  Since it is unknown whether the stack
448 *  grows up or down (in general), this give the CPU dependent
449 *  code the option of picking the version it wants to use.
450 *
451 *  NOTE: These two variables are required if the macro
452 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
453 *
454 *  H8300 Specific Information:
455 *
456 *  XXX
457 */
458
459SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
460SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
461
462/*
463 *  With some compilation systems, it is difficult if not impossible to
464 *  call a high-level language routine from assembly language.  This
465 *  is especially true of commercial Ada compilers and name mangling
466 *  C++ ones.  This variable can be optionally defined by the CPU porter
467 *  and contains the address of the routine _Thread_Dispatch.  This
468 *  can make it easier to invoke that routine at the end of the interrupt
469 *  sequence (if a dispatch is necessary).
470 *
471 *  H8300 Specific Information:
472 *
473 *  XXX
474 */
475
476SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
477
478/*
479 *  Nothing prevents the porter from declaring more CPU specific variables.
480 *
481 *  H8300 Specific Information:
482 *
483 *  XXX
484 */
485
486/* XXX: if needed, put more variables here */
487
488/*
489 *  The size of the floating point context area.  On some CPUs this
490 *  will not be a "sizeof" because the format of the floating point
491 *  area is not defined -- only the size is.  This is usually on
492 *  CPUs with a "floating point save context" instruction.
493 *
494 *  H8300 Specific Information:
495 *
496 *  XXX
497 */
498
499#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
500
501/*
502 *  Amount of extra stack (above minimum stack size) required by
503 *  system initialization thread.  Remember that in a multiprocessor
504 *  system the system intialization thread becomes the MP server thread.
505 *
506 *  H8300 Specific Information:
507 *
508 *  It is highly unlikely the H8300 will get used in a multiprocessor system.
509 */
510
511#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
512
513/*
514 *  This defines the number of entries in the ISR_Vector_table managed
515 *  by RTEMS.
516 *
517 *  H8300 Specific Information:
518 *
519 *  XXX
520 */
521
522#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
523#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
524
525/*
526 *  This is defined if the port has a special way to report the ISR nesting
527 *  level.  Most ports maintain the variable _ISR_Nest_level.
528 */
529
530#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
531
532/*
533 *  Should be large enough to run all RTEMS tests.  This ensures
534 *  that a "reasonable" small application should not have any problems.
535 *
536 *  H8300 Specific Information:
537 *
538 *  XXX
539 */
540
541#define CPU_STACK_MINIMUM_SIZE          (1536)
542
543/*
544 *  CPU's worst alignment requirement for data types on a byte boundary.  This
545 *  alignment does not take into account the requirements for the stack.
546 *
547 *  H8300 Specific Information:
548 *
549 *  XXX
550 */
551
552#define CPU_ALIGNMENT              8
553
554/*
555 *  This number corresponds to the byte alignment requirement for the
556 *  heap handler.  This alignment requirement may be stricter than that
557 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
558 *  common for the heap to follow the same alignment requirement as
559 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
560 *  then this should be set to CPU_ALIGNMENT.
561 *
562 *  NOTE:  This does not have to be a power of 2.  It does have to
563 *         be greater or equal to than CPU_ALIGNMENT.
564 *
565 *  H8300 Specific Information:
566 *
567 *  XXX
568 */
569
570#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
571
572/*
573 *  This number corresponds to the byte alignment requirement for memory
574 *  buffers allocated by the partition manager.  This alignment requirement
575 *  may be stricter than that for the data types alignment specified by
576 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
577 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
578 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
579 *
580 *  NOTE:  This does not have to be a power of 2.  It does have to
581 *         be greater or equal to than CPU_ALIGNMENT.
582 *
583 *  H8300 Specific Information:
584 *
585 *  XXX
586 */
587
588#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
589
590/*
591 *  This number corresponds to the byte alignment requirement for the
592 *  stack.  This alignment requirement may be stricter than that for the
593 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
594 *  is strict enough for the stack, then this should be set to 0.
595 *
596 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
597 *
598 *  H8300 Specific Information:
599 *
600 *  XXX
601 */
602
603#define CPU_STACK_ALIGNMENT        2
604
605/*
606 *  ISR handler macros
607 */
608
609/*
610 *  Support routine to initialize the RTEMS vector table after it is allocated.
611 */
612
613#define _CPU_Initialize_vectors()
614
615/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
616   Note requires ISR_Level be uint16_t or assembler croaks.
617*/
618
619#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
620
621
622/*
623 *  Disable all interrupts for an RTEMS critical section.  The previous
624 *  level is returned in _level.
625 */
626
627#define _CPU_ISR_Disable( _isr_cookie ) \
628  do { \
629    _isr_cookie = 0; /* to avoid warnings */; \
630    asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  "=r" (_isr_cookie) : ); \
631  } while (0)
632
633
634/*
635 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
636 *  This indicates the end of an RTEMS critical section.  The parameter
637 *  _level is not modified.
638 */
639
640
641#define _CPU_ISR_Enable( _isr_cookie )  \
642  do { \
643    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
644  } while (0)
645
646
647/*
648 *  This temporarily restores the interrupt to _level before immediately
649 *  disabling them again.  This is used to divide long RTEMS critical
650 *  sections into two or more parts.  The parameter _level is not
651 * modified.
652 */
653
654
655#define _CPU_ISR_Flash( _isr_cookie ) \
656  do { \
657    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
658  } while (0)
659
660/* end of ISR handler macros */
661
662#else /* modern gcc version */
663
664/*
665 *  Disable all interrupts for an RTEMS critical section.  The previous
666 *  level is returned in _level.
667 *
668 *  H8300 Specific Information:
669 *
670 *  XXX 
671 */
672
673#if defined(__H8300H__) || defined(__H8300S__)
674#define _CPU_ISR_Disable( _isr_cookie ) \
675  do { \
676    unsigned char __ccr; \
677    asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \
678             : "=m" (__ccr) /* : "0" (__ccr) */ ); \
679    (_isr_cookie) = __ccr; \
680  } while (0)
681#else
682#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
683#endif
684
685
686/*
687 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
688 *  This indicates the end of an RTEMS critical section.  The parameter
689 *  _level is not modified.
690 *
691 *  H8300 Specific Information:
692 *
693 *  XXX
694 */
695
696#if defined(__H8300H__) || defined(__H8300S__)
697#define _CPU_ISR_Enable( _isr_cookie )  \
698  do { \
699    unsigned char __ccr = (unsigned char) (_isr_cookie); \
700    asm volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
701  } while (0)
702#else
703#define _CPU_ISR_Enable( _isr_cookie )
704#endif
705
706/*
707 *  This temporarily restores the interrupt to _level before immediately
708 *  disabling them again.  This is used to divide long RTEMS critical
709 *  sections into two or more parts.  The parameter _level is not
710 *  modified.
711 *
712 *  H8300 Specific Information:
713 *
714 *  XXX
715 */
716
717#if defined(__H8300H__) || defined(__H8300S__)
718#define _CPU_ISR_Flash( _isr_cookie ) \
719  do { \
720    unsigned char __ccr = (unsigned char) (_isr_cookie); \
721    asm volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
722  } while (0)
723#else
724#define _CPU_ISR_Flash( _isr_cookie )
725#endif
726
727#endif /* end of old gcc */
728
729
730/*
731 *  Map interrupt level in task mode onto the hardware that the CPU
732 *  actually provides.  Currently, interrupt levels which do not
733 *  map onto the CPU in a generic fashion are undefined.  Someday,
734 *  it would be nice if these were "mapped" by the application
735 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
736 *  8 - 255 would be available for bsp/application specific meaning.
737 *  This could be used to manage a programmable interrupt controller
738 *  via the rtems_task_mode directive.
739 *
740 *  H8300 Specific Information:
741 *
742 *  XXX
743 */
744
745#define _CPU_ISR_Set_level( _new_level ) \
746  { \
747    if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \
748    else              asm volatile ( "andc #0x7f,ccr\n" ); \
749  }
750
751uint32_t   _CPU_ISR_Get_level( void );
752
753/* end of ISR handler macros */
754
755/* Context handler macros */
756
757/*
758 *  Initialize the context to a state suitable for starting a
759 *  task after a context restore operation.  Generally, this
760 *  involves:
761 *
762 *     - setting a starting address
763 *     - preparing the stack
764 *     - preparing the stack and frame pointers
765 *     - setting the proper interrupt level in the context
766 *     - initializing the floating point context
767 *
768 *  This routine generally does not set any unnecessary register
769 *  in the context.  The state of the "general data" registers is
770 *  undefined at task start time.
771 *
772 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
773 *        point thread.  This is typically only used on CPUs where the
774 *        FPU may be easily disabled by software such as on the SPARC
775 *        where the PSR contains an enable FPU bit.
776 *
777 *  H8300 Specific Information:
778 *
779 *  XXX
780 */
781
782
783#define CPU_CCR_INTERRUPTS_ON  0x80
784#define CPU_CCR_INTERRUPTS_OFF 0x00
785
786#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
787                                   _isr, _entry_point, _is_fp ) \
788  /* Locate Me */ \
789  do { \
790    uint32_t   _stack; \
791    \
792    if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
793    else          (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
794    \
795    _stack = ((uint32_t  )(_stack_base)) + (_size) - 4; \
796    *((proc_ptr *)(_stack)) = (_entry_point); \
797     (_the_context)->er7     = (void *) _stack; \
798     (_the_context)->er6     = (void *) _stack; \
799     (_the_context)->er5     = 0; \
800     (_the_context)->er4     = 1; \
801     (_the_context)->er3     = 2; \
802  } while (0)
803
804
805/*
806 *  This routine is responsible for somehow restarting the currently
807 *  executing task.  If you are lucky, then all that is necessary
808 *  is restoring the context.  Otherwise, there will need to be
809 *  a special assembly routine which does something special in this
810 *  case.  Context_Restore should work most of the time.  It will
811 *  not work if restarting self conflicts with the stack frame
812 *  assumptions of restoring a context.
813 *
814 *  H8300 Specific Information:
815 *
816 *  XXX
817 */
818
819#define _CPU_Context_Restart_self( _the_context ) \
820   _CPU_Context_restore( (_the_context) );
821
822/*
823 *  The purpose of this macro is to allow the initial pointer into
824 *  a floating point context area (used to save the floating point
825 *  context) to be at an arbitrary place in the floating point
826 *  context area.
827 *
828 *  This is necessary because some FP units are designed to have
829 *  their context saved as a stack which grows into lower addresses.
830 *  Other FP units can be saved by simply moving registers into offsets
831 *  from the base of the context area.  Finally some FP units provide
832 *  a "dump context" instruction which could fill in from high to low
833 *  or low to high based on the whim of the CPU designers.
834 *
835 *  H8300 Specific Information:
836 *
837 *  XXX
838 */
839
840#define _CPU_Context_Fp_start( _base, _offset ) \
841   ( (void *) (_base) + (_offset) )
842
843/*
844 *  This routine initializes the FP context area passed to it to.
845 *  There are a few standard ways in which to initialize the
846 *  floating point context.  The code included for this macro assumes
847 *  that this is a CPU in which a "initial" FP context was saved into
848 *  _CPU_Null_fp_context and it simply copies it to the destination
849 *  context passed to it.
850 *
851 *  Other models include (1) not doing anything, and (2) putting
852 *  a "null FP status word" in the correct place in the FP context.
853 *
854 *  H8300 Specific Information:
855 *
856 *  XXX
857 */
858
859#define _CPU_Context_Initialize_fp( _destination ) \
860  { \
861   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
862  }
863
864/* end of Context handler macros */
865
866/* Fatal Error manager macros */
867
868/*
869 *  This routine copies _error into a known place -- typically a stack
870 *  location or a register, optionally disables interrupts, and
871 *  halts/stops the CPU.
872 *
873 *  H8300 Specific Information:
874 *
875 *  XXX
876 */
877
878#define _CPU_Fatal_halt( _error ) \
879        printk("Fatal Error %d Halted\n",_error); \
880        for(;;)
881 
882
883/* end of Fatal Error manager macros */
884
885/* Bitfield handler macros */
886
887/*
888 *  This routine sets _output to the bit number of the first bit
889 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
890 *  This type may be either 16 or 32 bits wide although only the 16
891 *  least significant bits will be used.
892 *
893 *  There are a number of variables in using a "find first bit" type
894 *  instruction.
895 *
896 *    (1) What happens when run on a value of zero?
897 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
898 *    (3) The numbering may be zero or one based.
899 *    (4) The "find first bit" instruction may search from MSB or LSB.
900 *
901 *  RTEMS guarantees that (1) will never happen so it is not a concern.
902 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
903 *  _CPU_Priority_bits_index().  These three form a set of routines
904 *  which must logically operate together.  Bits in the _value are
905 *  set and cleared based on masks built by _CPU_Priority_mask().
906 *  The basic major and minor values calculated by _Priority_Major()
907 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
908 *  to properly range between the values returned by the "find first bit"
909 *  instruction.  This makes it possible for _Priority_Get_highest() to
910 *  calculate the major and directly index into the minor table.
911 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
912 *  is the first bit found.
913 *
914 *  This entire "find first bit" and mapping process depends heavily
915 *  on the manner in which a priority is broken into a major and minor
916 *  components with the major being the 4 MSB of a priority and minor
917 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
918 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
919 *  to the lowest priority.
920 *
921 *  If your CPU does not have a "find first bit" instruction, then
922 *  there are ways to make do without it.  Here are a handful of ways
923 *  to implement this in software:
924 *
925 *    - a series of 16 bit test instructions
926 *    - a "binary search using if's"
927 *    - _number = 0
928 *      if _value > 0x00ff
929 *        _value >>=8
930 *        _number = 8;
931 *
932 *      if _value > 0x0000f
933 *        _value >=8
934 *        _number += 4
935 *
936 *      _number += bit_set_table[ _value ]
937 *
938 *    where bit_set_table[ 16 ] has values which indicate the first
939 *      bit set
940 *
941 *  H8300 Specific Information:
942 *
943 *  XXX
944 */
945
946#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
947#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
948
949#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
950
951#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
952  { \
953    (_output) = 0;   /* do something to prevent warnings */ \
954  }
955
956#endif
957
958/* end of Bitfield handler macros */
959
960/*
961 *  This routine builds the mask which corresponds to the bit fields
962 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
963 *  for that routine.
964 *
965 *  H8300 Specific Information:
966 *
967 *  XXX
968 */
969
970#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
971
972#define _CPU_Priority_Mask( _bit_number ) \
973  ( 1 << (_bit_number) )
974
975#endif
976
977/*
978 *  This routine translates the bit numbers returned by
979 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
980 *  a major or minor component of a priority.  See the discussion
981 *  for that routine.
982 *
983 *  H8300 Specific Information:
984 *
985 *  XXX
986 */
987
988#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
989
990#define _CPU_Priority_bits_index( _priority ) \
991  (_priority)
992
993#endif
994
995/* end of Priority handler macros */
996
997/* functions */
998
999/*
1000 *  _CPU_Initialize
1001 *
1002 *  This routine performs CPU dependent initialization.
1003 *
1004 *  H8300 Specific Information:
1005 *
1006 *  XXX
1007 */
1008
1009void _CPU_Initialize(
1010  rtems_cpu_table  *cpu_table,
1011  void      (*thread_dispatch)
1012);
1013
1014/*
1015 *  _CPU_ISR_install_raw_handler
1016 *
1017 *  This routine installs a "raw" interrupt handler directly into the
1018 *  processor's vector table.
1019 *
1020 *  H8300 Specific Information:
1021 *
1022 *  XXX
1023 */
1024 
1025void _CPU_ISR_install_raw_handler(
1026  uint32_t    vector,
1027  proc_ptr    new_handler,
1028  proc_ptr   *old_handler
1029);
1030
1031/*
1032 *  _CPU_ISR_install_vector
1033 *
1034 *  This routine installs an interrupt vector.
1035 *
1036 *  H8300 Specific Information:
1037 *
1038 *  XXX
1039 */
1040
1041void _CPU_ISR_install_vector(
1042  uint32_t    vector,
1043  proc_ptr    new_handler,
1044  proc_ptr   *old_handler
1045);
1046
1047/*
1048 *  _CPU_Install_interrupt_stack
1049 *
1050 *  This routine installs the hardware interrupt stack pointer.
1051 *
1052 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1053 *         is TRUE.
1054 *
1055 *  H8300 Specific Information:
1056 *
1057 *  XXX
1058 */
1059
1060void _CPU_Install_interrupt_stack( void );
1061
1062/*
1063 *  _CPU_Internal_threads_Idle_thread_body
1064 *
1065 *  This routine is the CPU dependent IDLE thread body.
1066 *
1067 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1068 *         is TRUE.
1069 *
1070 *  H8300 Specific Information:
1071 *
1072 *  XXX
1073 */
1074
1075void _CPU_Thread_Idle_body( void );
1076
1077/*
1078 *  _CPU_Context_switch
1079 *
1080 *  This routine switches from the run context to the heir context.
1081 *
1082 *  H8300 Specific Information:
1083 *
1084 *  XXX
1085 */
1086
1087void _CPU_Context_switch(
1088  Context_Control  *run,
1089  Context_Control  *heir
1090);
1091
1092/*
1093 *  _CPU_Context_restore
1094 *
1095 *  This routine is generallu used only to restart self in an
1096 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1097 *
1098 *  NOTE: May be unnecessary to reload some registers.
1099 *
1100 *  H8300 Specific Information:
1101 *
1102 *  XXX
1103 */
1104
1105void _CPU_Context_restore(
1106  Context_Control *new_context
1107);
1108
1109/*
1110 *  _CPU_Context_save_fp
1111 *
1112 *  This routine saves the floating point context passed to it.
1113 *
1114 *  H8300 Specific Information:
1115 *
1116 *  XXX
1117 */
1118
1119void _CPU_Context_save_fp(
1120  void **fp_context_ptr
1121);
1122
1123/*
1124 *  _CPU_Context_restore_fp
1125 *
1126 *  This routine restores the floating point context passed to it.
1127 *
1128 *  H8300 Specific Information:
1129 *
1130 *  XXX
1131 */
1132
1133void _CPU_Context_restore_fp(
1134  void **fp_context_ptr
1135);
1136
1137/*  The following routine swaps the endian format of an unsigned int.
1138 *  It must be static because it is referenced indirectly.
1139 *
1140 *  This version will work on any processor, but if there is a better
1141 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1142 *
1143 *     swap least significant two bytes with 16-bit rotate
1144 *     swap upper and lower 16-bits
1145 *     swap most significant two bytes with 16-bit rotate
1146 *
1147 *  Some CPUs have special instructions which swap a 32-bit quantity in
1148 *  a single instruction (e.g. i486).  It is probably best to avoid
1149 *  an "endian swapping control bit" in the CPU.  One good reason is
1150 *  that interrupts would probably have to be disabled to ensure that
1151 *  an interrupt does not try to access the same "chunk" with the wrong
1152 *  endian.  Another good reason is that on some CPUs, the endian bit
1153 *  endianness for ALL fetches -- both code and data -- so the code
1154 *  will be fetched incorrectly.
1155 *
1156 *  H8300 Specific Information:
1157 *
1158 *  This is the generic implementation.
1159 */
1160 
1161static inline uint32_t   CPU_swap_u32(
1162  uint32_t   value
1163)
1164{
1165  uint32_t   byte1, byte2, byte3, byte4, swapped;
1166 
1167  byte4 = (value >> 24) & 0xff;
1168  byte3 = (value >> 16) & 0xff;
1169  byte2 = (value >> 8)  & 0xff;
1170  byte1 =  value        & 0xff;
1171 
1172  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1173  return( swapped );
1174}
1175
1176#define CPU_swap_u16( value ) \
1177  (((value&0xff) << 8) | ((value >> 8)&0xff))
1178
1179/* to be provided by the BSP */
1180extern void H8BD_Install_IRQ(
1181  uint32_t      vector,
1182  proc_ptr      new_handler,
1183  proc_ptr      *old_handler );
1184
1185#ifdef __cplusplus
1186}
1187#endif
1188
1189#endif
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