source: rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h @ 815994f

4.11
Last change on this file since 815994f was 815994f, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2012 at 4:48:11 PM

score: Add CPU_Exception_frame

Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().

The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().

Add rtems_exception_frame and rtems_exception_frame_print().

Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.

Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().

Add test sptests/spfatal26.

  • Property mode set to 100644
File size: 32.0 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the H8300
7 *  processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef _RTEMS_SCORE_CPU_H
18#define _RTEMS_SCORE_CPU_H
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/types.h>
25#include <rtems/score/h8300.h>
26#ifndef ASM
27  #include <rtems/bspIo.h>
28#endif
29
30/* conditional compilation parameters */
31
32/*
33 *  Should the calls to _Thread_Enable_dispatch be inlined?
34 *
35 *  If TRUE, then they are inlined.
36 *  If FALSE, then a subroutine call is made.
37 *
38 *  Basically this is an example of the classic trade-off of size
39 *  versus speed.  Inlining the call (TRUE) typically increases the
40 *  size of RTEMS while speeding up the enabling of dispatching.
41 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
42 *  only be 0 or 1 unless you are in an interrupt handler and that
43 *  interrupt handler invokes the executive.]  When not inlined
44 *  something calls _Thread_Enable_dispatch which in turns calls
45 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
46 *  one subroutine call is avoided entirely.]
47 *
48 *  H8300 Specific Information:
49 *
50 *  XXX
51 */
52
53#define CPU_INLINE_ENABLE_DISPATCH       FALSE
54
55/*
56 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
57 *  be unrolled one time?  In unrolled each iteration of the loop examines
58 *  two "nodes" on the chain being searched.  Otherwise, only one node
59 *  is examined per iteration.
60 *
61 *  If TRUE, then the loops are unrolled.
62 *  If FALSE, then the loops are not unrolled.
63 *
64 *  The primary factor in making this decision is the cost of disabling
65 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
66 *  body of the loop.  On some CPUs, the flash is more expensive than
67 *  one iteration of the loop body.  In this case, it might be desirable
68 *  to unroll the loop.  It is important to note that on some CPUs, this
69 *  code is the longest interrupt disable period in RTEMS.  So it is
70 *  necessary to strike a balance when setting this parameter.
71 *
72 *  H8300 Specific Information:
73 *
74 *  XXX
75 */
76
77#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
78
79/*
80 *  Should this target use 16 or 32 bit object Ids?
81 *
82 */
83#define RTEMS_USE_16_BIT_OBJECT
84
85/*
86 *  Does RTEMS manage a dedicated interrupt stack in software?
87 *
88 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
89 *  If FALSE, nothing is done.
90 *
91 *  If the CPU supports a dedicated interrupt stack in hardware,
92 *  then it is generally the responsibility of the BSP to allocate it
93 *  and set it up.
94 *
95 *  If the CPU does not support a dedicated interrupt stack, then
96 *  the porter has two options: (1) execute interrupts on the
97 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
98 *  interrupt stack.
99 *
100 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
101 *
102 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
103 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
104 *  possible that both are FALSE for a particular CPU.  Although it
105 *  is unclear what that would imply about the interrupt processing
106 *  procedure on that CPU.
107 *
108 *  H8300 Specific Information:
109 *
110 *  XXX
111 */
112
113#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
114
115/*
116 *  Does the CPU follow the simple vectored interrupt model?
117 *
118 *  If TRUE, then RTEMS allocates the vector table it internally manages.
119 *  If FALSE, then the BSP is assumed to allocate and manage the vector
120 *  table
121 *
122 *  H8300 Specific Information:
123 *
124 *  XXX document implementation including references if appropriate
125 */
126#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
127
128/*
129 *  Does this CPU have hardware support for a dedicated interrupt stack?
130 *
131 *  If TRUE, then it must be installed during initialization.
132 *  If FALSE, then no installation is performed.
133 *
134 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
135 *
136 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
137 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
138 *  possible that both are FALSE for a particular CPU.  Although it
139 *  is unclear what that would imply about the interrupt processing
140 *  procedure on that CPU.
141 *
142 *  H8300 Specific Information:
143 *
144 *  XXX
145 */
146
147#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
148
149/*
150 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
151 *
152 *  If TRUE, then the memory is allocated during initialization.
153 *  If FALSE, then the memory is allocated during initialization.
154 *
155 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
156 *
157 *  H8300 Specific Information:
158 *
159 *  XXX
160 */
161
162#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
163
164/*
165 *  Does the CPU have hardware floating point?
166 *
167 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
168 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
169 *
170 *  If there is a FP coprocessor such as the i387 or mc68881, then
171 *  the answer is TRUE.
172 *
173 *  The macro name "H8300_HAS_FPU" should be made CPU specific.
174 *  It indicates whether or not this CPU model has FP support.  For
175 *  example, it would be possible to have an i386_nofp CPU model
176 *  which set this to false to indicate that you have an i386 without
177 *  an i387 and wish to leave floating point support out of RTEMS.
178 *
179 *  H8300 Specific Information:
180 *
181 *  XXX
182 */
183
184#define CPU_HARDWARE_FP     FALSE
185
186/*
187 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
188 *
189 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
190 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
191 *
192 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
193 *
194 *  H8300 Specific Information:
195 *
196 *  XXX
197 */
198
199#define CPU_ALL_TASKS_ARE_FP     FALSE
200
201/*
202 *  Should the IDLE task have a floating point context?
203 *
204 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
205 *  and it has a floating point context which is switched in and out.
206 *  If FALSE, then the IDLE task does not have a floating point context.
207 *
208 *  Setting this to TRUE negatively impacts the time required to preempt
209 *  the IDLE task from an interrupt because the floating point context
210 *  must be saved as part of the preemption.
211 *
212 *  H8300 Specific Information:
213 *
214 *  XXX
215 */
216
217#define CPU_IDLE_TASK_IS_FP      FALSE
218
219/*
220 *  Should the saving of the floating point registers be deferred
221 *  until a context switch is made to another different floating point
222 *  task?
223 *
224 *  If TRUE, then the floating point context will not be stored until
225 *  necessary.  It will remain in the floating point registers and not
226 *  disturned until another floating point task is switched to.
227 *
228 *  If FALSE, then the floating point context is saved when a floating
229 *  point task is switched out and restored when the next floating point
230 *  task is restored.  The state of the floating point registers between
231 *  those two operations is not specified.
232 *
233 *  If the floating point context does NOT have to be saved as part of
234 *  interrupt dispatching, then it should be safe to set this to TRUE.
235 *
236 *  Setting this flag to TRUE results in using a different algorithm
237 *  for deciding when to save and restore the floating point context.
238 *  The deferred FP switch algorithm minimizes the number of times
239 *  the FP context is saved and restored.  The FP context is not saved
240 *  until a context switch is made to another, different FP task.
241 *  Thus in a system with only one FP task, the FP context will never
242 *  be saved or restored.
243 *
244 *  H8300 Specific Information:
245 *
246 *  XXX
247 */
248
249#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
250
251/*
252 *  Does this port provide a CPU dependent IDLE task implementation?
253 *
254 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
255 *  must be provided and is the default IDLE thread body instead of
256 *  _Internal_threads_Idle_thread_body.
257 *
258 *  If FALSE, then use the generic IDLE thread body if the BSP does
259 *  not provide one.
260 *
261 *  This is intended to allow for supporting processors which have
262 *  a low power or idle mode.  When the IDLE thread is executed, then
263 *  the CPU can be powered down.
264 *
265 *  The order of precedence for selecting the IDLE thread body is:
266 *
267 *    1.  BSP provided
268 *    2.  CPU dependent (if provided)
269 *    3.  generic (if no BSP and no CPU dependent)
270 *
271 *  H8300 Specific Information:
272 *
273 *  XXX
274 *  The port initially called a BSP dependent routine called
275 *  IDLE_Monitor.  The idle task body can be overridden by
276 *  the BSP in newer versions of RTEMS.
277 */
278
279#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
280
281/*
282 *  Does the stack grow up (toward higher addresses) or down
283 *  (toward lower addresses)?
284 *
285 *  If TRUE, then the grows upward.
286 *  If FALSE, then the grows toward smaller addresses.
287 *
288 *  H8300 Specific Information:
289 *
290 *  XXX
291 */
292
293#define CPU_STACK_GROWS_UP               FALSE
294
295/*
296 *  The following is the variable attribute used to force alignment
297 *  of critical RTEMS structures.  On some processors it may make
298 *  sense to have these aligned on tighter boundaries than
299 *  the minimum requirements of the compiler in order to have as
300 *  much of the critical data area as possible in a cache line.
301 *
302 *  The placement of this macro in the declaration of the variables
303 *  is based on the syntactically requirements of the GNU C
304 *  "__attribute__" extension.  For example with GNU C, use
305 *  the following to force a structures to a 32 byte boundary.
306 *
307 *      __attribute__ ((aligned (32)))
308 *
309 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
310 *         To benefit from using this, the data must be heavily
311 *         used so it will stay in the cache and used frequently enough
312 *         in the executive to justify turning this on.
313 *
314 *  H8300 Specific Information:
315 *
316 *  XXX
317 */
318
319#define CPU_STRUCTURE_ALIGNMENT
320
321#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
322
323/*
324 *  Define what is required to specify how the network to host conversion
325 *  routines are handled.
326 */
327
328#define CPU_BIG_ENDIAN                           TRUE
329#define CPU_LITTLE_ENDIAN                        FALSE
330
331/*
332 *  The following defines the number of bits actually used in the
333 *  interrupt field of the task mode.  How those bits map to the
334 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
335 *
336 *  H8300 Specific Information:
337 *
338 *  XXX
339 */
340
341#define CPU_MODES_INTERRUPT_MASK   0x00000001
342
343/*
344 *  Processor defined structures required for cpukit/score.
345 *
346 *  H8300 Specific Information:
347 *
348 *  XXX
349 */
350
351/* may need to put some structures here.  */
352
353/*
354 * Contexts
355 *
356 *  Generally there are 2 types of context to save.
357 *     1. Interrupt registers to save
358 *     2. Task level registers to save
359 *
360 *  This means we have the following 3 context items:
361 *     1. task level context stuff::  Context_Control
362 *     2. floating point task stuff:: Context_Control_fp
363 *     3. special interrupt level context :: Context_Control_interrupt
364 *
365 *  On some processors, it is cost-effective to save only the callee
366 *  preserved registers during a task context switch.  This means
367 *  that the ISR code needs to save those registers which do not
368 *  persist across function calls.  It is not mandatory to make this
369 *  distinctions between the caller/callee saves registers for the
370 *  purpose of minimizing context saved during task switch and on interrupts.
371 *  If the cost of saving extra registers is minimal, simplicity is the
372 *  choice.  Save the same context on interrupt entry as for tasks in
373 *  this case.
374 *
375 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
376 *  care should be used in designing the context area.
377 *
378 *  On some CPUs with hardware floating point support, the Context_Control_fp
379 *  structure will not be used or it simply consist of an array of a
380 *  fixed number of bytes.   This is done when the floating point context
381 *  is dumped by a "FP save context" type instruction and the format
382 *  is not really defined by the CPU.  In this case, there is no need
383 *  to figure out the exact format -- only the size.  Of course, although
384 *  this is enough information for RTEMS, it is probably not enough for
385 *  a debugger such as gdb.  But that is another problem.
386 *
387 *  H8300 Specific Information:
388 *
389 *  XXX
390 */
391
392#ifndef ASM
393
394#define nogap __attribute__ ((packed))
395
396typedef struct {
397    uint16_t    ccr nogap;
398    void        *er7 nogap;
399    void        *er6 nogap;
400    uint32_t    er5 nogap;
401    uint32_t    er4 nogap;
402    uint32_t    er3 nogap;
403    uint32_t    er2 nogap;
404    uint32_t    er1 nogap;
405    uint32_t    er0 nogap;
406    uint32_t    xxx nogap;
407} Context_Control;
408
409#define _CPU_Context_Get_SP( _context ) \
410  (_context)->er7
411
412typedef struct {
413    double      some_float_register[2];
414} Context_Control_fp;
415
416typedef struct {
417    uint32_t   special_interrupt_register;
418} CPU_Interrupt_frame;
419
420/*
421 *  This variable is optional.  It is used on CPUs on which it is difficult
422 *  to generate an "uninitialized" FP context.  It is filled in by
423 *  _CPU_Initialize and copied into the task's FP context area during
424 *  _CPU_Context_Initialize.
425 *
426 *  H8300 Specific Information:
427 *
428 *  XXX
429 */
430
431SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
432
433/*
434 *  Nothing prevents the porter from declaring more CPU specific variables.
435 *
436 *  H8300 Specific Information:
437 *
438 *  XXX
439 */
440
441/* XXX: if needed, put more variables here */
442
443/*
444 *  The size of the floating point context area.  On some CPUs this
445 *  will not be a "sizeof" because the format of the floating point
446 *  area is not defined -- only the size is.  This is usually on
447 *  CPUs with a "floating point save context" instruction.
448 *
449 *  H8300 Specific Information:
450 *
451 *  XXX
452 */
453
454#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
455
456#endif /* ASM */
457
458/*
459 *  Amount of extra stack (above minimum stack size) required by
460 *  system initialization thread.  Remember that in a multiprocessor
461 *  system the system intialization thread becomes the MP server thread.
462 *
463 *  H8300 Specific Information:
464 *
465 *  It is highly unlikely the H8300 will get used in a multiprocessor system.
466 */
467
468#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
469
470/*
471 *  This defines the number of entries in the ISR_Vector_table managed
472 *  by RTEMS.
473 *
474 *  H8300 Specific Information:
475 *
476 *  XXX
477 */
478
479#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
480#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
481
482/*
483 *  This is defined if the port has a special way to report the ISR nesting
484 *  level.  Most ports maintain the variable _ISR_Nest_level.
485 */
486
487#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
488
489/*
490 *  Should be large enough to run all RTEMS tests.  This ensures
491 *  that a "reasonable" small application should not have any problems.
492 *
493 *  H8300 Specific Information:
494 *
495 *  XXX
496 */
497
498#define CPU_STACK_MINIMUM_SIZE          (1536)
499
500#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
501  #define CPU_SIZEOF_POINTER 4
502#else
503  #define CPU_SIZEOF_POINTER 2
504#endif
505
506/*
507 *  CPU's worst alignment requirement for data types on a byte boundary.  This
508 *  alignment does not take into account the requirements for the stack.
509 *
510 *  H8300 Specific Information:
511 *
512 *  XXX
513 */
514
515#define CPU_ALIGNMENT              8
516
517/*
518 *  This number corresponds to the byte alignment requirement for the
519 *  heap handler.  This alignment requirement may be stricter than that
520 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
521 *  common for the heap to follow the same alignment requirement as
522 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
523 *  then this should be set to CPU_ALIGNMENT.
524 *
525 *  NOTE:  This does not have to be a power of 2.  It does have to
526 *         be greater or equal to than CPU_ALIGNMENT.
527 *
528 *  H8300 Specific Information:
529 *
530 *  XXX
531 */
532
533#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
534
535/*
536 *  This number corresponds to the byte alignment requirement for memory
537 *  buffers allocated by the partition manager.  This alignment requirement
538 *  may be stricter than that for the data types alignment specified by
539 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
540 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
541 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
542 *
543 *  NOTE:  This does not have to be a power of 2.  It does have to
544 *         be greater or equal to than CPU_ALIGNMENT.
545 *
546 *  H8300 Specific Information:
547 *
548 *  XXX
549 */
550
551#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
552
553/*
554 *  This number corresponds to the byte alignment requirement for the
555 *  stack.  This alignment requirement may be stricter than that for the
556 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
557 *  is strict enough for the stack, then this should be set to 0.
558 *
559 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
560 *
561 *  H8300 Specific Information:
562 *
563 *  XXX
564 */
565
566#define CPU_STACK_ALIGNMENT        2
567
568/*
569 *  ISR handler macros
570 */
571
572/*
573 *  Support routine to initialize the RTEMS vector table after it is allocated.
574 */
575
576#define _CPU_Initialize_vectors()
577
578/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
579   Note requires ISR_Level be uint16_t or assembler croaks.
580*/
581
582#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
583
584
585/*
586 *  Disable all interrupts for an RTEMS critical section.  The previous
587 *  level is returned in _level.
588 */
589
590#define _CPU_ISR_Disable( _isr_cookie ) \
591  do { \
592    __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
593  } while (0)
594
595
596/*
597 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
598 *  This indicates the end of an RTEMS critical section.  The parameter
599 *  _level is not modified.
600 */
601
602
603#define _CPU_ISR_Enable( _isr_cookie )  \
604  do { \
605    __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
606  } while (0)
607
608
609/*
610 *  This temporarily restores the interrupt to _level before immediately
611 *  disabling them again.  This is used to divide long RTEMS critical
612 *  sections into two or more parts.  The parameter _level is not
613 * modified.
614 */
615
616
617#define _CPU_ISR_Flash( _isr_cookie ) \
618  do { \
619    __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
620  } while (0)
621
622/* end of ISR handler macros */
623
624#else /* modern gcc version */
625
626/*
627 *  Disable all interrupts for an RTEMS critical section.  The previous
628 *  level is returned in _level.
629 *
630 *  H8300 Specific Information:
631 *
632 *  XXX
633 */
634
635#if defined(__H8300H__) || defined(__H8300S__)
636#define _CPU_ISR_Disable( _isr_cookie ) \
637  do { \
638    unsigned char __ccr; \
639    __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \
640             : "=m" (__ccr) /* : "0" (__ccr) */ ); \
641    (_isr_cookie) = __ccr; \
642  } while (0)
643#else
644#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
645#endif
646
647
648/*
649 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
650 *  This indicates the end of an RTEMS critical section.  The parameter
651 *  _level is not modified.
652 *
653 *  H8300 Specific Information:
654 *
655 *  XXX
656 */
657
658#if defined(__H8300H__) || defined(__H8300S__)
659#define _CPU_ISR_Enable( _isr_cookie )  \
660  do { \
661    unsigned char __ccr = (unsigned char) (_isr_cookie); \
662    __asm__ volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
663  } while (0)
664#else
665#define _CPU_ISR_Enable( _isr_cookie )
666#endif
667
668/*
669 *  This temporarily restores the interrupt to _level before immediately
670 *  disabling them again.  This is used to divide long RTEMS critical
671 *  sections into two or more parts.  The parameter _level is not
672 *  modified.
673 *
674 *  H8300 Specific Information:
675 *
676 *  XXX
677 */
678
679#if defined(__H8300H__) || defined(__H8300S__)
680#define _CPU_ISR_Flash( _isr_cookie ) \
681  do { \
682    unsigned char __ccr = (unsigned char) (_isr_cookie); \
683    __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
684  } while (0)
685#else
686#define _CPU_ISR_Flash( _isr_cookie )
687#endif
688
689#endif /* end of old gcc */
690
691
692/*
693 *  Map interrupt level in task mode onto the hardware that the CPU
694 *  actually provides.  Currently, interrupt levels which do not
695 *  map onto the CPU in a generic fashion are undefined.  Someday,
696 *  it would be nice if these were "mapped" by the application
697 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
698 *  8 - 255 would be available for bsp/application specific meaning.
699 *  This could be used to manage a programmable interrupt controller
700 *  via the rtems_task_mode directive.
701 *
702 *  H8300 Specific Information:
703 *
704 *  XXX
705 */
706
707#define _CPU_ISR_Set_level( _new_level ) \
708  { \
709    if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \
710    else              __asm__ volatile ( "andc #0x7f,ccr\n" ); \
711  }
712
713#ifndef ASM
714
715uint32_t   _CPU_ISR_Get_level( void );
716
717/* end of ISR handler macros */
718
719/* Context handler macros */
720
721/*
722 *  Initialize the context to a state suitable for starting a
723 *  task after a context restore operation.  Generally, this
724 *  involves:
725 *
726 *     - setting a starting address
727 *     - preparing the stack
728 *     - preparing the stack and frame pointers
729 *     - setting the proper interrupt level in the context
730 *     - initializing the floating point context
731 *
732 *  This routine generally does not set any unnecessary register
733 *  in the context.  The state of the "general data" registers is
734 *  undefined at task start time.
735 *
736 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
737 *        point thread.  This is typically only used on CPUs where the
738 *        FPU may be easily disabled by software such as on the SPARC
739 *        where the PSR contains an enable FPU bit.
740 *
741 *  H8300 Specific Information:
742 *
743 *  XXX
744 */
745
746
747#define CPU_CCR_INTERRUPTS_ON  0x80
748#define CPU_CCR_INTERRUPTS_OFF 0x00
749
750#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
751                                   _isr, _entry_point, _is_fp ) \
752  /* Locate Me */ \
753  do { \
754    uintptr_t   _stack; \
755    \
756    if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
757    else          (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
758    \
759    _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \
760    *((proc_ptr *)(_stack)) = (_entry_point); \
761     (_the_context)->er7     = (void *) _stack; \
762     (_the_context)->er6     = (void *) _stack; \
763     (_the_context)->er5     = 0; \
764     (_the_context)->er4     = 1; \
765     (_the_context)->er3     = 2; \
766  } while (0)
767
768
769/*
770 *  This routine is responsible for somehow restarting the currently
771 *  executing task.  If you are lucky, then all that is necessary
772 *  is restoring the context.  Otherwise, there will need to be
773 *  a special assembly routine which does something special in this
774 *  case.  Context_Restore should work most of the time.  It will
775 *  not work if restarting self conflicts with the stack frame
776 *  assumptions of restoring a context.
777 *
778 *  H8300 Specific Information:
779 *
780 *  XXX
781 */
782
783#define _CPU_Context_Restart_self( _the_context ) \
784   _CPU_Context_restore( (_the_context) );
785
786/*
787 *  The purpose of this macro is to allow the initial pointer into
788 *  a floating point context area (used to save the floating point
789 *  context) to be at an arbitrary place in the floating point
790 *  context area.
791 *
792 *  This is necessary because some FP units are designed to have
793 *  their context saved as a stack which grows into lower addresses.
794 *  Other FP units can be saved by simply moving registers into offsets
795 *  from the base of the context area.  Finally some FP units provide
796 *  a "dump context" instruction which could fill in from high to low
797 *  or low to high based on the whim of the CPU designers.
798 *
799 *  H8300 Specific Information:
800 *
801 *  XXX
802 */
803
804#define _CPU_Context_Fp_start( _base, _offset ) \
805   ( (void *) (_base) + (_offset) )
806
807/*
808 *  This routine initializes the FP context area passed to it to.
809 *  There are a few standard ways in which to initialize the
810 *  floating point context.  The code included for this macro assumes
811 *  that this is a CPU in which a "initial" FP context was saved into
812 *  _CPU_Null_fp_context and it simply copies it to the destination
813 *  context passed to it.
814 *
815 *  Other models include (1) not doing anything, and (2) putting
816 *  a "null FP status word" in the correct place in the FP context.
817 *
818 *  H8300 Specific Information:
819 *
820 *  XXX
821 */
822
823#define _CPU_Context_Initialize_fp( _destination ) \
824  { \
825   *(*(_destination)) = _CPU_Null_fp_context; \
826  }
827
828/* end of Context handler macros */
829
830/* Fatal Error manager macros */
831
832/*
833 *  This routine copies _error into a known place -- typically a stack
834 *  location or a register, optionally disables interrupts, and
835 *  halts/stops the CPU.
836 *
837 *  H8300 Specific Information:
838 *
839 *  XXX
840 */
841
842#define _CPU_Fatal_halt( _error ) \
843        printk("Fatal Error %d Halted\n",_error); \
844        for(;;)
845
846
847/* end of Fatal Error manager macros */
848
849/* Bitfield handler macros */
850
851/*
852 *  This routine sets _output to the bit number of the first bit
853 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
854 *  This type may be either 16 or 32 bits wide although only the 16
855 *  least significant bits will be used.
856 *
857 *  There are a number of variables in using a "find first bit" type
858 *  instruction.
859 *
860 *    (1) What happens when run on a value of zero?
861 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
862 *    (3) The numbering may be zero or one based.
863 *    (4) The "find first bit" instruction may search from MSB or LSB.
864 *
865 *  RTEMS guarantees that (1) will never happen so it is not a concern.
866 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
867 *  _CPU_Priority_bits_index().  These three form a set of routines
868 *  which must logically operate together.  Bits in the _value are
869 *  set and cleared based on masks built by _CPU_Priority_mask().
870 *  The basic major and minor values calculated by _Priority_Major()
871 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
872 *  to properly range between the values returned by the "find first bit"
873 *  instruction.  This makes it possible for _Priority_Get_highest() to
874 *  calculate the major and directly index into the minor table.
875 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
876 *  is the first bit found.
877 *
878 *  This entire "find first bit" and mapping process depends heavily
879 *  on the manner in which a priority is broken into a major and minor
880 *  components with the major being the 4 MSB of a priority and minor
881 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
882 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
883 *  to the lowest priority.
884 *
885 *  If your CPU does not have a "find first bit" instruction, then
886 *  there are ways to make do without it.  Here are a handful of ways
887 *  to implement this in software:
888 *
889 *    - a series of 16 bit test instructions
890 *    - a "binary search using if's"
891 *    - _number = 0
892 *      if _value > 0x00ff
893 *        _value >>=8
894 *        _number = 8;
895 *
896 *      if _value > 0x0000f
897 *        _value >=8
898 *        _number += 4
899 *
900 *      _number += bit_set_table[ _value ]
901 *
902 *    where bit_set_table[ 16 ] has values which indicate the first
903 *      bit set
904 *
905 *  H8300 Specific Information:
906 *
907 *  XXX
908 */
909
910#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
911#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
912
913#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
914
915#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
916  { \
917    (_output) = 0;   /* do something to prevent warnings */ \
918  }
919
920#endif
921
922/* end of Bitfield handler macros */
923
924/*
925 *  This routine builds the mask which corresponds to the bit fields
926 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
927 *  for that routine.
928 *
929 *  H8300 Specific Information:
930 *
931 *  XXX
932 */
933
934#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
935
936#define _CPU_Priority_Mask( _bit_number ) \
937  ( 1 << (_bit_number) )
938
939#endif
940
941/*
942 *  This routine translates the bit numbers returned by
943 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
944 *  a major or minor component of a priority.  See the discussion
945 *  for that routine.
946 *
947 *  H8300 Specific Information:
948 *
949 *  XXX
950 */
951
952#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
953
954#define _CPU_Priority_bits_index( _priority ) \
955  (_priority)
956
957#endif
958
959/* end of Priority handler macros */
960
961/* functions */
962
963/*
964 *  _CPU_Initialize
965 *
966 *  This routine performs CPU dependent initialization.
967 *
968 *  H8300 Specific Information:
969 *
970 *  XXX
971 */
972
973void _CPU_Initialize(void);
974
975/*
976 *  _CPU_ISR_install_raw_handler
977 *
978 *  This routine installs a "raw" interrupt handler directly into the
979 *  processor's vector table.
980 *
981 *  H8300 Specific Information:
982 *
983 *  XXX
984 */
985
986void _CPU_ISR_install_raw_handler(
987  uint32_t    vector,
988  proc_ptr    new_handler,
989  proc_ptr   *old_handler
990);
991
992/*
993 *  _CPU_ISR_install_vector
994 *
995 *  This routine installs an interrupt vector.
996 *
997 *  H8300 Specific Information:
998 *
999 *  XXX
1000 */
1001
1002void _CPU_ISR_install_vector(
1003  uint32_t    vector,
1004  proc_ptr    new_handler,
1005  proc_ptr   *old_handler
1006);
1007
1008/*
1009 *  _CPU_Install_interrupt_stack
1010 *
1011 *  This routine installs the hardware interrupt stack pointer.
1012 *
1013 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1014 *         is TRUE.
1015 *
1016 *  H8300 Specific Information:
1017 *
1018 *  XXX
1019 */
1020
1021void _CPU_Install_interrupt_stack( void );
1022
1023/*
1024 *  _CPU_Internal_threads_Idle_thread_body
1025 *
1026 *  This routine is the CPU dependent IDLE thread body.
1027 *
1028 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1029 *         is TRUE.
1030 *
1031 *  H8300 Specific Information:
1032 *
1033 *  XXX
1034 */
1035
1036void *_CPU_Thread_Idle_body( uint32_t );
1037
1038/*
1039 *  _CPU_Context_switch
1040 *
1041 *  This routine switches from the run context to the heir context.
1042 *
1043 *  H8300 Specific Information:
1044 *
1045 *  XXX
1046 */
1047
1048void _CPU_Context_switch(
1049  Context_Control  *run,
1050  Context_Control  *heir
1051);
1052
1053/*
1054 *  _CPU_Context_restore
1055 *
1056 *  This routine is generallu used only to restart self in an
1057 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1058 *
1059 *  NOTE: May be unnecessary to reload some registers.
1060 *
1061 *  H8300 Specific Information:
1062 *
1063 *  XXX
1064 */
1065
1066void _CPU_Context_restore(
1067  Context_Control *new_context
1068) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1069
1070/*
1071 *  _CPU_Context_save_fp
1072 *
1073 *  This routine saves the floating point context passed to it.
1074 *
1075 *  H8300 Specific Information:
1076 *
1077 *  XXX
1078 */
1079
1080void _CPU_Context_save_fp(
1081  Context_Control_fp **fp_context_ptr
1082);
1083
1084/*
1085 *  _CPU_Context_restore_fp
1086 *
1087 *  This routine restores the floating point context passed to it.
1088 *
1089 *  H8300 Specific Information:
1090 *
1091 *  XXX
1092 */
1093
1094void _CPU_Context_restore_fp(
1095  Context_Control_fp **fp_context_ptr
1096);
1097
1098/* FIXME */
1099typedef CPU_Interrupt_frame CPU_Exception_frame;
1100
1101void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1102
1103/*  The following routine swaps the endian format of an unsigned int.
1104 *  It must be static because it is referenced indirectly.
1105 *
1106 *  This version will work on any processor, but if there is a better
1107 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1108 *
1109 *     swap least significant two bytes with 16-bit rotate
1110 *     swap upper and lower 16-bits
1111 *     swap most significant two bytes with 16-bit rotate
1112 *
1113 *  Some CPUs have special instructions which swap a 32-bit quantity in
1114 *  a single instruction (e.g. i486).  It is probably best to avoid
1115 *  an "endian swapping control bit" in the CPU.  One good reason is
1116 *  that interrupts would probably have to be disabled to ensure that
1117 *  an interrupt does not try to access the same "chunk" with the wrong
1118 *  endian.  Another good reason is that on some CPUs, the endian bit
1119 *  endianness for ALL fetches -- both code and data -- so the code
1120 *  will be fetched incorrectly.
1121 *
1122 *  H8300 Specific Information:
1123 *
1124 *  This is the generic implementation.
1125 */
1126
1127static inline uint32_t   CPU_swap_u32(
1128  uint32_t   value
1129)
1130{
1131  uint32_t   byte1, byte2, byte3, byte4, swapped;
1132
1133  byte4 = (value >> 24) & 0xff;
1134  byte3 = (value >> 16) & 0xff;
1135  byte2 = (value >> 8)  & 0xff;
1136  byte1 =  value        & 0xff;
1137
1138  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1139  return( swapped );
1140}
1141
1142#define CPU_swap_u16( value ) \
1143  (((value&0xff) << 8) | ((value >> 8)&0xff))
1144
1145/* to be provided by the BSP */
1146extern void H8BD_Install_IRQ(
1147  uint32_t      vector,
1148  proc_ptr      new_handler,
1149  proc_ptr      *old_handler );
1150
1151#endif /* ASM */
1152
1153#ifdef __cplusplus
1154}
1155#endif
1156
1157#endif
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