[aa5049d] | 1 | /** |
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| 2 | * @file rtems/score/cpu.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[2540208] | 6 | * This include file contains information pertaining to the H8300 |
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[5532553] | 7 | * processor. |
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| 8 | * |
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[ece004d] | 9 | * COPYRIGHT (c) 1989-2006. |
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[5532553] | 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[a97f3776] | 14 | * http://www.rtems.com/license/LICENSE. |
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[5532553] | 15 | */ |
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| 16 | |
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[7f70d1b7] | 17 | #ifndef _RTEMS_SCORE_CPU_H |
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| 18 | #define _RTEMS_SCORE_CPU_H |
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[5532553] | 19 | |
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| 20 | #ifdef __cplusplus |
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| 21 | extern "C" { |
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| 22 | #endif |
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| 23 | |
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[b03055e] | 24 | #include <rtems/score/types.h> |
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[89b85e51] | 25 | #include <rtems/score/h8300.h> |
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[4ac56fbb] | 26 | #ifndef ASM |
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| 27 | #include <rtems/bspIo.h> |
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| 28 | #endif |
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[b8caf37] | 29 | |
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[5532553] | 30 | /* conditional compilation parameters */ |
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| 31 | |
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| 32 | /* |
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| 33 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 34 | * |
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| 35 | * If TRUE, then they are inlined. |
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| 36 | * If FALSE, then a subroutine call is made. |
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| 37 | * |
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| 38 | * Basically this is an example of the classic trade-off of size |
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| 39 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 40 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 41 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 42 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 43 | * interrupt handler invokes the executive.] When not inlined |
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| 44 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 45 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 46 | * one subroutine call is avoided entirely.] |
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| 47 | * |
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| 48 | * H8300 Specific Information: |
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| 49 | * |
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| 50 | * XXX |
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| 51 | */ |
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| 52 | |
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| 53 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 54 | |
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| 55 | /* |
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| 56 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 57 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 58 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 59 | * is examined per iteration. |
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| 60 | * |
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| 61 | * If TRUE, then the loops are unrolled. |
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| 62 | * If FALSE, then the loops are not unrolled. |
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| 63 | * |
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| 64 | * The primary factor in making this decision is the cost of disabling |
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| 65 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 66 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 67 | * one iteration of the loop body. In this case, it might be desirable |
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| 68 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 69 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 70 | * necessary to strike a balance when setting this parameter. |
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| 71 | * |
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| 72 | * H8300 Specific Information: |
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| 73 | * |
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| 74 | * XXX |
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| 75 | */ |
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| 76 | |
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[ef47bc78] | 77 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 78 | |
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| 79 | /* |
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| 80 | * Should this target use 16 or 32 bit object Ids? |
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| 81 | * |
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| 82 | */ |
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| 83 | #define RTEMS_USE_16_BIT_OBJECT |
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[5532553] | 84 | |
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| 85 | /* |
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| 86 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 87 | * |
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[8bc62aeb] | 88 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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[5532553] | 89 | * If FALSE, nothing is done. |
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| 90 | * |
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| 91 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 92 | * then it is generally the responsibility of the BSP to allocate it |
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| 93 | * and set it up. |
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| 94 | * |
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| 95 | * If the CPU does not support a dedicated interrupt stack, then |
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| 96 | * the porter has two options: (1) execute interrupts on the |
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| 97 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 98 | * interrupt stack. |
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| 99 | * |
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| 100 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 101 | * |
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| 102 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 103 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 104 | * possible that both are FALSE for a particular CPU. Although it |
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| 105 | * is unclear what that would imply about the interrupt processing |
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| 106 | * procedure on that CPU. |
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| 107 | * |
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| 108 | * H8300 Specific Information: |
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| 109 | * |
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| 110 | * XXX |
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| 111 | */ |
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| 112 | |
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| 113 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 114 | |
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[2fd427c] | 115 | /* |
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| 116 | * Does the CPU follow the simple vectored interrupt model? |
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| 117 | * |
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| 118 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 119 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 120 | * table |
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| 121 | * |
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| 122 | * H8300 Specific Information: |
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| 123 | * |
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| 124 | * XXX document implementation including references if appropriate |
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| 125 | */ |
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| 126 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 127 | |
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[5532553] | 128 | /* |
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| 129 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 130 | * |
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| 131 | * If TRUE, then it must be installed during initialization. |
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| 132 | * If FALSE, then no installation is performed. |
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| 133 | * |
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| 134 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 135 | * |
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| 136 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 137 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 138 | * possible that both are FALSE for a particular CPU. Although it |
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| 139 | * is unclear what that would imply about the interrupt processing |
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| 140 | * procedure on that CPU. |
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| 141 | * |
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| 142 | * H8300 Specific Information: |
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| 143 | * |
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| 144 | * XXX |
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| 145 | */ |
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| 146 | |
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| 147 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 148 | |
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| 149 | /* |
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| 150 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 151 | * |
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| 152 | * If TRUE, then the memory is allocated during initialization. |
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| 153 | * If FALSE, then the memory is allocated during initialization. |
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| 154 | * |
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[ece004d] | 155 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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[5532553] | 156 | * |
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| 157 | * H8300 Specific Information: |
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| 158 | * |
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| 159 | * XXX |
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| 160 | */ |
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| 161 | |
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| 162 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 163 | |
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| 164 | /* |
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| 165 | * Does the CPU have hardware floating point? |
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| 166 | * |
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| 167 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 168 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 169 | * |
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| 170 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 171 | * the answer is TRUE. |
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| 172 | * |
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[22ddca1f] | 173 | * The macro name "H8300_HAS_FPU" should be made CPU specific. |
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[5532553] | 174 | * It indicates whether or not this CPU model has FP support. For |
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| 175 | * example, it would be possible to have an i386_nofp CPU model |
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| 176 | * which set this to false to indicate that you have an i386 without |
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| 177 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 178 | * |
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| 179 | * H8300 Specific Information: |
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| 180 | * |
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| 181 | * XXX |
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| 182 | */ |
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| 183 | |
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| 184 | #define CPU_HARDWARE_FP FALSE |
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| 185 | |
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| 186 | /* |
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| 187 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 188 | * |
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| 189 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 190 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 191 | * |
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| 192 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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| 193 | * |
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| 194 | * H8300 Specific Information: |
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| 195 | * |
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| 196 | * XXX |
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| 197 | */ |
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| 198 | |
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| 199 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 200 | |
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| 201 | /* |
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| 202 | * Should the IDLE task have a floating point context? |
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| 203 | * |
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| 204 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 205 | * and it has a floating point context which is switched in and out. |
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| 206 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 207 | * |
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| 208 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 209 | * the IDLE task from an interrupt because the floating point context |
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| 210 | * must be saved as part of the preemption. |
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| 211 | * |
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| 212 | * H8300 Specific Information: |
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| 213 | * |
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| 214 | * XXX |
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| 215 | */ |
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| 216 | |
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| 217 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 218 | |
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| 219 | /* |
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| 220 | * Should the saving of the floating point registers be deferred |
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| 221 | * until a context switch is made to another different floating point |
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| 222 | * task? |
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| 223 | * |
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| 224 | * If TRUE, then the floating point context will not be stored until |
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| 225 | * necessary. It will remain in the floating point registers and not |
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| 226 | * disturned until another floating point task is switched to. |
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| 227 | * |
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| 228 | * If FALSE, then the floating point context is saved when a floating |
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| 229 | * point task is switched out and restored when the next floating point |
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| 230 | * task is restored. The state of the floating point registers between |
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| 231 | * those two operations is not specified. |
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| 232 | * |
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| 233 | * If the floating point context does NOT have to be saved as part of |
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| 234 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 235 | * |
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| 236 | * Setting this flag to TRUE results in using a different algorithm |
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| 237 | * for deciding when to save and restore the floating point context. |
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| 238 | * The deferred FP switch algorithm minimizes the number of times |
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| 239 | * the FP context is saved and restored. The FP context is not saved |
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| 240 | * until a context switch is made to another, different FP task. |
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| 241 | * Thus in a system with only one FP task, the FP context will never |
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| 242 | * be saved or restored. |
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| 243 | * |
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| 244 | * H8300 Specific Information: |
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| 245 | * |
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| 246 | * XXX |
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| 247 | */ |
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| 248 | |
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| 249 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 250 | |
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| 251 | /* |
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| 252 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 253 | * |
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| 254 | * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body |
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| 255 | * must be provided and is the default IDLE thread body instead of |
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| 256 | * _Internal_threads_Idle_thread_body. |
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| 257 | * |
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| 258 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 259 | * not provide one. |
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| 260 | * |
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| 261 | * This is intended to allow for supporting processors which have |
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| 262 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 263 | * the CPU can be powered down. |
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| 264 | * |
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| 265 | * The order of precedence for selecting the IDLE thread body is: |
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| 266 | * |
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| 267 | * 1. BSP provided |
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| 268 | * 2. CPU dependent (if provided) |
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| 269 | * 3. generic (if no BSP and no CPU dependent) |
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| 270 | * |
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| 271 | * H8300 Specific Information: |
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| 272 | * |
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| 273 | * XXX |
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[5bb38e15] | 274 | * The port initially called a BSP dependent routine called |
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[5532553] | 275 | * IDLE_Monitor. The idle task body can be overridden by |
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| 276 | * the BSP in newer versions of RTEMS. |
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| 277 | */ |
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| 278 | |
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| 279 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 280 | |
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| 281 | /* |
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| 282 | * Does the stack grow up (toward higher addresses) or down |
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| 283 | * (toward lower addresses)? |
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| 284 | * |
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| 285 | * If TRUE, then the grows upward. |
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| 286 | * If FALSE, then the grows toward smaller addresses. |
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| 287 | * |
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| 288 | * H8300 Specific Information: |
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| 289 | * |
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| 290 | * XXX |
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| 291 | */ |
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| 292 | |
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| 293 | #define CPU_STACK_GROWS_UP FALSE |
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| 294 | |
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| 295 | /* |
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| 296 | * The following is the variable attribute used to force alignment |
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| 297 | * of critical RTEMS structures. On some processors it may make |
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| 298 | * sense to have these aligned on tighter boundaries than |
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| 299 | * the minimum requirements of the compiler in order to have as |
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| 300 | * much of the critical data area as possible in a cache line. |
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| 301 | * |
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| 302 | * The placement of this macro in the declaration of the variables |
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| 303 | * is based on the syntactically requirements of the GNU C |
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| 304 | * "__attribute__" extension. For example with GNU C, use |
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| 305 | * the following to force a structures to a 32 byte boundary. |
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| 306 | * |
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| 307 | * __attribute__ ((aligned (32))) |
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| 308 | * |
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| 309 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 310 | * To benefit from using this, the data must be heavily |
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| 311 | * used so it will stay in the cache and used frequently enough |
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| 312 | * in the executive to justify turning this on. |
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| 313 | * |
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| 314 | * H8300 Specific Information: |
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| 315 | * |
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| 316 | * XXX |
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| 317 | */ |
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| 318 | |
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| 319 | #define CPU_STRUCTURE_ALIGNMENT |
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| 320 | |
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[9c121991] | 321 | #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE |
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| 322 | |
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[5532553] | 323 | /* |
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| 324 | * Define what is required to specify how the network to host conversion |
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| 325 | * routines are handled. |
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| 326 | */ |
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| 327 | |
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| 328 | #define CPU_BIG_ENDIAN TRUE |
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| 329 | #define CPU_LITTLE_ENDIAN FALSE |
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| 330 | |
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| 331 | /* |
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| 332 | * The following defines the number of bits actually used in the |
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| 333 | * interrupt field of the task mode. How those bits map to the |
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| 334 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 335 | * |
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| 336 | * H8300 Specific Information: |
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| 337 | * |
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| 338 | * XXX |
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| 339 | */ |
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| 340 | |
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| 341 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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| 342 | |
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| 343 | /* |
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[90550fe] | 344 | * Processor defined structures required for cpukit/score. |
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[5532553] | 345 | * |
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| 346 | * H8300 Specific Information: |
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| 347 | * |
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| 348 | * XXX |
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| 349 | */ |
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| 350 | |
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| 351 | /* may need to put some structures here. */ |
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| 352 | |
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| 353 | /* |
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| 354 | * Contexts |
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| 355 | * |
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| 356 | * Generally there are 2 types of context to save. |
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| 357 | * 1. Interrupt registers to save |
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| 358 | * 2. Task level registers to save |
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| 359 | * |
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| 360 | * This means we have the following 3 context items: |
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| 361 | * 1. task level context stuff:: Context_Control |
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| 362 | * 2. floating point task stuff:: Context_Control_fp |
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| 363 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 364 | * |
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| 365 | * On some processors, it is cost-effective to save only the callee |
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| 366 | * preserved registers during a task context switch. This means |
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| 367 | * that the ISR code needs to save those registers which do not |
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| 368 | * persist across function calls. It is not mandatory to make this |
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| 369 | * distinctions between the caller/callee saves registers for the |
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| 370 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 371 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 372 | * choice. Save the same context on interrupt entry as for tasks in |
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| 373 | * this case. |
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| 374 | * |
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| 375 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 376 | * care should be used in designing the context area. |
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| 377 | * |
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| 378 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 379 | * structure will not be used or it simply consist of an array of a |
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| 380 | * fixed number of bytes. This is done when the floating point context |
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| 381 | * is dumped by a "FP save context" type instruction and the format |
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| 382 | * is not really defined by the CPU. In this case, there is no need |
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| 383 | * to figure out the exact format -- only the size. Of course, although |
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| 384 | * this is enough information for RTEMS, it is probably not enough for |
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| 385 | * a debugger such as gdb. But that is another problem. |
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| 386 | * |
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| 387 | * H8300 Specific Information: |
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| 388 | * |
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| 389 | * XXX |
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| 390 | */ |
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| 391 | |
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[4ac56fbb] | 392 | #ifndef ASM |
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[5532553] | 393 | |
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| 394 | #define nogap __attribute__ ((packed)) |
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| 395 | |
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| 396 | typedef struct { |
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[c346f33d] | 397 | uint16_t ccr nogap; |
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[5532553] | 398 | void *er7 nogap; |
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| 399 | void *er6 nogap; |
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[c346f33d] | 400 | uint32_t er5 nogap; |
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| 401 | uint32_t er4 nogap; |
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| 402 | uint32_t er3 nogap; |
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| 403 | uint32_t er2 nogap; |
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| 404 | uint32_t er1 nogap; |
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| 405 | uint32_t er0 nogap; |
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| 406 | uint32_t xxx nogap; |
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[5532553] | 407 | } Context_Control; |
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| 408 | |
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[0ca6d0d9] | 409 | #define _CPU_Context_Get_SP( _context ) \ |
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| 410 | (_context)->er7 |
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| 411 | |
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[5532553] | 412 | typedef struct { |
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| 413 | double some_float_register[2]; |
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| 414 | } Context_Control_fp; |
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| 415 | |
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| 416 | typedef struct { |
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[c346f33d] | 417 | uint32_t special_interrupt_register; |
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[5532553] | 418 | } CPU_Interrupt_frame; |
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| 419 | |
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| 420 | /* |
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| 421 | * This variable is optional. It is used on CPUs on which it is difficult |
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| 422 | * to generate an "uninitialized" FP context. It is filled in by |
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| 423 | * _CPU_Initialize and copied into the task's FP context area during |
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| 424 | * _CPU_Context_Initialize. |
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| 425 | * |
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| 426 | * H8300 Specific Information: |
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| 427 | * |
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| 428 | * XXX |
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| 429 | */ |
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| 430 | |
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| 431 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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| 432 | |
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| 433 | /* |
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| 434 | * Nothing prevents the porter from declaring more CPU specific variables. |
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| 435 | * |
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| 436 | * H8300 Specific Information: |
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| 437 | * |
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| 438 | * XXX |
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| 439 | */ |
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| 440 | |
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| 441 | /* XXX: if needed, put more variables here */ |
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| 442 | |
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| 443 | /* |
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| 444 | * The size of the floating point context area. On some CPUs this |
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| 445 | * will not be a "sizeof" because the format of the floating point |
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| 446 | * area is not defined -- only the size is. This is usually on |
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| 447 | * CPUs with a "floating point save context" instruction. |
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| 448 | * |
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| 449 | * H8300 Specific Information: |
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| 450 | * |
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| 451 | * XXX |
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| 452 | */ |
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| 453 | |
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| 454 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 455 | |
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[4ac56fbb] | 456 | #endif /* ASM */ |
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| 457 | |
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[5532553] | 458 | /* |
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| 459 | * Amount of extra stack (above minimum stack size) required by |
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| 460 | * system initialization thread. Remember that in a multiprocessor |
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| 461 | * system the system intialization thread becomes the MP server thread. |
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| 462 | * |
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| 463 | * H8300 Specific Information: |
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| 464 | * |
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[3a05d15] | 465 | * It is highly unlikely the H8300 will get used in a multiprocessor system. |
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[5532553] | 466 | */ |
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| 467 | |
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[5bb38e15] | 468 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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[5532553] | 469 | |
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| 470 | /* |
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| 471 | * This defines the number of entries in the ISR_Vector_table managed |
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| 472 | * by RTEMS. |
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| 473 | * |
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| 474 | * H8300 Specific Information: |
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| 475 | * |
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| 476 | * XXX |
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| 477 | */ |
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| 478 | |
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| 479 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 |
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| 480 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 481 | |
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[4db30283] | 482 | /* |
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| 483 | * This is defined if the port has a special way to report the ISR nesting |
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| 484 | * level. Most ports maintain the variable _ISR_Nest_level. |
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| 485 | */ |
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| 486 | |
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| 487 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 488 | |
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[5532553] | 489 | /* |
---|
[ece004d] | 490 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[5532553] | 491 | * that a "reasonable" small application should not have any problems. |
---|
| 492 | * |
---|
| 493 | * H8300 Specific Information: |
---|
| 494 | * |
---|
| 495 | * XXX |
---|
| 496 | */ |
---|
| 497 | |
---|
| 498 | #define CPU_STACK_MINIMUM_SIZE (1536) |
---|
| 499 | |
---|
[f1738ed] | 500 | #if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) |
---|
| 501 | #define CPU_SIZEOF_POINTER 4 |
---|
| 502 | #else |
---|
| 503 | #define CPU_SIZEOF_POINTER 2 |
---|
| 504 | #endif |
---|
| 505 | |
---|
[5532553] | 506 | /* |
---|
| 507 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 508 | * alignment does not take into account the requirements for the stack. |
---|
| 509 | * |
---|
| 510 | * H8300 Specific Information: |
---|
| 511 | * |
---|
| 512 | * XXX |
---|
| 513 | */ |
---|
| 514 | |
---|
| 515 | #define CPU_ALIGNMENT 8 |
---|
| 516 | |
---|
| 517 | /* |
---|
| 518 | * This number corresponds to the byte alignment requirement for the |
---|
| 519 | * heap handler. This alignment requirement may be stricter than that |
---|
| 520 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 521 | * common for the heap to follow the same alignment requirement as |
---|
| 522 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 523 | * then this should be set to CPU_ALIGNMENT. |
---|
| 524 | * |
---|
| 525 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 526 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 527 | * |
---|
| 528 | * H8300 Specific Information: |
---|
| 529 | * |
---|
| 530 | * XXX |
---|
| 531 | */ |
---|
| 532 | |
---|
| 533 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 534 | |
---|
| 535 | /* |
---|
| 536 | * This number corresponds to the byte alignment requirement for memory |
---|
| 537 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 538 | * may be stricter than that for the data types alignment specified by |
---|
| 539 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 540 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 541 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 542 | * |
---|
| 543 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 544 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 545 | * |
---|
| 546 | * H8300 Specific Information: |
---|
| 547 | * |
---|
| 548 | * XXX |
---|
| 549 | */ |
---|
| 550 | |
---|
| 551 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 552 | |
---|
| 553 | /* |
---|
| 554 | * This number corresponds to the byte alignment requirement for the |
---|
| 555 | * stack. This alignment requirement may be stricter than that for the |
---|
| 556 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 557 | * is strict enough for the stack, then this should be set to 0. |
---|
| 558 | * |
---|
| 559 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 560 | * |
---|
| 561 | * H8300 Specific Information: |
---|
| 562 | * |
---|
| 563 | * XXX |
---|
| 564 | */ |
---|
| 565 | |
---|
| 566 | #define CPU_STACK_ALIGNMENT 2 |
---|
| 567 | |
---|
[fe7acdcf] | 568 | /* |
---|
| 569 | * ISR handler macros |
---|
| 570 | */ |
---|
| 571 | |
---|
| 572 | /* |
---|
| 573 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
| 574 | */ |
---|
| 575 | |
---|
| 576 | #define _CPU_Initialize_vectors() |
---|
[5532553] | 577 | |
---|
[fb31e1a2] | 578 | /* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. |
---|
[a58154f] | 579 | Note requires ISR_Level be uint16_t or assembler croaks. |
---|
[fb31e1a2] | 580 | */ |
---|
| 581 | |
---|
| 582 | #if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 ) |
---|
| 583 | |
---|
| 584 | |
---|
| 585 | /* |
---|
| 586 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 587 | * level is returned in _level. |
---|
| 588 | */ |
---|
| 589 | |
---|
| 590 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 591 | do { \ |
---|
[01850cde] | 592 | __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \ |
---|
[fb31e1a2] | 593 | } while (0) |
---|
| 594 | |
---|
| 595 | |
---|
| 596 | /* |
---|
[a58154f] | 597 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
[fb31e1a2] | 598 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 599 | * _level is not modified. |
---|
| 600 | */ |
---|
| 601 | |
---|
| 602 | |
---|
| 603 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 604 | do { \ |
---|
[01850cde] | 605 | __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \ |
---|
[fb31e1a2] | 606 | } while (0) |
---|
| 607 | |
---|
| 608 | |
---|
| 609 | /* |
---|
| 610 | * This temporarily restores the interrupt to _level before immediately |
---|
| 611 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 612 | * sections into two or more parts. The parameter _level is not |
---|
| 613 | * modified. |
---|
| 614 | */ |
---|
| 615 | |
---|
| 616 | |
---|
| 617 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 618 | do { \ |
---|
[01850cde] | 619 | __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \ |
---|
[fb31e1a2] | 620 | } while (0) |
---|
| 621 | |
---|
| 622 | /* end of ISR handler macros */ |
---|
| 623 | |
---|
[54ba5aa] | 624 | #else /* modern gcc version */ |
---|
[fb31e1a2] | 625 | |
---|
[5532553] | 626 | /* |
---|
| 627 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 628 | * level is returned in _level. |
---|
| 629 | * |
---|
| 630 | * H8300 Specific Information: |
---|
| 631 | * |
---|
[5bb38e15] | 632 | * XXX |
---|
[5532553] | 633 | */ |
---|
| 634 | |
---|
[54ba5aa] | 635 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
[5532553] | 636 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 637 | do { \ |
---|
| 638 | unsigned char __ccr; \ |
---|
[01850cde] | 639 | __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \ |
---|
[0c3817b] | 640 | : "=m" (__ccr) /* : "0" (__ccr) */ ); \ |
---|
[5532553] | 641 | (_isr_cookie) = __ccr; \ |
---|
[5bb38e15] | 642 | } while (0) |
---|
[54ba5aa] | 643 | #else |
---|
| 644 | #define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0 |
---|
[5532553] | 645 | #endif |
---|
| 646 | |
---|
| 647 | |
---|
| 648 | /* |
---|
[a58154f] | 649 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
[5532553] | 650 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 651 | * _level is not modified. |
---|
| 652 | * |
---|
| 653 | * H8300 Specific Information: |
---|
| 654 | * |
---|
| 655 | * XXX |
---|
| 656 | */ |
---|
| 657 | |
---|
[54ba5aa] | 658 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
[5532553] | 659 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 660 | do { \ |
---|
| 661 | unsigned char __ccr = (unsigned char) (_isr_cookie); \ |
---|
[01850cde] | 662 | __asm__ volatile( "ldc %0, ccr" : : "m" (__ccr) ); \ |
---|
[5bb38e15] | 663 | } while (0) |
---|
[54ba5aa] | 664 | #else |
---|
| 665 | #define _CPU_ISR_Enable( _isr_cookie ) |
---|
[5532553] | 666 | #endif |
---|
| 667 | |
---|
| 668 | /* |
---|
| 669 | * This temporarily restores the interrupt to _level before immediately |
---|
| 670 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 671 | * sections into two or more parts. The parameter _level is not |
---|
| 672 | * modified. |
---|
| 673 | * |
---|
| 674 | * H8300 Specific Information: |
---|
| 675 | * |
---|
| 676 | * XXX |
---|
| 677 | */ |
---|
| 678 | |
---|
[54ba5aa] | 679 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
[5532553] | 680 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 681 | do { \ |
---|
| 682 | unsigned char __ccr = (unsigned char) (_isr_cookie); \ |
---|
[01850cde] | 683 | __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \ |
---|
[5bb38e15] | 684 | } while (0) |
---|
[54ba5aa] | 685 | #else |
---|
| 686 | #define _CPU_ISR_Flash( _isr_cookie ) |
---|
[5532553] | 687 | #endif |
---|
| 688 | |
---|
[fb31e1a2] | 689 | #endif /* end of old gcc */ |
---|
| 690 | |
---|
[5532553] | 691 | |
---|
| 692 | /* |
---|
| 693 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 694 | * actually provides. Currently, interrupt levels which do not |
---|
| 695 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 696 | * it would be nice if these were "mapped" by the application |
---|
| 697 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 698 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 699 | * This could be used to manage a programmable interrupt controller |
---|
| 700 | * via the rtems_task_mode directive. |
---|
| 701 | * |
---|
| 702 | * H8300 Specific Information: |
---|
| 703 | * |
---|
| 704 | * XXX |
---|
| 705 | */ |
---|
| 706 | |
---|
| 707 | #define _CPU_ISR_Set_level( _new_level ) \ |
---|
| 708 | { \ |
---|
[01850cde] | 709 | if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \ |
---|
| 710 | else __asm__ volatile ( "andc #0x7f,ccr\n" ); \ |
---|
[5532553] | 711 | } |
---|
| 712 | |
---|
[4ac56fbb] | 713 | #ifndef ASM |
---|
| 714 | |
---|
[c346f33d] | 715 | uint32_t _CPU_ISR_Get_level( void ); |
---|
[5532553] | 716 | |
---|
| 717 | /* end of ISR handler macros */ |
---|
| 718 | |
---|
| 719 | /* Context handler macros */ |
---|
| 720 | |
---|
| 721 | /* |
---|
| 722 | * Initialize the context to a state suitable for starting a |
---|
| 723 | * task after a context restore operation. Generally, this |
---|
| 724 | * involves: |
---|
| 725 | * |
---|
| 726 | * - setting a starting address |
---|
| 727 | * - preparing the stack |
---|
| 728 | * - preparing the stack and frame pointers |
---|
| 729 | * - setting the proper interrupt level in the context |
---|
| 730 | * - initializing the floating point context |
---|
| 731 | * |
---|
| 732 | * This routine generally does not set any unnecessary register |
---|
| 733 | * in the context. The state of the "general data" registers is |
---|
| 734 | * undefined at task start time. |
---|
| 735 | * |
---|
| 736 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
| 737 | * point thread. This is typically only used on CPUs where the |
---|
| 738 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 739 | * where the PSR contains an enable FPU bit. |
---|
| 740 | * |
---|
| 741 | * H8300 Specific Information: |
---|
| 742 | * |
---|
| 743 | * XXX |
---|
| 744 | */ |
---|
| 745 | |
---|
| 746 | |
---|
| 747 | #define CPU_CCR_INTERRUPTS_ON 0x80 |
---|
| 748 | #define CPU_CCR_INTERRUPTS_OFF 0x00 |
---|
| 749 | |
---|
| 750 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
| 751 | _isr, _entry_point, _is_fp ) \ |
---|
| 752 | /* Locate Me */ \ |
---|
| 753 | do { \ |
---|
[2146dbac] | 754 | uintptr_t _stack; \ |
---|
[5532553] | 755 | \ |
---|
| 756 | if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ |
---|
| 757 | else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ |
---|
| 758 | \ |
---|
[2146dbac] | 759 | _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \ |
---|
[5532553] | 760 | *((proc_ptr *)(_stack)) = (_entry_point); \ |
---|
| 761 | (_the_context)->er7 = (void *) _stack; \ |
---|
| 762 | (_the_context)->er6 = (void *) _stack; \ |
---|
| 763 | (_the_context)->er5 = 0; \ |
---|
| 764 | (_the_context)->er4 = 1; \ |
---|
| 765 | (_the_context)->er3 = 2; \ |
---|
| 766 | } while (0) |
---|
| 767 | |
---|
| 768 | |
---|
| 769 | /* |
---|
| 770 | * This routine is responsible for somehow restarting the currently |
---|
| 771 | * executing task. If you are lucky, then all that is necessary |
---|
| 772 | * is restoring the context. Otherwise, there will need to be |
---|
| 773 | * a special assembly routine which does something special in this |
---|
| 774 | * case. Context_Restore should work most of the time. It will |
---|
| 775 | * not work if restarting self conflicts with the stack frame |
---|
| 776 | * assumptions of restoring a context. |
---|
| 777 | * |
---|
| 778 | * H8300 Specific Information: |
---|
| 779 | * |
---|
| 780 | * XXX |
---|
| 781 | */ |
---|
| 782 | |
---|
| 783 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 784 | _CPU_Context_restore( (_the_context) ); |
---|
| 785 | |
---|
| 786 | /* |
---|
| 787 | * The purpose of this macro is to allow the initial pointer into |
---|
| 788 | * a floating point context area (used to save the floating point |
---|
| 789 | * context) to be at an arbitrary place in the floating point |
---|
| 790 | * context area. |
---|
| 791 | * |
---|
| 792 | * This is necessary because some FP units are designed to have |
---|
| 793 | * their context saved as a stack which grows into lower addresses. |
---|
| 794 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 795 | * from the base of the context area. Finally some FP units provide |
---|
| 796 | * a "dump context" instruction which could fill in from high to low |
---|
| 797 | * or low to high based on the whim of the CPU designers. |
---|
| 798 | * |
---|
| 799 | * H8300 Specific Information: |
---|
| 800 | * |
---|
| 801 | * XXX |
---|
| 802 | */ |
---|
| 803 | |
---|
| 804 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 805 | ( (void *) (_base) + (_offset) ) |
---|
| 806 | |
---|
| 807 | /* |
---|
| 808 | * This routine initializes the FP context area passed to it to. |
---|
| 809 | * There are a few standard ways in which to initialize the |
---|
| 810 | * floating point context. The code included for this macro assumes |
---|
| 811 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 812 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 813 | * context passed to it. |
---|
| 814 | * |
---|
| 815 | * Other models include (1) not doing anything, and (2) putting |
---|
| 816 | * a "null FP status word" in the correct place in the FP context. |
---|
| 817 | * |
---|
| 818 | * H8300 Specific Information: |
---|
| 819 | * |
---|
| 820 | * XXX |
---|
| 821 | */ |
---|
| 822 | |
---|
| 823 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 824 | { \ |
---|
[ce1093e] | 825 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
[5532553] | 826 | } |
---|
| 827 | |
---|
| 828 | /* end of Context handler macros */ |
---|
| 829 | |
---|
| 830 | /* Fatal Error manager macros */ |
---|
| 831 | |
---|
| 832 | /* |
---|
| 833 | * This routine copies _error into a known place -- typically a stack |
---|
| 834 | * location or a register, optionally disables interrupts, and |
---|
| 835 | * halts/stops the CPU. |
---|
| 836 | * |
---|
| 837 | * H8300 Specific Information: |
---|
| 838 | * |
---|
| 839 | * XXX |
---|
| 840 | */ |
---|
| 841 | |
---|
| 842 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 843 | printk("Fatal Error %d Halted\n",_error); \ |
---|
[5bb38e15] | 844 | for(;;) |
---|
| 845 | |
---|
[5532553] | 846 | |
---|
| 847 | /* end of Fatal Error manager macros */ |
---|
| 848 | |
---|
| 849 | /* Bitfield handler macros */ |
---|
| 850 | |
---|
| 851 | /* |
---|
| 852 | * This routine sets _output to the bit number of the first bit |
---|
[4ef13360] | 853 | * set in _value. _value is of CPU dependent type Priority_bit_map_Control. |
---|
[5532553] | 854 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 855 | * least significant bits will be used. |
---|
| 856 | * |
---|
| 857 | * There are a number of variables in using a "find first bit" type |
---|
| 858 | * instruction. |
---|
| 859 | * |
---|
| 860 | * (1) What happens when run on a value of zero? |
---|
| 861 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 862 | * (3) The numbering may be zero or one based. |
---|
| 863 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 864 | * |
---|
| 865 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 866 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 867 | * _CPU_Priority_bits_index(). These three form a set of routines |
---|
| 868 | * which must logically operate together. Bits in the _value are |
---|
| 869 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 870 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 871 | * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() |
---|
| 872 | * to properly range between the values returned by the "find first bit" |
---|
| 873 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 874 | * calculate the major and directly index into the minor table. |
---|
| 875 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 876 | * is the first bit found. |
---|
| 877 | * |
---|
| 878 | * This entire "find first bit" and mapping process depends heavily |
---|
| 879 | * on the manner in which a priority is broken into a major and minor |
---|
| 880 | * components with the major being the 4 MSB of a priority and minor |
---|
| 881 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 882 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 883 | * to the lowest priority. |
---|
| 884 | * |
---|
| 885 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 886 | * there are ways to make do without it. Here are a handful of ways |
---|
| 887 | * to implement this in software: |
---|
| 888 | * |
---|
| 889 | * - a series of 16 bit test instructions |
---|
| 890 | * - a "binary search using if's" |
---|
| 891 | * - _number = 0 |
---|
| 892 | * if _value > 0x00ff |
---|
| 893 | * _value >>=8 |
---|
| 894 | * _number = 8; |
---|
| 895 | * |
---|
| 896 | * if _value > 0x0000f |
---|
| 897 | * _value >=8 |
---|
| 898 | * _number += 4 |
---|
| 899 | * |
---|
| 900 | * _number += bit_set_table[ _value ] |
---|
| 901 | * |
---|
| 902 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 903 | * bit set |
---|
| 904 | * |
---|
| 905 | * H8300 Specific Information: |
---|
| 906 | * |
---|
| 907 | * XXX |
---|
| 908 | */ |
---|
| 909 | |
---|
| 910 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 911 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 912 | |
---|
| 913 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 914 | |
---|
| 915 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 916 | { \ |
---|
| 917 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
| 918 | } |
---|
| 919 | |
---|
| 920 | #endif |
---|
| 921 | |
---|
| 922 | /* end of Bitfield handler macros */ |
---|
| 923 | |
---|
| 924 | /* |
---|
| 925 | * This routine builds the mask which corresponds to the bit fields |
---|
| 926 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 927 | * for that routine. |
---|
| 928 | * |
---|
| 929 | * H8300 Specific Information: |
---|
| 930 | * |
---|
| 931 | * XXX |
---|
| 932 | */ |
---|
| 933 | |
---|
| 934 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 935 | |
---|
| 936 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 937 | ( 1 << (_bit_number) ) |
---|
| 938 | |
---|
| 939 | #endif |
---|
| 940 | |
---|
| 941 | /* |
---|
| 942 | * This routine translates the bit numbers returned by |
---|
| 943 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 944 | * a major or minor component of a priority. See the discussion |
---|
| 945 | * for that routine. |
---|
| 946 | * |
---|
| 947 | * H8300 Specific Information: |
---|
| 948 | * |
---|
| 949 | * XXX |
---|
| 950 | */ |
---|
| 951 | |
---|
| 952 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 953 | |
---|
| 954 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 955 | (_priority) |
---|
| 956 | |
---|
| 957 | #endif |
---|
| 958 | |
---|
| 959 | /* end of Priority handler macros */ |
---|
| 960 | |
---|
| 961 | /* functions */ |
---|
| 962 | |
---|
| 963 | /* |
---|
| 964 | * _CPU_Initialize |
---|
| 965 | * |
---|
| 966 | * This routine performs CPU dependent initialization. |
---|
| 967 | * |
---|
| 968 | * H8300 Specific Information: |
---|
| 969 | * |
---|
| 970 | * XXX |
---|
| 971 | */ |
---|
| 972 | |
---|
[c03e2bc] | 973 | void _CPU_Initialize(void); |
---|
[5532553] | 974 | |
---|
| 975 | /* |
---|
| 976 | * _CPU_ISR_install_raw_handler |
---|
| 977 | * |
---|
[5bb38e15] | 978 | * This routine installs a "raw" interrupt handler directly into the |
---|
[5532553] | 979 | * processor's vector table. |
---|
| 980 | * |
---|
| 981 | * H8300 Specific Information: |
---|
| 982 | * |
---|
| 983 | * XXX |
---|
| 984 | */ |
---|
[5bb38e15] | 985 | |
---|
[5532553] | 986 | void _CPU_ISR_install_raw_handler( |
---|
[c346f33d] | 987 | uint32_t vector, |
---|
[5532553] | 988 | proc_ptr new_handler, |
---|
| 989 | proc_ptr *old_handler |
---|
| 990 | ); |
---|
| 991 | |
---|
| 992 | /* |
---|
| 993 | * _CPU_ISR_install_vector |
---|
| 994 | * |
---|
| 995 | * This routine installs an interrupt vector. |
---|
| 996 | * |
---|
| 997 | * H8300 Specific Information: |
---|
| 998 | * |
---|
| 999 | * XXX |
---|
| 1000 | */ |
---|
| 1001 | |
---|
| 1002 | void _CPU_ISR_install_vector( |
---|
[c346f33d] | 1003 | uint32_t vector, |
---|
[5532553] | 1004 | proc_ptr new_handler, |
---|
| 1005 | proc_ptr *old_handler |
---|
| 1006 | ); |
---|
| 1007 | |
---|
| 1008 | /* |
---|
| 1009 | * _CPU_Install_interrupt_stack |
---|
| 1010 | * |
---|
| 1011 | * This routine installs the hardware interrupt stack pointer. |
---|
| 1012 | * |
---|
| 1013 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 1014 | * is TRUE. |
---|
| 1015 | * |
---|
| 1016 | * H8300 Specific Information: |
---|
| 1017 | * |
---|
| 1018 | * XXX |
---|
| 1019 | */ |
---|
| 1020 | |
---|
| 1021 | void _CPU_Install_interrupt_stack( void ); |
---|
| 1022 | |
---|
| 1023 | /* |
---|
| 1024 | * _CPU_Internal_threads_Idle_thread_body |
---|
| 1025 | * |
---|
| 1026 | * This routine is the CPU dependent IDLE thread body. |
---|
| 1027 | * |
---|
| 1028 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 1029 | * is TRUE. |
---|
| 1030 | * |
---|
| 1031 | * H8300 Specific Information: |
---|
| 1032 | * |
---|
| 1033 | * XXX |
---|
| 1034 | */ |
---|
| 1035 | |
---|
[3c87adba] | 1036 | void *_CPU_Thread_Idle_body( uint32_t ); |
---|
[5532553] | 1037 | |
---|
| 1038 | /* |
---|
| 1039 | * _CPU_Context_switch |
---|
| 1040 | * |
---|
| 1041 | * This routine switches from the run context to the heir context. |
---|
| 1042 | * |
---|
| 1043 | * H8300 Specific Information: |
---|
| 1044 | * |
---|
| 1045 | * XXX |
---|
| 1046 | */ |
---|
| 1047 | |
---|
| 1048 | void _CPU_Context_switch( |
---|
| 1049 | Context_Control *run, |
---|
| 1050 | Context_Control *heir |
---|
| 1051 | ); |
---|
| 1052 | |
---|
| 1053 | /* |
---|
| 1054 | * _CPU_Context_restore |
---|
| 1055 | * |
---|
| 1056 | * This routine is generallu used only to restart self in an |
---|
| 1057 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 1058 | * |
---|
| 1059 | * NOTE: May be unnecessary to reload some registers. |
---|
| 1060 | * |
---|
| 1061 | * H8300 Specific Information: |
---|
| 1062 | * |
---|
| 1063 | * XXX |
---|
| 1064 | */ |
---|
| 1065 | |
---|
| 1066 | void _CPU_Context_restore( |
---|
| 1067 | Context_Control *new_context |
---|
[479cbaf8] | 1068 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
[5532553] | 1069 | |
---|
| 1070 | /* |
---|
| 1071 | * _CPU_Context_save_fp |
---|
| 1072 | * |
---|
| 1073 | * This routine saves the floating point context passed to it. |
---|
| 1074 | * |
---|
| 1075 | * H8300 Specific Information: |
---|
| 1076 | * |
---|
| 1077 | * XXX |
---|
| 1078 | */ |
---|
| 1079 | |
---|
| 1080 | void _CPU_Context_save_fp( |
---|
[ce1093e] | 1081 | Context_Control_fp **fp_context_ptr |
---|
[5532553] | 1082 | ); |
---|
| 1083 | |
---|
| 1084 | /* |
---|
| 1085 | * _CPU_Context_restore_fp |
---|
| 1086 | * |
---|
| 1087 | * This routine restores the floating point context passed to it. |
---|
| 1088 | * |
---|
| 1089 | * H8300 Specific Information: |
---|
| 1090 | * |
---|
| 1091 | * XXX |
---|
| 1092 | */ |
---|
| 1093 | |
---|
| 1094 | void _CPU_Context_restore_fp( |
---|
[ce1093e] | 1095 | Context_Control_fp **fp_context_ptr |
---|
[5532553] | 1096 | ); |
---|
| 1097 | |
---|
[815994f] | 1098 | /* FIXME */ |
---|
| 1099 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
---|
| 1100 | |
---|
| 1101 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
| 1102 | |
---|
[5532553] | 1103 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 1104 | * It must be static because it is referenced indirectly. |
---|
| 1105 | * |
---|
| 1106 | * This version will work on any processor, but if there is a better |
---|
| 1107 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 1108 | * |
---|
| 1109 | * swap least significant two bytes with 16-bit rotate |
---|
| 1110 | * swap upper and lower 16-bits |
---|
| 1111 | * swap most significant two bytes with 16-bit rotate |
---|
| 1112 | * |
---|
| 1113 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 1114 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 1115 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[ece004d] | 1116 | * that interrupts would probably have to be disabled to ensure that |
---|
[5532553] | 1117 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 1118 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 1119 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 1120 | * will be fetched incorrectly. |
---|
| 1121 | * |
---|
| 1122 | * H8300 Specific Information: |
---|
| 1123 | * |
---|
[f6c6bc8f] | 1124 | * This is the generic implementation. |
---|
[5532553] | 1125 | */ |
---|
[5bb38e15] | 1126 | |
---|
[c346f33d] | 1127 | static inline uint32_t CPU_swap_u32( |
---|
| 1128 | uint32_t value |
---|
[5532553] | 1129 | ) |
---|
| 1130 | { |
---|
[c346f33d] | 1131 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[5bb38e15] | 1132 | |
---|
[5532553] | 1133 | byte4 = (value >> 24) & 0xff; |
---|
| 1134 | byte3 = (value >> 16) & 0xff; |
---|
| 1135 | byte2 = (value >> 8) & 0xff; |
---|
| 1136 | byte1 = value & 0xff; |
---|
[5bb38e15] | 1137 | |
---|
[5532553] | 1138 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
| 1139 | return( swapped ); |
---|
| 1140 | } |
---|
| 1141 | |
---|
[f6c6bc8f] | 1142 | #define CPU_swap_u16( value ) \ |
---|
| 1143 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 1144 | |
---|
[f94470a5] | 1145 | /* to be provided by the BSP */ |
---|
| 1146 | extern void H8BD_Install_IRQ( |
---|
[c346f33d] | 1147 | uint32_t vector, |
---|
[f94470a5] | 1148 | proc_ptr new_handler, |
---|
| 1149 | proc_ptr *old_handler ); |
---|
| 1150 | |
---|
[4ac56fbb] | 1151 | #endif /* ASM */ |
---|
| 1152 | |
---|
[5532553] | 1153 | #ifdef __cplusplus |
---|
| 1154 | } |
---|
| 1155 | #endif |
---|
| 1156 | |
---|
| 1157 | #endif |
---|