1 | /* |
---|
2 | * Hitachi H8 Score CPU functions |
---|
3 | * Copyright Comnet Technologies Ltd 1999 |
---|
4 | * |
---|
5 | * Based on example code and other ports with this copyright: |
---|
6 | * |
---|
7 | * COPYRIGHT (c) 1989-1999. |
---|
8 | * On-Line Applications Research Corporation (OAR). |
---|
9 | * |
---|
10 | * The license and distribution terms for this file may be |
---|
11 | * found in the file LICENSE in this distribution or at |
---|
12 | * http://www.OARcorp.com/rtems/license.html. |
---|
13 | * |
---|
14 | * $Id$ |
---|
15 | */ |
---|
16 | |
---|
17 | |
---|
18 | ;.equ RUNCONTEXT_ARG, er0 |
---|
19 | ;.equ HEIRCONTEXT_ARG, er1 |
---|
20 | |
---|
21 | /* |
---|
22 | * Make sure we tell the assembler what type of CPU model we are |
---|
23 | * being compiled for. |
---|
24 | */ |
---|
25 | |
---|
26 | #if defined(__H8300H__) |
---|
27 | .h8300h |
---|
28 | #endif |
---|
29 | #if defined(__H8300S__) |
---|
30 | .h8300s |
---|
31 | #endif |
---|
32 | .text |
---|
33 | |
---|
34 | .text |
---|
35 | /* |
---|
36 | GCC Compiled with optimisations and Wimplicit decs to ensure |
---|
37 | that stack from doesn't change |
---|
38 | |
---|
39 | Supposedly R2 and R3 do not need to be saved but who knows |
---|
40 | |
---|
41 | Arg1 = er0 (not on stack) |
---|
42 | Arg2 = er1 (not on stack) |
---|
43 | */ |
---|
44 | |
---|
45 | .align 2 |
---|
46 | |
---|
47 | .global __CPU_Context_switch |
---|
48 | |
---|
49 | __CPU_Context_switch: |
---|
50 | /* Save Context */ |
---|
51 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
52 | stc.w ccr,@(0:16,er0) |
---|
53 | mov.l er7,@(2:16,er0) |
---|
54 | mov.l er6,@(6:16,er0) |
---|
55 | mov.l er5,@(10:16,er0) |
---|
56 | mov.l er4,@(14:16,er0) |
---|
57 | mov.l er3,@(18:16,er0) |
---|
58 | mov.l er2,@(22:16,er0) |
---|
59 | |
---|
60 | /* Install New context */ |
---|
61 | |
---|
62 | restore: |
---|
63 | mov.l @(22:16,er1),er2 |
---|
64 | mov.l @(18:16,er1),er3 |
---|
65 | mov.l @(14:16,er1),er4 |
---|
66 | mov.l @(10:16,er1),er5 |
---|
67 | mov.l @(6:16,er1),er6 |
---|
68 | mov.l @(2:16,er1),er7 |
---|
69 | ldc.w @(0:16,er1),ccr |
---|
70 | #endif |
---|
71 | |
---|
72 | rts |
---|
73 | |
---|
74 | .align 2 |
---|
75 | |
---|
76 | .global __CPU_Context_restore |
---|
77 | |
---|
78 | __CPU_Context_restore: |
---|
79 | |
---|
80 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
81 | mov.l er0,er1 |
---|
82 | jmp @restore:24 |
---|
83 | #endif |
---|
84 | |
---|
85 | |
---|
86 | |
---|
87 | /* |
---|
88 | VHandler for Vectored Interrupts |
---|
89 | |
---|
90 | All IRQ's are vectored to routine _ISR_#vector_number |
---|
91 | This routine stacks er0 and loads er0 with vector number |
---|
92 | before transferring to here |
---|
93 | |
---|
94 | */ |
---|
95 | .align 2 |
---|
96 | .global __ISR_Handler |
---|
97 | .extern __ISR_Nest_level |
---|
98 | .extern __Vector_table |
---|
99 | .extern __Context_switch_necessary |
---|
100 | |
---|
101 | |
---|
102 | __ISR_Handler: |
---|
103 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
104 | mov.l er1,@-er7 |
---|
105 | mov.l er2,@-er7 |
---|
106 | mov.l er3,@-er7 |
---|
107 | mov.l er4,@-er7 |
---|
108 | mov.l er5,@-er7 |
---|
109 | mov.l er6,@-er7 |
---|
110 | |
---|
111 | /* Set IRQ Stack */ |
---|
112 | orc #0xc0,ccr |
---|
113 | mov.l er7,er6 ; save stack pointer |
---|
114 | mov.l @__ISR_Nest_level,er1 |
---|
115 | bne nested |
---|
116 | mov.l @__CPU_Interrupt_stack_high,er7 |
---|
117 | |
---|
118 | nested: |
---|
119 | mov.l er6,@-er7 ; save sp so pop regardless of nest level |
---|
120 | |
---|
121 | ;; Inc system counters |
---|
122 | mov.l @__ISR_Nest_level,er1 |
---|
123 | inc.l #1,er1 |
---|
124 | mov.l er1,@__ISR_Nest_level |
---|
125 | mov.l @__Thread_Dispatch_disable_level,er1 |
---|
126 | inc.l #1,er1 |
---|
127 | mov.l er1,@__Thread_Dispatch_disable_level |
---|
128 | |
---|
129 | /* Vector to ISR */ |
---|
130 | |
---|
131 | mov.l @__ISR_Vector_table,er1 |
---|
132 | mov er0,er2 ; copy vector |
---|
133 | shll.l er2 |
---|
134 | shll.l er2 ; vector = vector * 4 (sizeof(int)) |
---|
135 | add.l er2,er1 |
---|
136 | mov.l @er1,er1 |
---|
137 | jsr @er1 ; er0 = arg1 =vector |
---|
138 | |
---|
139 | orc #0xc0,ccr |
---|
140 | mov.l @__ISR_Nest_level,er1 |
---|
141 | dec.l #1,er1 |
---|
142 | mov.l er1,@__ISR_Nest_level |
---|
143 | mov.l @__Thread_Dispatch_disable_level,er1 |
---|
144 | dec.l #1,er1 |
---|
145 | mov.l er1,@__Thread_Dispatch_disable_level |
---|
146 | bne exit |
---|
147 | |
---|
148 | mov.l @__Context_Switch_necessary,er1 |
---|
149 | bne bframe ; If yes then dispatch next task |
---|
150 | |
---|
151 | mov.l @__ISR_Signals_to_thread_executing,er1 |
---|
152 | beq exit ; If no signals waiting |
---|
153 | |
---|
154 | /* Context switch here through ISR_Dispatch */ |
---|
155 | |
---|
156 | bframe: |
---|
157 | orc #0xc0,ccr |
---|
158 | /* Pop Stack */ |
---|
159 | mov @er7+,er6 |
---|
160 | mov er6,er7 |
---|
161 | mov.l #0,er2 |
---|
162 | mov.l er2,@__ISR_Signals_to_thread_executing |
---|
163 | |
---|
164 | /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */ |
---|
165 | |
---|
166 | mov.l #0xc0000000,er2 /* Disable IRQ */ |
---|
167 | or.l #_ISR_Dispatch,er2 |
---|
168 | mov.l er2,@-er7 |
---|
169 | rte |
---|
170 | |
---|
171 | /* Inner IRQ Return, pop flags and return */ |
---|
172 | exit: |
---|
173 | /* Pop Stack */ |
---|
174 | orc #0x80,ccr |
---|
175 | mov @er7+,er6 |
---|
176 | mov er6,er7 |
---|
177 | mov @er7+,er6 |
---|
178 | mov @er7+,er5 |
---|
179 | mov @er7+,er4 |
---|
180 | mov @er7+,er3 |
---|
181 | mov @er7+,er2 |
---|
182 | mov @er7+,er1 |
---|
183 | mov @er7+,er0 |
---|
184 | #endif |
---|
185 | rte |
---|
186 | |
---|
187 | /* |
---|
188 | Called from ISR_Handler as a way of ending IRQ |
---|
189 | but allowing dispatch to another task. |
---|
190 | Must use RTE as CCR is still on stack but IRQ has been serviced. |
---|
191 | CCR and PC occupy same word so rte can be used. |
---|
192 | now using task stack |
---|
193 | */ |
---|
194 | |
---|
195 | .align 2 |
---|
196 | .global _ISR_Dispatch |
---|
197 | |
---|
198 | _ISR_Dispatch: |
---|
199 | |
---|
200 | #if defined(__H8300H__) || defined(__H8300S__) |
---|
201 | jsr @__Thread_Dispatch |
---|
202 | mov @er7+,er6 |
---|
203 | mov @er7+,er5 |
---|
204 | mov @er7+,er4 |
---|
205 | mov @er7+,er3 |
---|
206 | mov @er7+,er2 |
---|
207 | mov @er7+,er1 |
---|
208 | mov @er7+,er0 |
---|
209 | #endif |
---|
210 | rte |
---|
211 | |
---|
212 | |
---|
213 | .align 2 |
---|
214 | .global __CPU_Context_save_fp |
---|
215 | |
---|
216 | __CPU_Context_save_fp: |
---|
217 | rts |
---|
218 | |
---|
219 | |
---|
220 | .align 2 |
---|
221 | .global __CPU_Context_restore_fp |
---|
222 | |
---|
223 | __CPU_Context_restore_fp: |
---|
224 | rts |
---|
225 | |
---|