source: rtems/cpukit/score/cpu/h8300/cpu_asm.S @ 03b7789

4.11
Last change on this file since 03b7789 was 03b7789, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 26, 2014 at 1:09:10 PM

score: Statically initialize _ISR_Vector_table

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 * Hitachi H8 Score CPU functions
3 *   Copyright Comnet Technologies Ltd 1999
4 *
5 *  Based on example code and other ports with this copyright:
6 *
7 *  COPYRIGHT (c) 1989-1999.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16#include "config.h"
17#endif
18
19#include <rtems/asm.h>
20#include <rtems/score/percpu.h>
21
22;.equ   RUNCONTEXT_ARG,  er0
23;.equ   HEIRCONTEXT_ARG, er1
24       
25/*
26 *  Make sure we tell the assembler what type of CPU model we are
27 *  being compiled for.
28 */
29
30#if defined(__H8300H__)
31        .h8300h
32#endif
33#if defined(__H8300S__)
34        .h8300s
35#endif
36#if defined(__H8300SX__)
37        .h8300sx
38#endif
39        .text
40
41        .text
42/*
43        GCC Compiled with optimisations and Wimplicit decs to ensure
44    that stack from doesn't change
45       
46        Supposedly R2 and R3 do not need to be saved but who knows
47       
48        Arg1 = er0      (not on stack)
49        Arg2 = er1      (not on stack)
50*/
51
52        .align 2
53
54        .global SYM(_CPU_Context_switch)
55
56SYM(_CPU_Context_switch):
57        /* Save Context */
58#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
59        stc.w   ccr,@(0:16,er0)
60        mov.l   er7,@(2:16,er0)
61        mov.l   er6,@(6:16,er0)
62        mov.l   er5,@(10:16,er0)
63        mov.l   er4,@(14:16,er0)
64        mov.l   er3,@(18:16,er0)
65        mov.l   er2,@(22:16,er0)
66
67        /* Install New context */
68
69restore:
70        mov.l   @(22:16,er1),er2
71        mov.l   @(18:16,er1),er3
72        mov.l   @(14:16,er1),er4
73        mov.l   @(10:16,er1),er5
74        mov.l   @(6:16,er1),er6
75        mov.l   @(2:16,er1),er7
76        ldc.w   @(0:16,er1),ccr
77#endif
78
79        rts
80
81        .align 2
82
83        .global SYM(_CPU_Context_restore)
84
85SYM(_CPU_Context_restore):
86       
87#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
88        mov.l   er0,er1
89        jmp             @restore:24
90#endif
91
92
93
94/*
95        VHandler for Vectored Interrupts
96       
97        All IRQ's are vectored to routine _ISR_#vector_number
98        This routine stacks er0 and loads er0 with vector number
99        before transferring to here
100       
101*/
102        .align 2
103        .global SYM(_ISR_Handler)
104        .extern SYM(_Vector_table)
105
106       
107SYM(_ISR_Handler):
108#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
109        mov.l   er1,@-er7
110        mov.l   er2,@-er7
111        mov.l   er3,@-er7
112        mov.l   er4,@-er7
113        mov.l   er5,@-er7
114        mov.l   er6,@-er7
115       
116/*  Set IRQ Stack */
117        orc             #0xc0,ccr
118        mov.l   er7,er6         ; save stack pointer
119        mov.l   @ISR_NEST_LEVEL,er1
120        bne             nested
121        mov.l   @INTERRUPT_STACK_HIGH,er7
122       
123nested:
124        mov.l   er6,@-er7       ; save sp so pop regardless of nest level
125       
126;; Inc  system counters
127        mov.l   @ISR_NEST_LEVEL,er1
128        inc.l   #1,er1
129        mov.l   er1,@ISR_NEST_LEVEL
130        mov.l   @THREAD_DISPATCH_DISABLE_LEVEL,er1
131        inc.l   #1,er1
132        mov.l   er1,@THREAD_DISPATCH_DISABLE_LEVEL
133       
134/* Vector to ISR */
135
136        mov             er0,er2 ; copy vector
137        shll.l  er2
138        shll.l  er2             ; vector = vector * 4 (sizeof(int))
139        mov.l   @(SYM(_ISR_Vector_table), er2),er1
140        jsr             @er1    ; er0 = arg1 =vector
141       
142        orc             #0xc0,ccr
143        mov.l   @ISR_NEST_LEVEL,er1
144        dec.l   #1,er1
145        mov.l   er1,@ISR_NEST_LEVEL
146        mov.l   @THREAD_DISPATCH_DISABLE_LEVEL,er1
147        dec.l   #1,er1
148        mov.l   er1,@THREAD_DISPATCH_DISABLE_LEVEL
149        bne     exit
150       
151        mov.b   @DISPATCH_NEEDED,er1
152        beq     exit            ; If no then exit
153
154        /* Context switch here through ISR_Dispatch */
155bframe:
156        orc     #0xc0,ccr
157/*      Pop Stack       */
158        mov     @er7+,er6
159        mov     er6,er7
160
161        /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
162       
163        mov.l   #0xc0000000,er2         /* Disable IRQ */
164        or.l    #SYM(_ISR_Dispatch),er2
165        mov.l   er2,@-er7
166        rte
167
168/*      Inner IRQ Return, pop flags and return */
169exit:
170/*      Pop Stack       */
171        orc             #0x80,ccr
172        mov             @er7+,er6
173        mov             er6,er7
174        mov             @er7+,er6
175        mov             @er7+,er5
176        mov             @er7+,er4
177        mov             @er7+,er3
178        mov             @er7+,er2
179        mov             @er7+,er1
180        mov             @er7+,er0
181#endif
182        rte
183       
184/*
185        Called from ISR_Handler as a way of ending IRQ
186        but allowing dispatch to another task.
187        Must use RTE as CCR is still on stack but IRQ has been serviced.       
188        CCR and PC occupy same word so rte can be used.
189        now using task stack
190*/
191
192        .align 2
193        .global SYM(_ISR_Dispatch)
194
195SYM(_ISR_Dispatch):
196       
197#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
198        jsr             @SYM(_Thread_Dispatch)
199        mov             @er7+,er6
200        mov             @er7+,er5
201        mov             @er7+,er4
202        mov             @er7+,er3
203        mov             @er7+,er2
204        mov             @er7+,er1
205        mov             @er7+,er0
206#endif
207        rte
208       
209
210        .align 2
211        .global SYM(_CPU_Context_save_fp)
212
213SYM(_CPU_Context_save_fp):
214        rts
215
216
217        .align 2
218        .global SYM(_CPU_Context_restore_fp)
219
220SYM(_CPU_Context_restore_fp):
221        rts
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