[5532553] | 1 | /* |
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| 2 | * Hitachi H8 Score CPU functions |
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| 3 | * Copyright Comnet Technologies Ltd 1999 |
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| 4 | * |
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| 5 | * Based on example code and other ports with this copyright: |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1999. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[a97f3776] | 12 | * http://www.rtems.com/license/LICENSE. |
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[5532553] | 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | |
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| 18 | ;.equ RUNCONTEXT_ARG, er0 |
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| 19 | ;.equ HEIRCONTEXT_ARG, er1 |
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| 20 | |
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[fb31e1a2] | 21 | /* |
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[5532553] | 22 | * Make sure we tell the assembler what type of CPU model we are |
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| 23 | * being compiled for. |
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[fb31e1a2] | 24 | */ |
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[5532553] | 25 | |
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| 26 | #if defined(__H8300H__) |
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[fb31e1a2] | 27 | .h8300h |
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[5532553] | 28 | #endif |
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[fb31e1a2] | 29 | #if defined(__H8300S__) |
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| 30 | .h8300s |
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[5532553] | 31 | #endif |
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[fb31e1a2] | 32 | .text |
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[5532553] | 33 | |
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[fb31e1a2] | 34 | .text |
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[5532553] | 35 | /* |
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| 36 | GCC Compiled with optimisations and Wimplicit decs to ensure |
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| 37 | that stack from doesn't change |
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| 38 | |
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| 39 | Supposedly R2 and R3 do not need to be saved but who knows |
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| 40 | |
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| 41 | Arg1 = er0 (not on stack) |
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| 42 | Arg2 = er1 (not on stack) |
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| 43 | */ |
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| 44 | |
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| 45 | .align 2 |
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[fb31e1a2] | 46 | |
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[5532553] | 47 | .global __CPU_Context_switch |
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[fb31e1a2] | 48 | |
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[5532553] | 49 | __CPU_Context_switch: |
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| 50 | /* Save Context */ |
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[54ba5aa] | 51 | #if defined(__H8300H__) || defined(__H8300S__) |
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[fb31e1a2] | 52 | stc.w ccr,@(0:16,er0) |
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[5532553] | 53 | mov.l er7,@(2:16,er0) |
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| 54 | mov.l er6,@(6:16,er0) |
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| 55 | mov.l er5,@(10:16,er0) |
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| 56 | mov.l er4,@(14:16,er0) |
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| 57 | mov.l er3,@(18:16,er0) |
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| 58 | mov.l er2,@(22:16,er0) |
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| 59 | |
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| 60 | /* Install New context */ |
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| 61 | |
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| 62 | restore: |
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| 63 | mov.l @(22:16,er1),er2 |
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| 64 | mov.l @(18:16,er1),er3 |
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| 65 | mov.l @(14:16,er1),er4 |
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| 66 | mov.l @(10:16,er1),er5 |
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| 67 | mov.l @(6:16,er1),er6 |
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| 68 | mov.l @(2:16,er1),er7 |
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[fb31e1a2] | 69 | ldc.w @(0:16,er1),ccr |
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[54ba5aa] | 70 | #endif |
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[fb31e1a2] | 71 | |
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[5532553] | 72 | rts |
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| 73 | |
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| 74 | .align 2 |
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[fb31e1a2] | 75 | |
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[5532553] | 76 | .global __CPU_Context_restore |
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[fb31e1a2] | 77 | |
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[5532553] | 78 | __CPU_Context_restore: |
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[fb31e1a2] | 79 | |
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[54ba5aa] | 80 | #if defined(__H8300H__) || defined(__H8300S__) |
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| 81 | mov.l er0,er1 |
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[fb31e1a2] | 82 | jmp @restore:24 |
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[54ba5aa] | 83 | #endif |
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[5532553] | 84 | |
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| 85 | |
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| 86 | |
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| 87 | /* |
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| 88 | VHandler for Vectored Interrupts |
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| 89 | |
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| 90 | All IRQ's are vectored to routine _ISR_#vector_number |
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| 91 | This routine stacks er0 and loads er0 with vector number |
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| 92 | before transferring to here |
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| 93 | |
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| 94 | */ |
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| 95 | .align 2 |
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| 96 | .global __ISR_Handler |
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| 97 | .extern __ISR_Nest_level |
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| 98 | .extern __Vector_table |
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| 99 | .extern __Context_switch_necessary |
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| 100 | |
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| 101 | |
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| 102 | __ISR_Handler: |
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[54ba5aa] | 103 | #if defined(__H8300H__) || defined(__H8300S__) |
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[5532553] | 104 | mov.l er1,@-er7 |
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| 105 | mov.l er2,@-er7 |
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| 106 | mov.l er3,@-er7 |
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| 107 | mov.l er4,@-er7 |
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| 108 | mov.l er5,@-er7 |
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| 109 | mov.l er6,@-er7 |
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| 110 | |
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| 111 | /* Set IRQ Stack */ |
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[fb31e1a2] | 112 | orc #0xc0,ccr |
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[5532553] | 113 | mov.l er7,er6 ; save stack pointer |
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| 114 | mov.l @__ISR_Nest_level,er1 |
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| 115 | bne nested |
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| 116 | mov.l @__CPU_Interrupt_stack_high,er7 |
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| 117 | |
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| 118 | nested: |
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| 119 | mov.l er6,@-er7 ; save sp so pop regardless of nest level |
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| 120 | |
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| 121 | ;; Inc system counters |
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| 122 | mov.l @__ISR_Nest_level,er1 |
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| 123 | inc.l #1,er1 |
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| 124 | mov.l er1,@__ISR_Nest_level |
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| 125 | mov.l @__Thread_Dispatch_disable_level,er1 |
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| 126 | inc.l #1,er1 |
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| 127 | mov.l er1,@__Thread_Dispatch_disable_level |
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| 128 | |
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| 129 | /* Vector to ISR */ |
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| 130 | |
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[fe7acdcf] | 131 | mov.l @__ISR_Vector_table,er1 |
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[5532553] | 132 | mov er0,er2 ; copy vector |
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| 133 | shll.l er2 |
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| 134 | shll.l er2 ; vector = vector * 4 (sizeof(int)) |
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| 135 | add.l er2,er1 |
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| 136 | mov.l @er1,er1 |
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| 137 | jsr @er1 ; er0 = arg1 =vector |
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| 138 | |
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[fb31e1a2] | 139 | orc #0xc0,ccr |
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[5532553] | 140 | mov.l @__ISR_Nest_level,er1 |
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| 141 | dec.l #1,er1 |
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| 142 | mov.l er1,@__ISR_Nest_level |
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| 143 | mov.l @__Thread_Dispatch_disable_level,er1 |
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| 144 | dec.l #1,er1 |
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| 145 | mov.l er1,@__Thread_Dispatch_disable_level |
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| 146 | bne exit |
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| 147 | |
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| 148 | mov.l @__Context_Switch_necessary,er1 |
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| 149 | bne bframe ; If yes then dispatch next task |
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| 150 | |
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| 151 | mov.l @__ISR_Signals_to_thread_executing,er1 |
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| 152 | beq exit ; If no signals waiting |
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| 153 | |
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| 154 | /* Context switch here through ISR_Dispatch */ |
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| 155 | |
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| 156 | bframe: |
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[fb31e1a2] | 157 | orc #0xc0,ccr |
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[5532553] | 158 | /* Pop Stack */ |
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| 159 | mov @er7+,er6 |
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| 160 | mov er6,er7 |
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| 161 | mov.l #0,er2 |
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| 162 | mov.l er2,@__ISR_Signals_to_thread_executing |
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| 163 | |
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| 164 | /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */ |
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| 165 | |
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[fb31e1a2] | 166 | mov.l #0xc0000000,er2 /* Disable IRQ */ |
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[5532553] | 167 | or.l #_ISR_Dispatch,er2 |
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| 168 | mov.l er2,@-er7 |
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| 169 | rte |
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| 170 | |
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| 171 | /* Inner IRQ Return, pop flags and return */ |
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| 172 | exit: |
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| 173 | /* Pop Stack */ |
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| 174 | orc #0x80,ccr |
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| 175 | mov @er7+,er6 |
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| 176 | mov er6,er7 |
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| 177 | mov @er7+,er6 |
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| 178 | mov @er7+,er5 |
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| 179 | mov @er7+,er4 |
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| 180 | mov @er7+,er3 |
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| 181 | mov @er7+,er2 |
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| 182 | mov @er7+,er1 |
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| 183 | mov @er7+,er0 |
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[54ba5aa] | 184 | #endif |
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[5532553] | 185 | rte |
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| 186 | |
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| 187 | /* |
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| 188 | Called from ISR_Handler as a way of ending IRQ |
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| 189 | but allowing dispatch to another task. |
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| 190 | Must use RTE as CCR is still on stack but IRQ has been serviced. |
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| 191 | CCR and PC occupy same word so rte can be used. |
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[fb31e1a2] | 192 | now using task stack |
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[5532553] | 193 | */ |
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| 194 | |
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| 195 | .align 2 |
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| 196 | .global _ISR_Dispatch |
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| 197 | |
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| 198 | _ISR_Dispatch: |
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[fb31e1a2] | 199 | |
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[54ba5aa] | 200 | #if defined(__H8300H__) || defined(__H8300S__) |
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| 201 | jsr @__Thread_Dispatch |
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[5532553] | 202 | mov @er7+,er6 |
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| 203 | mov @er7+,er5 |
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| 204 | mov @er7+,er4 |
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| 205 | mov @er7+,er3 |
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| 206 | mov @er7+,er2 |
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| 207 | mov @er7+,er1 |
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| 208 | mov @er7+,er0 |
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[54ba5aa] | 209 | #endif |
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[5532553] | 210 | rte |
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| 211 | |
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| 212 | |
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| 213 | .align 2 |
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| 214 | .global __CPU_Context_save_fp |
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| 215 | |
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| 216 | __CPU_Context_save_fp: |
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| 217 | rts |
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| 218 | |
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| 219 | |
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| 220 | .align 2 |
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| 221 | .global __CPU_Context_restore_fp |
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| 222 | |
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| 223 | __CPU_Context_restore_fp: |
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| 224 | rts |
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