[5532553] | 1 | /* |
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| 2 | * Hitachi H8 Score CPU functions |
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| 3 | * Copyright Comnet Technologies Ltd 1999 |
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| 4 | * |
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| 5 | * Based on example code and other ports with this copyright: |
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[5bb38e15] | 6 | * |
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[5532553] | 7 | * COPYRIGHT (c) 1989-1999. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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[5bb38e15] | 9 | * |
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[5532553] | 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[5532553] | 13 | */ |
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| 14 | |
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[febaa8a] | 15 | #ifdef HAVE_CONFIG_H |
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| 16 | #include "config.h" |
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| 17 | #endif |
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| 18 | |
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[1ef0afe6] | 19 | #include <rtems/asm.h> |
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| 20 | #include <rtems/score/percpu.h> |
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[5532553] | 21 | |
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| 22 | ;.equ RUNCONTEXT_ARG, er0 |
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| 23 | ;.equ HEIRCONTEXT_ARG, er1 |
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| 24 | |
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[5bb38e15] | 25 | /* |
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[5532553] | 26 | * Make sure we tell the assembler what type of CPU model we are |
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| 27 | * being compiled for. |
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[5bb38e15] | 28 | */ |
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[5532553] | 29 | |
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| 30 | #if defined(__H8300H__) |
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[fb31e1a2] | 31 | .h8300h |
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[5532553] | 32 | #endif |
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[5bb38e15] | 33 | #if defined(__H8300S__) |
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[fb31e1a2] | 34 | .h8300s |
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[f389307] | 35 | #endif |
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[5bb38e15] | 36 | #if defined(__H8300SX__) |
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[f389307] | 37 | .h8300sx |
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[5532553] | 38 | #endif |
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[fb31e1a2] | 39 | .text |
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[5532553] | 40 | |
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[fb31e1a2] | 41 | .text |
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[5532553] | 42 | /* |
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| 43 | GCC Compiled with optimisations and Wimplicit decs to ensure |
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| 44 | that stack from doesn't change |
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| 45 | |
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| 46 | Supposedly R2 and R3 do not need to be saved but who knows |
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| 47 | |
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| 48 | Arg1 = er0 (not on stack) |
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| 49 | Arg2 = er1 (not on stack) |
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| 50 | */ |
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| 51 | |
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| 52 | .align 2 |
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[fb31e1a2] | 53 | |
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[1ef0afe6] | 54 | .global SYM(_CPU_Context_switch) |
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[fb31e1a2] | 55 | |
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[1ef0afe6] | 56 | SYM(_CPU_Context_switch): |
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[5532553] | 57 | /* Save Context */ |
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[f1cf019] | 58 | #if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) |
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[fb31e1a2] | 59 | stc.w ccr,@(0:16,er0) |
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[5532553] | 60 | mov.l er7,@(2:16,er0) |
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| 61 | mov.l er6,@(6:16,er0) |
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| 62 | mov.l er5,@(10:16,er0) |
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| 63 | mov.l er4,@(14:16,er0) |
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| 64 | mov.l er3,@(18:16,er0) |
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| 65 | mov.l er2,@(22:16,er0) |
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| 66 | |
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| 67 | /* Install New context */ |
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| 68 | |
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| 69 | restore: |
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| 70 | mov.l @(22:16,er1),er2 |
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| 71 | mov.l @(18:16,er1),er3 |
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| 72 | mov.l @(14:16,er1),er4 |
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| 73 | mov.l @(10:16,er1),er5 |
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| 74 | mov.l @(6:16,er1),er6 |
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| 75 | mov.l @(2:16,er1),er7 |
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[fb31e1a2] | 76 | ldc.w @(0:16,er1),ccr |
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[54ba5aa] | 77 | #endif |
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[fb31e1a2] | 78 | |
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[5532553] | 79 | rts |
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| 80 | |
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| 81 | .align 2 |
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[fb31e1a2] | 82 | |
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[1ef0afe6] | 83 | .global SYM(_CPU_Context_restore) |
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[fb31e1a2] | 84 | |
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[1ef0afe6] | 85 | SYM(_CPU_Context_restore): |
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[fb31e1a2] | 86 | |
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[f1cf019] | 87 | #if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) |
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[54ba5aa] | 88 | mov.l er0,er1 |
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[fb31e1a2] | 89 | jmp @restore:24 |
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[54ba5aa] | 90 | #endif |
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[5532553] | 91 | |
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| 92 | |
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| 93 | |
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| 94 | /* |
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| 95 | VHandler for Vectored Interrupts |
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| 96 | |
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| 97 | All IRQ's are vectored to routine _ISR_#vector_number |
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| 98 | This routine stacks er0 and loads er0 with vector number |
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| 99 | before transferring to here |
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| 100 | |
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| 101 | */ |
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| 102 | .align 2 |
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[1ef0afe6] | 103 | .global SYM(_ISR_Handler) |
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| 104 | .extern SYM(_Vector_table) |
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[5532553] | 105 | |
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| 106 | |
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[1ef0afe6] | 107 | SYM(_ISR_Handler): |
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[f1cf019] | 108 | #if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) |
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[5532553] | 109 | mov.l er1,@-er7 |
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| 110 | mov.l er2,@-er7 |
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| 111 | mov.l er3,@-er7 |
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| 112 | mov.l er4,@-er7 |
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| 113 | mov.l er5,@-er7 |
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| 114 | mov.l er6,@-er7 |
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| 115 | |
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| 116 | /* Set IRQ Stack */ |
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[fb31e1a2] | 117 | orc #0xc0,ccr |
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[5532553] | 118 | mov.l er7,er6 ; save stack pointer |
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[1ef0afe6] | 119 | mov.l @ISR_NEST_LEVEL,er1 |
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[5532553] | 120 | bne nested |
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[1ef0afe6] | 121 | mov.l @INTERRUPT_STACK_HIGH,er7 |
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[5532553] | 122 | |
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| 123 | nested: |
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| 124 | mov.l er6,@-er7 ; save sp so pop regardless of nest level |
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| 125 | |
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[5bb38e15] | 126 | ;; Inc system counters |
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[1ef0afe6] | 127 | mov.l @ISR_NEST_LEVEL,er1 |
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[5532553] | 128 | inc.l #1,er1 |
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[1ef0afe6] | 129 | mov.l er1,@ISR_NEST_LEVEL |
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[d19cce29] | 130 | mov.l @THREAD_DISPATCH_DISABLE_LEVEL,er1 |
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[5532553] | 131 | inc.l #1,er1 |
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[d19cce29] | 132 | mov.l er1,@THREAD_DISPATCH_DISABLE_LEVEL |
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[5532553] | 133 | |
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| 134 | /* Vector to ISR */ |
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| 135 | |
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| 136 | mov er0,er2 ; copy vector |
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| 137 | shll.l er2 |
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| 138 | shll.l er2 ; vector = vector * 4 (sizeof(int)) |
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[03b7789] | 139 | mov.l @(SYM(_ISR_Vector_table), er2),er1 |
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[5532553] | 140 | jsr @er1 ; er0 = arg1 =vector |
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| 141 | |
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[fb31e1a2] | 142 | orc #0xc0,ccr |
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[1ef0afe6] | 143 | mov.l @ISR_NEST_LEVEL,er1 |
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[5532553] | 144 | dec.l #1,er1 |
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[1ef0afe6] | 145 | mov.l er1,@ISR_NEST_LEVEL |
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[d19cce29] | 146 | mov.l @THREAD_DISPATCH_DISABLE_LEVEL,er1 |
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[5532553] | 147 | dec.l #1,er1 |
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[d19cce29] | 148 | mov.l er1,@THREAD_DISPATCH_DISABLE_LEVEL |
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[1ef0afe6] | 149 | bne exit |
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[5532553] | 150 | |
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[1ef0afe6] | 151 | mov.b @DISPATCH_NEEDED,er1 |
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| 152 | beq exit ; If no then exit |
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[5532553] | 153 | |
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| 154 | /* Context switch here through ISR_Dispatch */ |
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| 155 | bframe: |
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[1ef0afe6] | 156 | orc #0xc0,ccr |
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[5532553] | 157 | /* Pop Stack */ |
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[1ef0afe6] | 158 | mov @er7+,er6 |
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| 159 | mov er6,er7 |
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[5532553] | 160 | |
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| 161 | /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */ |
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| 162 | |
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[fb31e1a2] | 163 | mov.l #0xc0000000,er2 /* Disable IRQ */ |
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[1ef0afe6] | 164 | or.l #SYM(_ISR_Dispatch),er2 |
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[5532553] | 165 | mov.l er2,@-er7 |
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| 166 | rte |
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| 167 | |
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| 168 | /* Inner IRQ Return, pop flags and return */ |
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| 169 | exit: |
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| 170 | /* Pop Stack */ |
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| 171 | orc #0x80,ccr |
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| 172 | mov @er7+,er6 |
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| 173 | mov er6,er7 |
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| 174 | mov @er7+,er6 |
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| 175 | mov @er7+,er5 |
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| 176 | mov @er7+,er4 |
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| 177 | mov @er7+,er3 |
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| 178 | mov @er7+,er2 |
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| 179 | mov @er7+,er1 |
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| 180 | mov @er7+,er0 |
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[54ba5aa] | 181 | #endif |
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[5532553] | 182 | rte |
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| 183 | |
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| 184 | /* |
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| 185 | Called from ISR_Handler as a way of ending IRQ |
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| 186 | but allowing dispatch to another task. |
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| 187 | Must use RTE as CCR is still on stack but IRQ has been serviced. |
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| 188 | CCR and PC occupy same word so rte can be used. |
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[fb31e1a2] | 189 | now using task stack |
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[5532553] | 190 | */ |
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| 191 | |
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| 192 | .align 2 |
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[1ef0afe6] | 193 | .global SYM(_ISR_Dispatch) |
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[5532553] | 194 | |
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[1ef0afe6] | 195 | SYM(_ISR_Dispatch): |
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[fb31e1a2] | 196 | |
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[f1cf019] | 197 | #if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) |
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[1ef0afe6] | 198 | jsr @SYM(_Thread_Dispatch) |
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[5532553] | 199 | mov @er7+,er6 |
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| 200 | mov @er7+,er5 |
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| 201 | mov @er7+,er4 |
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| 202 | mov @er7+,er3 |
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| 203 | mov @er7+,er2 |
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| 204 | mov @er7+,er1 |
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| 205 | mov @er7+,er0 |
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[54ba5aa] | 206 | #endif |
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[5532553] | 207 | rte |
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| 208 | |
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| 209 | |
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| 210 | .align 2 |
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[1ef0afe6] | 211 | .global SYM(_CPU_Context_save_fp) |
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[5532553] | 212 | |
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[1ef0afe6] | 213 | SYM(_CPU_Context_save_fp): |
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[5532553] | 214 | rts |
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| 215 | |
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| 216 | |
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| 217 | .align 2 |
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[1ef0afe6] | 218 | .global SYM(_CPU_Context_restore_fp) |
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[5532553] | 219 | |
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[1ef0afe6] | 220 | SYM(_CPU_Context_restore_fp): |
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[5532553] | 221 | rts |
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