source: rtems/cpukit/score/cpu/h8300/cpu.c @ febaa8a

4.104.11
Last change on this file since febaa8a was febaa8a, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:03:09 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • cpu.c, cpu_asm.S: Add include of config.h
  • Property mode set to 100644
File size: 3.3 KB
Line 
1/*
2 *  Hitachi H8300 CPU Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#ifdef HAVE_CONFIG_H
15#include "config.h"
16#endif
17
18#include <rtems/system.h>
19#include <rtems/score/isr.h>
20#include <rtems/score/wkspace.h>
21
22/*  _CPU_Initialize
23 *
24 *  This routine performs processor dependent initialization.
25 *
26 *  INPUT PARAMETERS: NONE
27 */
28
29
30void _CPU_Initialize(void)
31{
32  /*
33   *  If there is not an easy way to initialize the FP context
34   *  during Context_Initialize, then it is usually easier to
35   *  save an "uninitialized" FP context here and copy it to
36   *  the task's during Context_Initialize.
37   */
38
39  /* FP context initialization support goes here */
40}
41
42/*PAGE
43 *
44 *  _CPU_ISR_Get_level
45 *
46 *  This routine returns the current interrupt level.
47 */
48
49uint32_t   _CPU_ISR_Get_level( void )
50{
51  unsigned int _ccr;
52
53#if defined(__H8300__)
54#warning "How do we get ccr on base CPU models"
55#else
56  asm volatile ( "stc ccr, %0" : "=m" (_ccr) : );
57#endif
58
59  if ( _ccr & 0x80 )
60    return 1;
61  return 0;
62}
63
64/*PAGE
65 *
66 *  _CPU_ISR_install_raw_handler
67 */
68
69void _CPU_ISR_install_raw_handler(
70  uint32_t    vector,
71  proc_ptr    new_handler,
72  proc_ptr   *old_handler
73)
74{
75  /*
76   *  This is where we install the interrupt handler into the "raw" interrupt
77   *  table used by the CPU to dispatch interrupt handlers.
78   *  Use Debug level IRQ Handlers
79   */
80  H8BD_Install_IRQ(vector,new_handler,old_handler);
81}
82
83/*PAGE
84 *
85 *  _CPU_ISR_install_vector
86 *
87 *  This kernel routine installs the RTEMS handler for the
88 *  specified vector.
89 *
90 *  Input parameters:
91 *    vector      - interrupt vector number
92 *    old_handler - former ISR for this vector number
93 *    new_handler - replacement ISR for this vector number
94 *
95 *  Output parameters:  NONE
96 *
97 */
98
99void _CPU_ISR_install_vector(
100  uint32_t    vector,
101  proc_ptr    new_handler,
102  proc_ptr   *old_handler
103)
104{
105   *old_handler = _ISR_Vector_table[ vector ];
106
107   /*
108    *  If the interrupt vector table is a table of pointer to isr entry
109    *  points, then we need to install the appropriate RTEMS interrupt
110    *  handler for this vector number.
111    */
112
113   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
114
115   /*
116    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
117    *  be used by the _ISR_Handler so the user gets control.
118    */
119
120    _ISR_Vector_table[ vector ] = new_handler;
121}
122
123/*PAGE
124 *
125 *  _CPU_Install_interrupt_stack
126 */
127
128void _CPU_Install_interrupt_stack( void )
129{
130}
131
132/*PAGE
133 *
134 *  _CPU_Thread_Idle_body
135 *
136 *  NOTES:
137 *
138 *  1. This is the same as the regular CPU independent algorithm.
139 *
140 *  2. If you implement this using a "halt", "idle", or "shutdown"
141 *     instruction, then don't forget to put it in an infinite loop.
142 *
143 *  3. Be warned. Some processors with onboard DMA have been known
144 *     to stop the DMA if the CPU were put in IDLE mode.  This might
145 *     also be a problem with other on-chip peripherals.  So use this
146 *     hook with caution.
147 */
148
149#if 0
150void *_CPU_Thread_Idle_body( uintptr_t ignored )
151{
152
153  for( ; ; )
154    IDLE_Monitor();
155        /*asm(" sleep   \n"); */
156    /* insert your "halt" instruction here */ ;
157}
158#endif
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