[5532553] | 1 | /* |
---|
| 2 | * Hitachi H8300 CPU Dependent Source |
---|
| 3 | * |
---|
| 4 | * COPYRIGHT (c) 1989-1999. |
---|
| 5 | * On-Line Applications Research Corporation (OAR). |
---|
| 6 | * |
---|
| 7 | * The license and distribution terms for this file may be |
---|
| 8 | * found in the file LICENSE in this distribution or at |
---|
[a97f3776] | 9 | * http://www.rtems.com/license/LICENSE. |
---|
[5532553] | 10 | * |
---|
| 11 | * $Id$ |
---|
| 12 | */ |
---|
| 13 | |
---|
| 14 | #include <rtems/system.h> |
---|
| 15 | #include <rtems/score/isr.h> |
---|
| 16 | #include <rtems/score/wkspace.h> |
---|
| 17 | |
---|
| 18 | /* _CPU_Initialize |
---|
| 19 | * |
---|
| 20 | * This routine performs processor dependent initialization. |
---|
| 21 | * |
---|
| 22 | * INPUT PARAMETERS: |
---|
| 23 | * thread_dispatch - address of disptaching routine |
---|
| 24 | */ |
---|
| 25 | |
---|
| 26 | |
---|
| 27 | void _CPU_Initialize( |
---|
| 28 | void (*thread_dispatch) /* ignored on this CPU */ |
---|
| 29 | ) |
---|
| 30 | { |
---|
| 31 | /* |
---|
| 32 | * The thread_dispatch argument is the address of the entry point |
---|
| 33 | * for the routine called at the end of an ISR once it has been |
---|
| 34 | * decided a context switch is necessary. On some compilation |
---|
| 35 | * systems it is difficult to call a high-level language routine |
---|
| 36 | * from assembly. This allows us to trick these systems. |
---|
| 37 | * |
---|
| 38 | * If you encounter this problem save the entry point in a CPU |
---|
| 39 | * dependent variable. |
---|
| 40 | */ |
---|
| 41 | |
---|
| 42 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
---|
| 43 | |
---|
| 44 | /* |
---|
| 45 | * If there is not an easy way to initialize the FP context |
---|
| 46 | * during Context_Initialize, then it is usually easier to |
---|
| 47 | * save an "uninitialized" FP context here and copy it to |
---|
| 48 | * the task's during Context_Initialize. |
---|
| 49 | */ |
---|
| 50 | |
---|
| 51 | /* FP context initialization support goes here */ |
---|
| 52 | } |
---|
| 53 | |
---|
| 54 | /*PAGE |
---|
| 55 | * |
---|
| 56 | * _CPU_ISR_Get_level |
---|
| 57 | * |
---|
| 58 | * This routine returns the current interrupt level. |
---|
| 59 | */ |
---|
| 60 | |
---|
[c346f33d] | 61 | uint32_t _CPU_ISR_Get_level( void ) |
---|
[5532553] | 62 | { |
---|
| 63 | unsigned int _ccr; |
---|
| 64 | |
---|
| 65 | #if defined(__H8300__) |
---|
| 66 | #warning "How do we get ccr on base CPU models" |
---|
| 67 | #else |
---|
| 68 | asm volatile ( "stc ccr, %0" : "=m" (_ccr) : ); |
---|
| 69 | #endif |
---|
| 70 | |
---|
| 71 | if ( _ccr & 0x80 ) |
---|
| 72 | return 1; |
---|
| 73 | return 0; |
---|
| 74 | } |
---|
| 75 | |
---|
| 76 | /*PAGE |
---|
| 77 | * |
---|
| 78 | * _CPU_ISR_install_raw_handler |
---|
| 79 | */ |
---|
| 80 | |
---|
| 81 | void _CPU_ISR_install_raw_handler( |
---|
[c346f33d] | 82 | uint32_t vector, |
---|
[5532553] | 83 | proc_ptr new_handler, |
---|
| 84 | proc_ptr *old_handler |
---|
| 85 | ) |
---|
| 86 | { |
---|
| 87 | /* |
---|
| 88 | * This is where we install the interrupt handler into the "raw" interrupt |
---|
| 89 | * table used by the CPU to dispatch interrupt handlers. |
---|
| 90 | * Use Debug level IRQ Handlers |
---|
| 91 | */ |
---|
| 92 | H8BD_Install_IRQ(vector,new_handler,old_handler); |
---|
| 93 | } |
---|
| 94 | |
---|
| 95 | /*PAGE |
---|
| 96 | * |
---|
| 97 | * _CPU_ISR_install_vector |
---|
| 98 | * |
---|
| 99 | * This kernel routine installs the RTEMS handler for the |
---|
| 100 | * specified vector. |
---|
| 101 | * |
---|
| 102 | * Input parameters: |
---|
| 103 | * vector - interrupt vector number |
---|
| 104 | * old_handler - former ISR for this vector number |
---|
| 105 | * new_handler - replacement ISR for this vector number |
---|
| 106 | * |
---|
| 107 | * Output parameters: NONE |
---|
| 108 | * |
---|
| 109 | */ |
---|
| 110 | |
---|
| 111 | void _CPU_ISR_install_vector( |
---|
[c346f33d] | 112 | uint32_t vector, |
---|
[5532553] | 113 | proc_ptr new_handler, |
---|
| 114 | proc_ptr *old_handler |
---|
| 115 | ) |
---|
| 116 | { |
---|
| 117 | *old_handler = _ISR_Vector_table[ vector ]; |
---|
| 118 | |
---|
| 119 | /* |
---|
| 120 | * If the interrupt vector table is a table of pointer to isr entry |
---|
| 121 | * points, then we need to install the appropriate RTEMS interrupt |
---|
| 122 | * handler for this vector number. |
---|
| 123 | */ |
---|
| 124 | |
---|
| 125 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
---|
| 126 | |
---|
| 127 | /* |
---|
| 128 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
---|
| 129 | * be used by the _ISR_Handler so the user gets control. |
---|
| 130 | */ |
---|
| 131 | |
---|
| 132 | _ISR_Vector_table[ vector ] = new_handler; |
---|
| 133 | } |
---|
| 134 | |
---|
| 135 | /*PAGE |
---|
| 136 | * |
---|
| 137 | * _CPU_Install_interrupt_stack |
---|
| 138 | */ |
---|
| 139 | |
---|
| 140 | void _CPU_Install_interrupt_stack( void ) |
---|
| 141 | { |
---|
| 142 | } |
---|
| 143 | |
---|
| 144 | /*PAGE |
---|
| 145 | * |
---|
| 146 | * _CPU_Thread_Idle_body |
---|
| 147 | * |
---|
| 148 | * NOTES: |
---|
| 149 | * |
---|
| 150 | * 1. This is the same as the regular CPU independent algorithm. |
---|
| 151 | * |
---|
| 152 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
---|
| 153 | * instruction, then don't forget to put it in an infinite loop. |
---|
| 154 | * |
---|
| 155 | * 3. Be warned. Some processors with onboard DMA have been known |
---|
| 156 | * to stop the DMA if the CPU were put in IDLE mode. This might |
---|
| 157 | * also be a problem with other on-chip peripherals. So use this |
---|
| 158 | * hook with caution. |
---|
| 159 | */ |
---|
| 160 | |
---|
| 161 | #if 0 |
---|
[3c87adba] | 162 | void *_CPU_Thread_Idle_body( uint32_t ignored ) |
---|
[5532553] | 163 | { |
---|
| 164 | |
---|
| 165 | for( ; ; ) |
---|
| 166 | IDLE_Monitor(); |
---|
| 167 | /*asm(" sleep \n"); */ |
---|
| 168 | /* insert your "halt" instruction here */ ; |
---|
| 169 | } |
---|
| 170 | #endif |
---|