source: rtems/cpukit/score/cpu/epiphany/rtems/score/epiphany-utility.h @ 66a5000d

4.115
Last change on this file since 66a5000d was 66a5000d, checked in by Hesham ALMatary <heshamelmatary@…>, on May 21, 2015 at 4:52:56 PM

cpukit: Add Epiphany architecture port v4

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1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief This include file contains macros pertaining to the
7 *  Epiphany processor family.
8 */
9
10/*
11 * Copyright (c) 2015 University of York.
12 * Hesham ALMatary <hmka501@york.ac.uk>
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 *    notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in the
21 *    documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#ifndef _EPIPHANY_UTILITY_H
37#define _EPIPHANY_UTILITY_H
38
39/* eCore IRQs */
40typedef enum
41{
42  START,
43  SW_EXCEPTION,
44  MEM_FAULT,
45  TIMER0,
46  TIMER1,
47  SMP_MESSAGE,
48  DMA0,
49  DMA1,
50  SER,
51} EPIPHANY_IRQ_PER_CORE_T;
52
53/*  Per-core IO mapped register addresses
54 *  @see Epiphany architecture reference.
55 */
56#define EPIPHANY_PER_CORE_REG_CONFIG      0xF0400
57#define EPIPHANY_PER_CORE_REG_STATUS      0xF0404
58#define EPIPHANY_PER_CORE_REG_PC          0xF0408
59#define EPIPHANY_PER_CORE_REG_DEBUGSTATUS 0xF040C
60#define EPIPHANY_PER_CORE_REG_LC          0xF0414
61#define EPIPHANY_PER_CORE_REG_LS          0xF0418
62#define EPIPHANY_PER_CORE_REG_LE          0xF041C
63#define EPIPHANY_PER_CORE_REG_IRET        0xF0420
64#define EPIPHANY_PER_CORE_REG_IMASK       0xF0424
65#define EPIPHANY_PER_CORE_REG_ILAT        0xF0428
66#define EPIPHANY_PER_CORE_REG_ILATST      0xF042C
67#define EPIPHANY_PER_CORE_REG_ILATCL      0xF0430
68#define EPIPHANY_PER_CORE_REG_IPEND       0xF0434
69#define EPIPHANY_PER_CORE_REG_FSTATUS     0xF0440
70#define EPIPHANY_PER_CORE_REG_DEBUGCMD    0xF0448
71#define EPIPHANY_PER_CORE_REG_RESETCORE   0xF070C
72
73/* Event timer registers */
74#define EPIPHANY_PER_CORE_REG_CTIMER0     0xF0438
75#define EPIPHANY_PER_CORE_REG_CTIMER1     0xF043C
76
77/* Processor control registers */
78#define EPIPHANY_PER_CORE_REG_MEMSTATUS   0xF0604
79#define EPIPHANY_PER_CORE_REG_MEMPROTECT  0xF0608
80
81/* DMA Registers */
82#define EPIPHANY_PER_CORE_REG_DMA0CONFIG  0xF0500
83#define EPIPHANY_PER_CORE_REG_DMA0STRIDE  0xF0504
84#define EPIPHANY_PER_CORE_REG_DMA0COUNT   0xF0508
85#define EPIPHANY_PER_CORE_REG_DMA0SRCADDR 0xF050C
86#define EPIPHANY_PER_CORE_REG_DMA0DSTADDR 0xF0510
87#define EPIPHANY_PER_CORE_REG_DMA0AUTO0   0xF0514
88#define EPIPHANY_PER_CORE_REG_DMA0AUTO1   0xF0518
89#define EPIPHANY_PER_CORE_REG_DMA0STATUS  0xF051C
90#define EPIPHANY_PER_CORE_REG_DMA1CONFIG  0xF0520
91#define EPIPHANY_PER_CORE_REG_DMA1STRIDE  0xF0524
92#define EPIPHANY_PER_CORE_REG_DMA1COUNT   0xF0528
93#define EPIPHANY_PER_CORE_REG_DMA1SRCADDR 0xF052C
94#define EPIPHANY_PER_CORE_REG_DMA1DSTADDR 0xF0530
95#define EPIPHANY_PER_CORE_REG_DMA1AUTO0   0xF0534
96#define EPIPHANY_PER_CORE_REG_DMA1AUTO1   0xF0538
97#define EPIPHANY_PER_CORE_REG_DMA1STATUS  0xF053C
98
99/* Mesh Node Control Registers */
100#define EPIPHANY_PER_CORE_REG_MESHCONFIG  0xF0700
101#define EPIPHANY_PER_CORE_REG_COREID      0xF0704
102#define EPIPHANY_PER_CORE_REG_MULTICAST   0xF0708
103#define EPIPHANY_PER_CORE_REG_CMESHROUTE  0xF0710
104#define EPIPHANY_PER_CORE_REG_XMESHROUTE  0xF0714
105#define EPIPHANY_PER_CORE_REG_RMESHROUTE  0xF0718
106
107/*  This macros constructs an address space of epiphany cores
108 *  from their IDs.
109 */
110#define EPIPHANY_COREID_TO_MSB_ADDR(id) (id) << 20
111
112/*  Construct a complete/absolute IO mapped address register from
113 *  core ID and register name
114 */
115#define EPIPHANY_GET_REG_ABSOLUTE_ADDR(coreid, reg) \
116        (EPIPHANY_COREID_TO_MSB_ADDR(coreid) | (reg))
117
118#define EPIPHANY_REG(reg) (uint32_t *) (reg)
119
120/* Read register with its absolute address */
121static inline uint32_t read_epiphany_reg(volatile uint32_t reg_addr)
122{
123  return *(EPIPHANY_REG(reg_addr));
124}
125
126/* Write register with its abolute address */
127static inline void write_epiphany_reg(volatile uint32_t reg_addr, uint32_t val)
128{
129  *(EPIPHANY_REG(reg_addr)) = val;
130}
131
132/*  Epiphany uses 12 bits for defining core IDs, while RTEMS uses
133 *  linear IDs. The following function converts RTEMS linear IDs to
134 *  Epiphany corresponding ones
135 */
136static const uint32_t map[16] =
137{
138   0x808, 0x809, 0x80A, 0x80B,
139   0x848, 0x849, 0x84A, 0x84B,
140   0x888, 0x889, 0x88A, 0x88B,
141   0x8C8, 0x8C9, 0x8CA, 0x8CB
142};
143
144static inline uint32_t rtems_coreid_to_epiphany_map(uint32_t rtems_id)
145{
146  return map[rtems_id];
147}
148
149/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses
150 * linear IDs. The following function is used to map Epiphany IDs to
151 * RTEMS linear IDs.
152 */
153static inline uint32_t epiphany_coreid_to_rtems_map(uint32_t epiphany_id)
154{
155  register uint32_t coreid asm ("r17") = epiphany_id;
156
157  /* Mapping from Epiphany IDs to 0-16 IDs macro */
158  __asm__ __volatile__(" \
159   movfs r17, coreid \
160   mov r19, #0x003   \
161   mov r20, #0x0F0   \
162   and r19, r17, r19 \
163   and r20, r17, r20 \
164   lsr r20, r20, #4  \
165   add r17, r19, r20 \
166   ");
167
168  /* coreid or r17 now holds the rtems core id */
169  return coreid;
170}
171
172static inline uint32_t _Epiphany_Get_current_processor()
173{
174  uint32_t coreid;
175
176  asm volatile ("movfs %0, coreid" : "=r" (coreid): );
177
178  return epiphany_coreid_to_rtems_map(coreid);
179}
180#endif  /* _EPIPHANY_UTILITY_H */
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