1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * |
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7 | * Copyright (c) 2015 University of York. |
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8 | * Hesham ALMatary <hmka501@york.ac.uk> |
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9 | * |
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10 | * COPYRIGHT (c) 1989-1999. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * Redistribution and use in source and binary forms, with or without |
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14 | * modification, are permitted provided that the following conditions |
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15 | * are met: |
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16 | * 1. Redistributions of source code must retain the above copyright |
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17 | * notice, this list of conditions and the following disclaimer. |
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18 | * 2. Redistributions in binary form must reproduce the above copyright |
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19 | * notice, this list of conditions and the following disclaimer in the |
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20 | * documentation and/or other materials provided with the distribution. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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32 | * SUCH DAMAGE. |
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33 | */ |
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34 | |
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35 | #ifndef _EPIPHANY_CPU_H |
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36 | #define _EPIPHANY_CPU_H |
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37 | |
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38 | #ifdef __cplusplus |
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39 | extern "C" { |
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40 | #endif |
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41 | |
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42 | #include <rtems/score/epiphany.h> /* pick up machine definitions */ |
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43 | #include <rtems/score/types.h> |
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44 | #ifndef ASM |
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45 | #include <rtems/bspIo.h> |
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46 | #include <stdint.h> |
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47 | #include <stdio.h> /* for printk */ |
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48 | #endif |
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49 | |
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50 | /* conditional compilation parameters */ |
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51 | |
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52 | /* |
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53 | * Does RTEMS manage a dedicated interrupt stack in software? |
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54 | * |
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55 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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56 | * If FALSE, nothing is done. |
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57 | * |
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58 | * If the CPU supports a dedicated interrupt stack in hardware, |
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59 | * then it is generally the responsibility of the BSP to allocate it |
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60 | * and set it up. |
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61 | * |
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62 | * If the CPU does not support a dedicated interrupt stack, then |
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63 | * the porter has two options: (1) execute interrupts on the |
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64 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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65 | * interrupt stack. |
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66 | * |
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67 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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68 | * |
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69 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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70 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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71 | * possible that both are FALSE for a particular CPU. Although it |
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72 | * is unclear what that would imply about the interrupt processing |
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73 | * procedure on that CPU. |
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74 | * |
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75 | * Currently, for epiphany port, _ISR_Handler is responsible for switching to |
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76 | * RTEMS dedicated interrupt task. |
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77 | * |
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78 | */ |
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79 | |
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80 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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81 | |
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82 | /* |
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83 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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84 | * |
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85 | * If TRUE, then it must be installed during initialization. |
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86 | * If FALSE, then no installation is performed. |
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87 | * |
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88 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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89 | * |
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90 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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91 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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92 | * possible that both are FALSE for a particular CPU. Although it |
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93 | * is unclear what that would imply about the interrupt processing |
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94 | * procedure on that CPU. |
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95 | * |
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96 | */ |
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97 | |
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98 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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99 | |
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100 | /* |
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101 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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102 | * |
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103 | * If TRUE, then the memory is allocated during initialization. |
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104 | * If FALSE, then the memory is allocated during initialization. |
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105 | * |
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106 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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107 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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108 | * |
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109 | */ |
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110 | |
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111 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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112 | |
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113 | /* |
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114 | * Does the RTEMS invoke the user's ISR with the vector number and |
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115 | * a pointer to the saved interrupt frame (1) or just the vector |
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116 | * number (0)? |
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117 | * |
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118 | */ |
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119 | |
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120 | #define CPU_ISR_PASSES_FRAME_POINTER TRUE |
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121 | |
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122 | /* |
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123 | * Does the CPU have hardware floating point? |
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124 | * |
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125 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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126 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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127 | * |
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128 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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129 | * the answer is TRUE. |
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130 | * |
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131 | * The macro name "epiphany_HAS_FPU" should be made CPU specific. |
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132 | * It indicates whether or not this CPU model has FP support. For |
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133 | * example, it would be possible to have an i386_nofp CPU model |
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134 | * which set this to false to indicate that you have an i386 without |
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135 | * an i387 and wish to leave floating point support out of RTEMS. |
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136 | * |
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137 | * The CPU_SOFTWARE_FP is used to indicate whether or not there |
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138 | * is software implemented floating point that must be context |
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139 | * switched. The determination of whether or not this applies |
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140 | * is very tool specific and the state saved/restored is also |
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141 | * compiler specific. |
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142 | * |
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143 | * epiphany Specific Information: |
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144 | * |
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145 | * At this time there are no implementations of Epiphany that are |
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146 | * expected to implement floating point. |
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147 | */ |
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148 | |
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149 | #define CPU_HARDWARE_FP FALSE |
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150 | #define CPU_SOFTWARE_FP FALSE |
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151 | |
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152 | /* |
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153 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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154 | * |
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155 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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156 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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157 | * |
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158 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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159 | * |
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160 | */ |
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161 | |
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162 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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163 | |
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164 | /* |
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165 | * Should the IDLE task have a floating point context? |
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166 | * |
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167 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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168 | * and it has a floating point context which is switched in and out. |
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169 | * If FALSE, then the IDLE task does not have a floating point context. |
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170 | * |
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171 | * Setting this to TRUE negatively impacts the time required to preempt |
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172 | * the IDLE task from an interrupt because the floating point context |
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173 | * must be saved as part of the preemption. |
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174 | * |
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175 | */ |
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176 | |
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177 | #define CPU_IDLE_TASK_IS_FP FALSE |
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178 | |
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179 | /* |
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180 | * Should the saving of the floating point registers be deferred |
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181 | * until a context switch is made to another different floating point |
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182 | * task? |
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183 | * |
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184 | * If TRUE, then the floating point context will not be stored until |
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185 | * necessary. It will remain in the floating point registers and not |
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186 | * disturned until another floating point task is switched to. |
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187 | * |
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188 | * If FALSE, then the floating point context is saved when a floating |
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189 | * point task is switched out and restored when the next floating point |
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190 | * task is restored. The state of the floating point registers between |
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191 | * those two operations is not specified. |
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192 | * |
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193 | * If the floating point context does NOT have to be saved as part of |
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194 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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195 | * |
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196 | * Setting this flag to TRUE results in using a different algorithm |
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197 | * for deciding when to save and restore the floating point context. |
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198 | * The deferred FP switch algorithm minimizes the number of times |
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199 | * the FP context is saved and restored. The FP context is not saved |
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200 | * until a context switch is made to another, different FP task. |
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201 | * Thus in a system with only one FP task, the FP context will never |
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202 | * be saved or restored. |
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203 | * |
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204 | */ |
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205 | |
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206 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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207 | |
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208 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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209 | |
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210 | /* |
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211 | * Does this port provide a CPU dependent IDLE task implementation? |
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212 | * |
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213 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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214 | * must be provided and is the default IDLE thread body instead of |
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215 | * _CPU_Thread_Idle_body. |
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216 | * |
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217 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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218 | * not provide one. |
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219 | * |
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220 | * This is intended to allow for supporting processors which have |
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221 | * a low power or idle mode. When the IDLE thread is executed, then |
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222 | * the CPU can be powered down. |
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223 | * |
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224 | * The order of precedence for selecting the IDLE thread body is: |
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225 | * |
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226 | * 1. BSP provided |
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227 | * 2. CPU dependent (if provided) |
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228 | * 3. generic (if no BSP and no CPU dependent) |
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229 | * |
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230 | */ |
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231 | |
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232 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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233 | |
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234 | /* |
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235 | * Does the stack grow up (toward higher addresses) or down |
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236 | * (toward lower addresses)? |
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237 | * |
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238 | * If TRUE, then the grows upward. |
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239 | * If FALSE, then the grows toward smaller addresses. |
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240 | * |
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241 | */ |
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242 | |
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243 | #define CPU_STACK_GROWS_UP FALSE |
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244 | |
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245 | /* FIXME: Is this the right value? */ |
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246 | #define CPU_CACHE_LINE_BYTES 64 |
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247 | |
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248 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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249 | |
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250 | /* |
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251 | * Define what is required to specify how the network to host conversion |
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252 | * routines are handled. |
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253 | * |
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254 | * epiphany Specific Information: |
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255 | * |
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256 | * This version of RTEMS is designed specifically to run with |
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257 | * big endian architectures. If you want little endian, you'll |
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258 | * have to make the appropriate adjustments here and write |
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259 | * efficient routines for byte swapping. The epiphany architecture |
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260 | * doesn't do this very well. |
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261 | */ |
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262 | |
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263 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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264 | |
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265 | /* |
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266 | * The following defines the number of bits actually used in the |
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267 | * interrupt field of the task mode. How those bits map to the |
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268 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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269 | * |
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270 | */ |
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271 | |
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272 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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273 | |
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274 | /* |
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275 | * Processor defined structures required for cpukit/score. |
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276 | */ |
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277 | |
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278 | /* |
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279 | * Contexts |
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280 | * |
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281 | * Generally there are 2 types of context to save. |
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282 | * 1. Interrupt registers to save |
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283 | * 2. Task level registers to save |
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284 | * |
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285 | * This means we have the following 3 context items: |
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286 | * 1. task level context stuff:: Context_Control |
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287 | * 2. floating point task stuff:: Context_Control_fp |
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288 | * 3. special interrupt level context :: Context_Control_interrupt |
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289 | * |
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290 | * On some processors, it is cost-effective to save only the callee |
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291 | * preserved registers during a task context switch. This means |
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292 | * that the ISR code needs to save those registers which do not |
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293 | * persist across function calls. It is not mandatory to make this |
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294 | * distinctions between the caller/callee saves registers for the |
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295 | * purpose of minimizing context saved during task switch and on interrupts. |
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296 | * If the cost of saving extra registers is minimal, simplicity is the |
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297 | * choice. Save the same context on interrupt entry as for tasks in |
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298 | * this case. |
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299 | * |
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300 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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301 | * care should be used in designing the context area. |
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302 | * |
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303 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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304 | * structure will not be used or it simply consist of an array of a |
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305 | * fixed number of bytes. This is done when the floating point context |
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306 | * is dumped by a "FP save context" type instruction and the format |
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307 | * is not really defined by the CPU. In this case, there is no need |
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308 | * to figure out the exact format -- only the size. Of course, although |
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309 | * this is enough information for RTEMS, it is probably not enough for |
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310 | * a debugger such as gdb. But that is another problem. |
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311 | * |
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312 | * |
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313 | */ |
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314 | #ifndef ASM |
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315 | |
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316 | typedef struct { |
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317 | uint32_t r[64]; |
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318 | |
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319 | uint32_t status; |
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320 | uint32_t config; |
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321 | uint32_t iret; |
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322 | |
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323 | #ifdef RTEMS_SMP |
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324 | /** |
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325 | * @brief On SMP configurations the thread context must contain a boolean |
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326 | * indicator to signal if this context is executing on a processor. |
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327 | * |
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328 | * This field must be updated during a context switch. The context switch |
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329 | * to the heir must wait until the heir context indicates that it is no |
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330 | * longer executing on a processor. The context switch must also check if |
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331 | * a thread dispatch is necessary to honor updates of the heir thread for |
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332 | * this processor. This indicator must be updated using an atomic test and |
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333 | * set operation to ensure that at most one processor uses the heir |
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334 | * context at the same time. |
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335 | * |
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336 | * @code |
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337 | * void _CPU_Context_switch( |
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338 | * Context_Control *executing, |
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339 | * Context_Control *heir |
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340 | * ) |
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341 | * { |
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342 | * save( executing ); |
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343 | * |
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344 | * executing->is_executing = false; |
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345 | * memory_barrier(); |
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346 | * |
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347 | * if ( test_and_set( &heir->is_executing ) ) { |
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348 | * do { |
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349 | * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); |
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350 | * |
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351 | * if ( cpu_self->dispatch_necessary ) { |
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352 | * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); |
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353 | * } |
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354 | * } while ( test_and_set( &heir->is_executing ) ); |
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355 | * } |
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356 | * |
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357 | * restore( heir ); |
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358 | * } |
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359 | * @endcode |
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360 | */ |
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361 | volatile bool is_executing; |
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362 | #endif |
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363 | } Context_Control; |
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364 | |
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365 | #define _CPU_Context_Get_SP( _context ) \ |
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366 | (_context)->r[13] |
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367 | |
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368 | typedef struct { |
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369 | /** FPU registers are listed here */ |
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370 | double some_float_register; |
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371 | } Context_Control_fp; |
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372 | |
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373 | typedef Context_Control CPU_Interrupt_frame; |
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374 | |
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375 | /* |
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376 | * The size of the floating point context area. On some CPUs this |
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377 | * will not be a "sizeof" because the format of the floating point |
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378 | * area is not defined -- only the size is. This is usually on |
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379 | * CPUs with a "floating point save context" instruction. |
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380 | * |
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381 | * epiphany Specific Information: |
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382 | * |
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383 | */ |
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384 | |
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385 | #define CPU_CONTEXT_FP_SIZE 0 |
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386 | |
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387 | /* |
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388 | * Amount of extra stack (above minimum stack size) required by |
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389 | * MPCI receive server thread. Remember that in a multiprocessor |
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390 | * system this thread must exist and be able to process all directives. |
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391 | * |
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392 | */ |
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393 | |
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394 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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395 | |
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396 | /* |
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397 | * Should be large enough to run all RTEMS tests. This insures |
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398 | * that a "reasonable" small application should not have any problems. |
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399 | * |
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400 | */ |
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401 | |
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402 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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403 | |
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404 | /* |
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405 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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406 | * alignment does not take into account the requirements for the stack. |
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407 | * |
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408 | */ |
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409 | |
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410 | #define CPU_ALIGNMENT 8 |
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411 | |
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412 | /* |
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413 | * This is defined if the port has a special way to report the ISR nesting |
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414 | * level. Most ports maintain the variable _ISR_Nest_level. |
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415 | */ |
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416 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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417 | |
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418 | /* |
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419 | * This number corresponds to the byte alignment requirement for the |
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420 | * heap handler. This alignment requirement may be stricter than that |
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421 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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422 | * common for the heap to follow the same alignment requirement as |
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423 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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424 | * then this should be set to CPU_ALIGNMENT. |
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425 | * |
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426 | * NOTE: This does not have to be a power of 2 although it should be |
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427 | * a multiple of 2 greater than or equal to 2. The requirement |
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428 | * to be a multiple of 2 is because the heap uses the least |
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429 | * significant field of the front and back flags to indicate |
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430 | * that a block is in use or free. So you do not want any odd |
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431 | * length blocks really putting length data in that bit. |
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432 | * |
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433 | * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will |
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434 | * have to be greater or equal to than CPU_ALIGNMENT to ensure that |
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435 | * elements allocated from the heap meet all restrictions. |
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436 | * |
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437 | */ |
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438 | |
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439 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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440 | |
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441 | /* |
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442 | * This number corresponds to the byte alignment requirement for memory |
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443 | * buffers allocated by the partition manager. This alignment requirement |
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444 | * may be stricter than that for the data types alignment specified by |
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445 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
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446 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
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447 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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448 | * |
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449 | * NOTE: This does not have to be a power of 2. It does have to |
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450 | * be greater or equal to than CPU_ALIGNMENT. |
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451 | * |
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452 | */ |
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453 | |
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454 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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455 | |
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456 | /* |
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457 | * This number corresponds to the byte alignment requirement for the |
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458 | * stack. This alignment requirement may be stricter than that for the |
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459 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
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460 | * is strict enough for the stack, then this should be set to 0. |
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461 | * |
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462 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
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463 | * |
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464 | */ |
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465 | |
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466 | #define CPU_STACK_ALIGNMENT 8 |
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467 | |
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468 | /* ISR handler macros */ |
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469 | |
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470 | /* |
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471 | * Support routine to initialize the RTEMS vector table after it is allocated. |
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472 | * |
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473 | * NO_CPU Specific Information: |
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474 | * |
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475 | * XXX document implementation including references if appropriate |
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476 | */ |
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477 | |
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478 | #define _CPU_Initialize_vectors() |
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479 | |
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480 | /* |
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481 | * Disable all interrupts for an RTEMS critical section. The previous |
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482 | * level is returned in _level. |
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483 | * |
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484 | */ |
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485 | |
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486 | static inline uint32_t epiphany_interrupt_disable( void ) |
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487 | { |
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488 | uint32_t sr; |
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489 | __asm__ __volatile__ ("movfs %[sr], status \n" : [sr] "=r" (sr):); |
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490 | __asm__ __volatile__("gid \n"); |
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491 | return sr; |
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492 | } |
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493 | |
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494 | static inline void epiphany_interrupt_enable(uint32_t level) |
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495 | { |
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496 | __asm__ __volatile__("gie \n"); |
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497 | __asm__ __volatile__ ("movts status, %[level] \n" :: [level] "r" (level):); |
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498 | } |
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499 | |
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500 | #define _CPU_ISR_Disable( _level ) \ |
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501 | _level = epiphany_interrupt_disable() |
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502 | |
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503 | /* |
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504 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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505 | * This indicates the end of an RTEMS critical section. The parameter |
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506 | * _level is not modified. |
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507 | * |
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508 | */ |
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509 | |
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510 | #define _CPU_ISR_Enable( _level ) \ |
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511 | epiphany_interrupt_enable( _level ) |
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512 | |
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513 | /* |
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514 | * This temporarily restores the interrupt to _level before immediately |
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515 | * disabling them again. This is used to divide long RTEMS critical |
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516 | * sections into two or more parts. The parameter _level is not |
---|
517 | * modified. |
---|
518 | * |
---|
519 | */ |
---|
520 | |
---|
521 | #define _CPU_ISR_Flash( _level ) \ |
---|
522 | do{ \ |
---|
523 | if ( (_level & 0x2) != 0 ) \ |
---|
524 | _CPU_ISR_Enable( _level ); \ |
---|
525 | epiphany_interrupt_disable(); \ |
---|
526 | } while(0) |
---|
527 | |
---|
528 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
529 | { |
---|
530 | return ( level & 0x2 ) != 0; |
---|
531 | } |
---|
532 | |
---|
533 | /* |
---|
534 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
535 | * actually provides. Currently, interrupt levels which do not |
---|
536 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
537 | * it would be nice if these were "mapped" by the application |
---|
538 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
539 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
540 | * This could be used to manage a programmable interrupt controller |
---|
541 | * via the rtems_task_mode directive. |
---|
542 | * |
---|
543 | * The get routine usually must be implemented as a subroutine. |
---|
544 | * |
---|
545 | */ |
---|
546 | |
---|
547 | void _CPU_ISR_Set_level( uint32_t level ); |
---|
548 | |
---|
549 | uint32_t _CPU_ISR_Get_level( void ); |
---|
550 | |
---|
551 | /* end of ISR handler macros */ |
---|
552 | |
---|
553 | /* Context handler macros */ |
---|
554 | |
---|
555 | /* |
---|
556 | * Initialize the context to a state suitable for starting a |
---|
557 | * task after a context restore operation. Generally, this |
---|
558 | * involves: |
---|
559 | * |
---|
560 | * - setting a starting address |
---|
561 | * - preparing the stack |
---|
562 | * - preparing the stack and frame pointers |
---|
563 | * - setting the proper interrupt level in the context |
---|
564 | * - initializing the floating point context |
---|
565 | * |
---|
566 | * This routine generally does not set any unnecessary register |
---|
567 | * in the context. The state of the "general data" registers is |
---|
568 | * undefined at task start time. |
---|
569 | * |
---|
570 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
571 | * point thread. This is typically only used on CPUs where the |
---|
572 | * FPU may be easily disabled by software such as on the SPARC |
---|
573 | * where the PSR contains an enable FPU bit. |
---|
574 | * |
---|
575 | */ |
---|
576 | |
---|
577 | /** |
---|
578 | * @brief Account for GCC red-zone |
---|
579 | * |
---|
580 | * The following macro is used when initializing task's stack |
---|
581 | * to account for GCC red-zone. |
---|
582 | */ |
---|
583 | |
---|
584 | #define EPIPHANY_GCC_RED_ZONE_SIZE 128 |
---|
585 | |
---|
586 | /** |
---|
587 | * @brief Initializes the CPU context. |
---|
588 | * |
---|
589 | * The following steps are performed: |
---|
590 | * - setting a starting address |
---|
591 | * - preparing the stack |
---|
592 | * - preparing the stack and frame pointers |
---|
593 | * - setting the proper interrupt level in the context |
---|
594 | * |
---|
595 | * @param[in] context points to the context area |
---|
596 | * @param[in] stack_area_begin is the low address of the allocated stack area |
---|
597 | * @param[in] stack_area_size is the size of the stack area in bytes |
---|
598 | * @param[in] new_level is the interrupt level for the task |
---|
599 | * @param[in] entry_point is the task's entry point |
---|
600 | * @param[in] is_fp is set to @c true if the task is a floating point task |
---|
601 | * @param[in] tls_area is the thread-local storage (TLS) area |
---|
602 | */ |
---|
603 | void _CPU_Context_Initialize( |
---|
604 | Context_Control *context, |
---|
605 | void *stack_area_begin, |
---|
606 | size_t stack_area_size, |
---|
607 | uint32_t new_level, |
---|
608 | void (*entry_point)( void ), |
---|
609 | bool is_fp, |
---|
610 | void *tls_area |
---|
611 | ); |
---|
612 | |
---|
613 | /* |
---|
614 | * This routine is responsible for somehow restarting the currently |
---|
615 | * executing task. If you are lucky, then all that is necessary |
---|
616 | * is restoring the context. Otherwise, there will need to be |
---|
617 | * a special assembly routine which does something special in this |
---|
618 | * case. Context_Restore should work most of the time. It will |
---|
619 | * not work if restarting self conflicts with the stack frame |
---|
620 | * assumptions of restoring a context. |
---|
621 | * |
---|
622 | */ |
---|
623 | |
---|
624 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
625 | _CPU_Context_restore( (_the_context) ) |
---|
626 | |
---|
627 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
628 | memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); |
---|
629 | |
---|
630 | /* end of Context handler macros */ |
---|
631 | |
---|
632 | /* Fatal Error manager macros */ |
---|
633 | |
---|
634 | /* |
---|
635 | * This routine copies _error into a known place -- typically a stack |
---|
636 | * location or a register, optionally disables interrupts, and |
---|
637 | * halts/stops the CPU. |
---|
638 | * |
---|
639 | */ |
---|
640 | |
---|
641 | #define _CPU_Fatal_halt(_source, _error ) \ |
---|
642 | printk("Fatal Error %d.%d Halted\n",_source, _error); \ |
---|
643 | asm("trap 3" :: "r" (_error)); \ |
---|
644 | for(;;) |
---|
645 | |
---|
646 | /* end of Fatal Error manager macros */ |
---|
647 | |
---|
648 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
649 | |
---|
650 | #endif /* ASM */ |
---|
651 | |
---|
652 | /** |
---|
653 | * Size of a pointer. |
---|
654 | * |
---|
655 | * This must be an integer literal that can be used by the assembler. This |
---|
656 | * value will be used to calculate offsets of structure members. These |
---|
657 | * offsets will be used in assembler code. |
---|
658 | */ |
---|
659 | #define CPU_SIZEOF_POINTER 4 |
---|
660 | #define CPU_EXCEPTION_FRAME_SIZE 260 |
---|
661 | |
---|
662 | #define CPU_MAXIMUM_PROCESSORS 32 |
---|
663 | |
---|
664 | #ifndef ASM |
---|
665 | |
---|
666 | typedef struct { |
---|
667 | uint32_t r[62]; |
---|
668 | uint32_t status; |
---|
669 | uint32_t config; |
---|
670 | uint32_t iret; |
---|
671 | } CPU_Exception_frame; |
---|
672 | |
---|
673 | /** |
---|
674 | * @brief Prints the exception frame via printk(). |
---|
675 | * |
---|
676 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
---|
677 | */ |
---|
678 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
679 | |
---|
680 | |
---|
681 | /* end of Priority handler macros */ |
---|
682 | |
---|
683 | /* functions */ |
---|
684 | |
---|
685 | /* |
---|
686 | * _CPU_Initialize |
---|
687 | * |
---|
688 | * This routine performs CPU dependent initialization. |
---|
689 | * |
---|
690 | */ |
---|
691 | |
---|
692 | void _CPU_Initialize( |
---|
693 | void |
---|
694 | ); |
---|
695 | |
---|
696 | /* |
---|
697 | * _CPU_ISR_install_raw_handler |
---|
698 | * |
---|
699 | * This routine installs a "raw" interrupt handler directly into the |
---|
700 | * processor's vector table. |
---|
701 | * |
---|
702 | */ |
---|
703 | |
---|
704 | void _CPU_ISR_install_raw_handler( |
---|
705 | uint32_t vector, |
---|
706 | proc_ptr new_handler, |
---|
707 | proc_ptr *old_handler |
---|
708 | ); |
---|
709 | |
---|
710 | /* |
---|
711 | * _CPU_ISR_install_vector |
---|
712 | * |
---|
713 | * This routine installs an interrupt vector. |
---|
714 | * |
---|
715 | * NO_CPU Specific Information: |
---|
716 | * |
---|
717 | * XXX document implementation including references if appropriate |
---|
718 | */ |
---|
719 | |
---|
720 | void _CPU_ISR_install_vector( |
---|
721 | uint32_t vector, |
---|
722 | proc_ptr new_handler, |
---|
723 | proc_ptr *old_handler |
---|
724 | ); |
---|
725 | |
---|
726 | /* |
---|
727 | * _CPU_Install_interrupt_stack |
---|
728 | * |
---|
729 | * This routine installs the hardware interrupt stack pointer. |
---|
730 | * |
---|
731 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
732 | * is TRUE. |
---|
733 | * |
---|
734 | */ |
---|
735 | |
---|
736 | void _CPU_Install_interrupt_stack( void ); |
---|
737 | |
---|
738 | /* |
---|
739 | * _CPU_Thread_Idle_body |
---|
740 | * |
---|
741 | * This routine is the CPU dependent IDLE thread body. |
---|
742 | * |
---|
743 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
744 | * is TRUE. |
---|
745 | * |
---|
746 | */ |
---|
747 | |
---|
748 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
749 | |
---|
750 | /* |
---|
751 | * _CPU_Context_switch |
---|
752 | * |
---|
753 | * This routine switches from the run context to the heir context. |
---|
754 | * |
---|
755 | * epiphany Specific Information: |
---|
756 | * |
---|
757 | * Please see the comments in the .c file for a description of how |
---|
758 | * this function works. There are several things to be aware of. |
---|
759 | */ |
---|
760 | |
---|
761 | void _CPU_Context_switch( |
---|
762 | Context_Control *run, |
---|
763 | Context_Control *heir |
---|
764 | ); |
---|
765 | |
---|
766 | /* |
---|
767 | * _CPU_Context_restore |
---|
768 | * |
---|
769 | * This routine is generally used only to restart self in an |
---|
770 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
771 | * |
---|
772 | * NOTE: May be unnecessary to reload some registers. |
---|
773 | * |
---|
774 | */ |
---|
775 | |
---|
776 | void _CPU_Context_restore( |
---|
777 | Context_Control *new_context |
---|
778 | ) RTEMS_NO_RETURN; |
---|
779 | |
---|
780 | /* |
---|
781 | * _CPU_Context_save_fp |
---|
782 | * |
---|
783 | * This routine saves the floating point context passed to it. |
---|
784 | * |
---|
785 | */ |
---|
786 | |
---|
787 | void _CPU_Context_save_fp( |
---|
788 | void **fp_context_ptr |
---|
789 | ); |
---|
790 | |
---|
791 | /* |
---|
792 | * _CPU_Context_restore_fp |
---|
793 | * |
---|
794 | * This routine restores the floating point context passed to it. |
---|
795 | * |
---|
796 | */ |
---|
797 | |
---|
798 | void _CPU_Context_restore_fp( |
---|
799 | void **fp_context_ptr |
---|
800 | ); |
---|
801 | |
---|
802 | /* The following routine swaps the endian format of an unsigned int. |
---|
803 | * It must be static because it is referenced indirectly. |
---|
804 | * |
---|
805 | * This version will work on any processor, but if there is a better |
---|
806 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
807 | * |
---|
808 | * swap least significant two bytes with 16-bit rotate |
---|
809 | * swap upper and lower 16-bits |
---|
810 | * swap most significant two bytes with 16-bit rotate |
---|
811 | * |
---|
812 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
813 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
814 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
815 | * that interrupts would probably have to be disabled to insure that |
---|
816 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
817 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
818 | * endianness for ALL fetches -- both code and data -- so the code |
---|
819 | * will be fetched incorrectly. |
---|
820 | * |
---|
821 | */ |
---|
822 | |
---|
823 | static inline unsigned int CPU_swap_u32( |
---|
824 | unsigned int value |
---|
825 | ) |
---|
826 | { |
---|
827 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
828 | |
---|
829 | byte4 = (value >> 24) & 0xff; |
---|
830 | byte3 = (value >> 16) & 0xff; |
---|
831 | byte2 = (value >> 8) & 0xff; |
---|
832 | byte1 = value & 0xff; |
---|
833 | |
---|
834 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
835 | return( swapped ); |
---|
836 | } |
---|
837 | |
---|
838 | #define CPU_swap_u16( value ) \ |
---|
839 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
840 | |
---|
841 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
842 | { |
---|
843 | /* TODO */ |
---|
844 | } |
---|
845 | |
---|
846 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
847 | { |
---|
848 | while (1) { |
---|
849 | /* TODO */ |
---|
850 | } |
---|
851 | } |
---|
852 | |
---|
853 | typedef uint32_t CPU_Counter_ticks; |
---|
854 | |
---|
855 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
856 | |
---|
857 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
858 | CPU_Counter_ticks second, |
---|
859 | CPU_Counter_ticks first |
---|
860 | ) |
---|
861 | { |
---|
862 | return second - first; |
---|
863 | } |
---|
864 | |
---|
865 | #endif /* ASM */ |
---|
866 | |
---|
867 | #ifdef __cplusplus |
---|
868 | } |
---|
869 | #endif |
---|
870 | |
---|
871 | #endif |
---|