1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPU |
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5 | * |
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6 | * @brief This include file contains macros pertaining to the |
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7 | * Epiphany processor family. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2015 University of York. |
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12 | * Hesham ALMatary <hmka501@york.ac.uk> |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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29 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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30 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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31 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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32 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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33 | * SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #ifndef _EPIPHANY_UTILITY_H |
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37 | #define _EPIPHANY_UTILITY_H |
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38 | |
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39 | /* eCore IRQs */ |
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40 | typedef enum |
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41 | { |
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42 | START, |
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43 | SW_EXCEPTION, |
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44 | MEM_FAULT, |
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45 | TIMER0, |
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46 | TIMER1, |
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47 | SMP_MESSAGE, |
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48 | DMA0, |
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49 | DMA1, |
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50 | SER, |
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51 | } EPIPHANY_IRQ_PER_CORE_T; |
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52 | |
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53 | /* Per-core IO mapped register addresses |
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54 | * @see Epiphany architecture reference. |
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55 | */ |
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56 | #define EPIPHANY_PER_CORE_REG_CONFIG 0xF0400 |
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57 | #define EPIPHANY_PER_CORE_REG_STATUS 0xF0404 |
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58 | #define EPIPHANY_PER_CORE_REG_PC 0xF0408 |
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59 | #define EPIPHANY_PER_CORE_REG_DEBUGSTATUS 0xF040C |
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60 | #define EPIPHANY_PER_CORE_REG_LC 0xF0414 |
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61 | #define EPIPHANY_PER_CORE_REG_LS 0xF0418 |
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62 | #define EPIPHANY_PER_CORE_REG_LE 0xF041C |
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63 | #define EPIPHANY_PER_CORE_REG_IRET 0xF0420 |
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64 | #define EPIPHANY_PER_CORE_REG_IMASK 0xF0424 |
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65 | #define EPIPHANY_PER_CORE_REG_ILAT 0xF0428 |
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66 | #define EPIPHANY_PER_CORE_REG_ILATST 0xF042C |
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67 | #define EPIPHANY_PER_CORE_REG_ILATCL 0xF0430 |
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68 | #define EPIPHANY_PER_CORE_REG_IPEND 0xF0434 |
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69 | #define EPIPHANY_PER_CORE_REG_FSTATUS 0xF0440 |
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70 | #define EPIPHANY_PER_CORE_REG_DEBUGCMD 0xF0448 |
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71 | #define EPIPHANY_PER_CORE_REG_RESETCORE 0xF070C |
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72 | |
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73 | /* Event timer registers */ |
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74 | #define EPIPHANY_PER_CORE_REG_CTIMER0 0xF0438 |
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75 | #define EPIPHANY_PER_CORE_REG_CTIMER1 0xF043C |
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76 | |
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77 | /* Processor control registers */ |
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78 | #define EPIPHANY_PER_CORE_REG_MEMSTATUS 0xF0604 |
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79 | #define EPIPHANY_PER_CORE_REG_MEMPROTECT 0xF0608 |
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80 | |
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81 | /* DMA Registers */ |
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82 | #define EPIPHANY_PER_CORE_REG_DMA0CONFIG 0xF0500 |
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83 | #define EPIPHANY_PER_CORE_REG_DMA0STRIDE 0xF0504 |
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84 | #define EPIPHANY_PER_CORE_REG_DMA0COUNT 0xF0508 |
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85 | #define EPIPHANY_PER_CORE_REG_DMA0SRCADDR 0xF050C |
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86 | #define EPIPHANY_PER_CORE_REG_DMA0DSTADDR 0xF0510 |
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87 | #define EPIPHANY_PER_CORE_REG_DMA0AUTO0 0xF0514 |
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88 | #define EPIPHANY_PER_CORE_REG_DMA0AUTO1 0xF0518 |
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89 | #define EPIPHANY_PER_CORE_REG_DMA0STATUS 0xF051C |
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90 | #define EPIPHANY_PER_CORE_REG_DMA1CONFIG 0xF0520 |
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91 | #define EPIPHANY_PER_CORE_REG_DMA1STRIDE 0xF0524 |
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92 | #define EPIPHANY_PER_CORE_REG_DMA1COUNT 0xF0528 |
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93 | #define EPIPHANY_PER_CORE_REG_DMA1SRCADDR 0xF052C |
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94 | #define EPIPHANY_PER_CORE_REG_DMA1DSTADDR 0xF0530 |
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95 | #define EPIPHANY_PER_CORE_REG_DMA1AUTO0 0xF0534 |
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96 | #define EPIPHANY_PER_CORE_REG_DMA1AUTO1 0xF0538 |
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97 | #define EPIPHANY_PER_CORE_REG_DMA1STATUS 0xF053C |
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98 | |
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99 | /* Mesh Node Control Registers */ |
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100 | #define EPIPHANY_PER_CORE_REG_MESHCONFIG 0xF0700 |
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101 | #define EPIPHANY_PER_CORE_REG_COREID 0xF0704 |
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102 | #define EPIPHANY_PER_CORE_REG_MULTICAST 0xF0708 |
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103 | #define EPIPHANY_PER_CORE_REG_CMESHROUTE 0xF0710 |
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104 | #define EPIPHANY_PER_CORE_REG_XMESHROUTE 0xF0714 |
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105 | #define EPIPHANY_PER_CORE_REG_RMESHROUTE 0xF0718 |
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106 | |
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107 | /* This macros constructs an address space of epiphany cores |
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108 | * from their IDs. |
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109 | */ |
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110 | #define EPIPHANY_COREID_TO_MSB_ADDR(id) (id) << 20 |
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111 | |
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112 | /* Construct a complete/absolute IO mapped address register from |
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113 | * core ID and register name |
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114 | */ |
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115 | #define EPIPHANY_GET_REG_ABSOLUTE_ADDR(coreid, reg) \ |
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116 | (EPIPHANY_COREID_TO_MSB_ADDR(coreid) | (reg)) |
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117 | |
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118 | #define EPIPHANY_REG(reg) (uint32_t *) (reg) |
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119 | |
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120 | /* Read register with its absolute address */ |
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121 | static inline uint32_t read_epiphany_reg(volatile uint32_t reg_addr) |
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122 | { |
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123 | return *(EPIPHANY_REG(reg_addr)); |
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124 | } |
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125 | |
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126 | /* Write register with its abolute address */ |
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127 | static inline void write_epiphany_reg(volatile uint32_t reg_addr, uint32_t val) |
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128 | { |
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129 | *(EPIPHANY_REG(reg_addr)) = val; |
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130 | } |
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131 | |
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132 | /* Epiphany uses 12 bits for defining core IDs, while RTEMS uses |
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133 | * linear IDs. The following function converts RTEMS linear IDs to |
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134 | * Epiphany corresponding ones |
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135 | */ |
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136 | static const uint32_t map[16] = |
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137 | { |
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138 | 0x808, 0x809, 0x80A, 0x80B, |
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139 | 0x848, 0x849, 0x84A, 0x84B, |
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140 | 0x888, 0x889, 0x88A, 0x88B, |
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141 | 0x8C8, 0x8C9, 0x8CA, 0x8CB |
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142 | }; |
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143 | |
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144 | static inline uint32_t rtems_coreid_to_epiphany_map(uint32_t rtems_id) |
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145 | { |
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146 | return map[rtems_id]; |
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147 | } |
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148 | |
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149 | /* Epiphany uses 12 bits for defining core IDs, while RTEMS uses |
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150 | * linear IDs. The following function is used to map Epiphany IDs to |
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151 | * RTEMS linear IDs. |
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152 | */ |
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153 | static inline uint32_t epiphany_coreid_to_rtems_map(uint32_t epiphany_id) |
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154 | { |
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155 | register uint32_t coreid asm ("r17") = epiphany_id; |
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156 | |
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157 | /* Mapping from Epiphany IDs to 0-16 IDs macro */ |
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158 | __asm__ __volatile__(" \ |
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159 | movfs r17, coreid \ |
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160 | mov r19, #0x003 \ |
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161 | mov r20, #0x0F0 \ |
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162 | and r19, r17, r19 \ |
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163 | and r20, r17, r20 \ |
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164 | lsr r20, r20, #4 \ |
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165 | add r17, r19, r20 \ |
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166 | "); |
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167 | |
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168 | /* coreid or r17 now holds the rtems core id */ |
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169 | return coreid; |
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170 | } |
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171 | |
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172 | static inline uint32_t _Epiphany_Get_current_processor(void) |
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173 | { |
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174 | uint32_t coreid; |
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175 | |
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176 | asm volatile ("movfs %0, coreid" : "=r" (coreid): ); |
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177 | |
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178 | return epiphany_coreid_to_rtems_map(coreid); |
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179 | } |
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180 | #endif /* _EPIPHANY_UTILITY_H */ |
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