1 | /* |
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2 | * Epiphany CPU Dependent Source |
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3 | * |
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4 | * Copyright (c) 2015 University of York. |
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5 | * Hesham ALMatary <hmka501@york.ac.uk> |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * |
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16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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26 | * SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | #ifdef HAVE_CONFIG_H |
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30 | #include "config.h" |
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31 | #endif |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | |
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35 | .section .text,"ax" |
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36 | .align 4 |
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37 | |
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38 | PUBLIC(_CPU_Context_switch) |
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39 | PUBLIC(_CPU_Context_restore) |
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40 | PUBLIC(_CPU_Context_restore_fp) |
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41 | PUBLIC(_CPU_Context_save_fp) |
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42 | PUBLIC(restore) |
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43 | |
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44 | SYM(_CPU_Context_switch): |
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45 | /* Disable interrupts and store all registers */ |
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46 | gid |
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47 | |
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48 | str r0, [r0] |
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49 | str r1, [r0,1] |
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50 | str r2, [r0,2] |
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51 | str r3, [r0,3] |
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52 | str r4, [r0,4] |
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53 | str r5, [r0,5] |
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54 | str r6, [r0,6] |
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55 | str r7, [r0,7] |
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56 | str r8, [r0,8] |
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57 | str r9, [r0,9] |
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58 | str r10, [r0,10] |
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59 | str fp, [r0,11] |
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60 | str r12, [r0,12] |
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61 | str sp, [r0,13] |
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62 | str lr, [r0,14] |
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63 | str r15, [r0,15] |
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64 | str r16, [r0,16] |
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65 | str r17, [r0,17] |
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66 | str r18, [r0,18] |
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67 | str r19, [r0,19] |
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68 | str r20, [r0,20] |
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69 | str r21, [r0,21] |
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70 | str r22, [r0,22] |
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71 | str r23, [r0,23] |
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72 | str r24, [r0,24] |
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73 | str r25, [r0,25] |
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74 | str r26, [r0,26] |
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75 | str r27, [r0,27] |
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76 | str r28, [r0,28] |
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77 | str r29, [r0,29] |
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78 | str r30, [r0,30] |
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79 | str r31, [r0,31] |
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80 | str r32, [r0,32] |
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81 | str r33, [r0,33] |
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82 | str r34, [r0,34] |
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83 | str r35, [r0,35] |
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84 | str r36, [r0,36] |
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85 | str r37, [r0,37] |
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86 | str r38, [r0,38] |
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87 | str r39, [r0,39] |
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88 | str r40, [r0,40] |
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89 | str r41, [r0,41] |
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90 | str r42, [r0,42] |
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91 | str r43, [r0,43] |
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92 | str r44, [r0,44] |
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93 | str r45, [r0,45] |
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94 | str r46, [r0,46] |
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95 | str r47, [r0,47] |
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96 | str r48, [r0,48] |
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97 | str r49, [r0,49] |
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98 | str r50, [r0,50] |
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99 | str r51, [r0,51] |
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100 | str r52, [r0,52] |
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101 | str r53, [r0,53] |
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102 | str r54, [r0,54] |
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103 | str r55, [r0,55] |
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104 | str r56, [r0,56] |
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105 | str r57, [r0,57] |
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106 | str r58, [r0,58] |
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107 | str r59, [r0,59] |
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108 | str r60, [r0,60] |
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109 | str r61, [r0,61] |
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110 | str r62, [r0,62] |
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111 | str r63, [r0,63] |
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112 | |
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113 | /* Store status register */ |
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114 | movfs r27, status |
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115 | str r27, [r0,64] |
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116 | |
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117 | /* Store config register */ |
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118 | movfs r27, config |
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119 | str r27, [r0,65] |
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120 | |
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121 | /* Store interrupt return address register */ |
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122 | movfs r27, iret |
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123 | str r27, [r0,66] |
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124 | |
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125 | SYM(restore): |
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126 | |
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127 | /* r1 contains buffer address, skip it */ |
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128 | ldr r2, [r1,2] |
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129 | ldr r3, [r1,3] |
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130 | ldr r4, [r1,4] |
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131 | ldr r5, [r1,5] |
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132 | ldr r6, [r1,6] |
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133 | ldr r7, [r1,7] |
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134 | ldr r8, [r1,8] |
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135 | ldr r9, [r1,9] |
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136 | ldr r10, [r1,10] |
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137 | ldr fp, [r1,11] |
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138 | ldr r12, [r1,12] |
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139 | ldr sp, [r1,13] |
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140 | ldr lr, [r1,14] |
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141 | ldr r15, [r1,15] |
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142 | ldr r16, [r1,16] |
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143 | ldr r17, [r1,17] |
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144 | ldr r18, [r1,18] |
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145 | ldr r19, [r1,19] |
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146 | ldr r20, [r1,20] |
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147 | ldr r21, [r1,21] |
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148 | ldr r22, [r1,22] |
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149 | ldr r23, [r1,23] |
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150 | ldr r24, [r1,24] |
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151 | ldr r25, [r1,25] |
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152 | ldr r26, [r1,26] |
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153 | ldr r27, [r1,27] |
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154 | ldr r32, [r1,32] |
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155 | ldr r33, [r1,33] |
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156 | ldr r34, [r1,34] |
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157 | ldr r35, [r1,35] |
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158 | ldr r36, [r1,36] |
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159 | ldr r37, [r1,37] |
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160 | ldr r38, [r1,38] |
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161 | ldr r39, [r1,39] |
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162 | ldr r40, [r1,40] |
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163 | ldr r41, [r1,41] |
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164 | ldr r42, [r1,42] |
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165 | ldr r43, [r1,43] |
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166 | ldr r44, [r1,44] |
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167 | ldr r45, [r1,45] |
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168 | ldr r46, [r1,46] |
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169 | ldr r47, [r1,47] |
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170 | ldr r48, [r1,48] |
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171 | ldr r49, [r1,49] |
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172 | ldr r50, [r1,50] |
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173 | ldr r51, [r1,51] |
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174 | ldr r52, [r1,52] |
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175 | ldr r53, [r1,53] |
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176 | ldr r54, [r1,54] |
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177 | ldr r55, [r1,55] |
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178 | ldr r56, [r1,56] |
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179 | ldr r57, [r1,57] |
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180 | ldr r58, [r1,58] |
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181 | ldr r59, [r1,59] |
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182 | ldr r60, [r1,60] |
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183 | ldr r61, [r1,61] |
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184 | ldr r62, [r1,62] |
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185 | ldr r63, [r1,63] |
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186 | |
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187 | /* Load status register */ |
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188 | ldr r0, [r1,64] |
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189 | movts status, r0 |
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190 | |
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191 | /* Load config register */ |
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192 | ldr r0, [r1,65] |
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193 | movts config, r0 |
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194 | |
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195 | /* Load interrupt return address register */ |
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196 | ldr r0,[r1,66] |
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197 | movts iret, r0 |
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198 | |
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199 | ldr r0,[r1] |
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200 | ldr r1,[r1,1] |
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201 | |
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202 | /* Enable interrupts and return */ |
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203 | gie |
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204 | jr lr |
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205 | |
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206 | SYM(_CPU_Context_restore): |
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207 | mov r1, r0 |
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208 | b _restore |
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209 | nop |
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210 | |
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211 | /* No FP support for Epiphany yet */ |
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212 | SYM(_CPU_Context_restore_fp): |
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213 | nop |
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214 | |
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215 | SYM(_CPU_Context_save_fp): |
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216 | nop |
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