source: rtems/cpukit/score/cpu/epiphany/epiphany-context-switch.S @ 2afb22b

5
Last change on this file since 2afb22b was 66a5000d, checked in by Hesham ALMatary <heshamelmatary@…>, on May 21, 2015 at 4:52:56 PM

cpukit: Add Epiphany architecture port v4

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File size: 4.7 KB
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1/*
2 * Epiphany CPU Dependent Source
3 *
4 * Copyright (c) 2015 University of York.
5 * Hesham ALMatary <hmka501@york.ac.uk>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifdef HAVE_CONFIG_H
30  #include "config.h"
31#endif
32
33#include <rtems/asm.h>
34
35.section .text,"ax"
36.align 4
37
38PUBLIC(_CPU_Context_switch)
39PUBLIC(_CPU_Context_restore)
40PUBLIC(_CPU_Context_restore_fp)
41PUBLIC(_CPU_Context_save_fp)
42PUBLIC(restore)
43
44SYM(_CPU_Context_switch):
45  /* Disable interrupts and store all registers */
46  gid
47
48  str r0,  [r0]
49  str r1,  [r0,1]
50  str r2,  [r0,2]
51  str r3,  [r0,3]
52  str r4,  [r0,4]
53  str r5,  [r0,5]
54  str r6,  [r0,6]
55  str r7,  [r0,7]
56  str r8,  [r0,8]
57  str r9,  [r0,9]
58  str r10, [r0,10]
59  str fp,  [r0,11]
60  str r12, [r0,12]
61  str sp,  [r0,13]
62  str lr,  [r0,14]
63  str r15, [r0,15]
64  str r16, [r0,16]
65  str r17, [r0,17]
66  str r18, [r0,18]
67  str r19, [r0,19]
68  str r20, [r0,20]
69  str r21, [r0,21]
70  str r22, [r0,22]
71  str r23, [r0,23]
72  str r24, [r0,24]
73  str r25, [r0,25]
74  str r26, [r0,26]
75  str r27, [r0,27]
76  str r28, [r0,28]
77  str r29, [r0,29]
78  str r30, [r0,30]
79  str r31, [r0,31]
80  str r32, [r0,32]
81  str r33, [r0,33]
82  str r34, [r0,34]
83  str r35, [r0,35]
84  str r36, [r0,36]
85  str r37, [r0,37]
86  str r38, [r0,38]
87  str r39, [r0,39]
88  str r40, [r0,40]
89  str r41, [r0,41]
90  str r42, [r0,42]
91  str r43, [r0,43]
92  str r44, [r0,44]
93  str r45, [r0,45]
94  str r46, [r0,46]
95  str r47, [r0,47]
96  str r48, [r0,48]
97  str r49, [r0,49]
98  str r50, [r0,50]
99  str r51, [r0,51]
100  str r52, [r0,52]
101  str r53, [r0,53]
102  str r54, [r0,54]
103  str r55, [r0,55]
104  str r56, [r0,56]
105  str r57, [r0,57]
106  str r58, [r0,58]
107  str r59, [r0,59]
108  str r60, [r0,60]
109  str r61, [r0,61]
110  str r62, [r0,62]
111  str r63, [r0,63]
112
113  /* Store status register */
114  movfs r27, status
115  str r27, [r0,64]
116
117  /* Store config register */
118  movfs r27, config
119  str r27, [r0,65]
120
121  /* Store interrupt return address register */
122  movfs r27, iret
123  str r27, [r0,66]
124
125SYM(restore):
126
127  /* r1 contains buffer address, skip it */
128  ldr r2,  [r1,2]
129  ldr r3,  [r1,3]
130  ldr r4,  [r1,4]
131  ldr r5,  [r1,5]
132  ldr r6,  [r1,6]
133  ldr r7,  [r1,7]
134  ldr r8,  [r1,8]
135  ldr r9,  [r1,9]
136  ldr r10, [r1,10]
137  ldr fp,  [r1,11]
138  ldr r12, [r1,12]
139  ldr sp,  [r1,13]
140  ldr lr,  [r1,14]
141  ldr r15, [r1,15]
142  ldr r16, [r1,16]
143  ldr r17, [r1,17]
144  ldr r18, [r1,18]
145  ldr r19, [r1,19]
146  ldr r20, [r1,20]
147  ldr r21, [r1,21]
148  ldr r22, [r1,22]
149  ldr r23, [r1,23]
150  ldr r24, [r1,24]
151  ldr r25, [r1,25]
152  ldr r26, [r1,26]
153  ldr r27, [r1,27]
154  ldr r32, [r1,32]
155  ldr r33, [r1,33]
156  ldr r34, [r1,34]
157  ldr r35, [r1,35]
158  ldr r36, [r1,36]
159  ldr r37, [r1,37]
160  ldr r38, [r1,38]
161  ldr r39, [r1,39]
162  ldr r40, [r1,40]
163  ldr r41, [r1,41]
164  ldr r42, [r1,42]
165  ldr r43, [r1,43]
166  ldr r44, [r1,44]
167  ldr r45, [r1,45]
168  ldr r46, [r1,46]
169  ldr r47, [r1,47]
170  ldr r48, [r1,48]
171  ldr r49, [r1,49]
172  ldr r50, [r1,50]
173  ldr r51, [r1,51]
174  ldr r52, [r1,52]
175  ldr r53, [r1,53]
176  ldr r54, [r1,54]
177  ldr r55, [r1,55]
178  ldr r56, [r1,56]
179  ldr r57, [r1,57]
180  ldr r58, [r1,58]
181  ldr r59, [r1,59]
182  ldr r60, [r1,60]
183  ldr r61, [r1,61]
184  ldr r62, [r1,62]
185  ldr r63, [r1,63]
186
187  /* Load status register */
188  ldr r0, [r1,64]
189  movts status, r0
190
191  /* Load config register */
192  ldr r0, [r1,65]
193  movts config, r0
194
195  /* Load interrupt return address register */
196  ldr r0,[r1,66]
197  movts iret, r0
198
199  ldr r0,[r1]
200  ldr r1,[r1,1]
201
202  /* Enable interrupts and return */
203  gie
204  jr lr
205
206SYM(_CPU_Context_restore):
207  mov     r1, r0
208  b       _restore
209  nop
210
211/* No FP support for Epiphany yet */
212SYM(_CPU_Context_restore_fp):
213  nop
214
215 SYM(_CPU_Context_save_fp):
216  nop
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