source: rtems/cpukit/score/cpu/c4x/rtems/score/c4x.h @ 38e5a9f

4.104.114.84.95
Last change on this file since 38e5a9f was 38e5a9f, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 18, 2000 at 12:57:00 PM

2000-10-18 Joel Sherrill <joel@…>

  • rtems/score/c4x.h: Modified to properly multilib. This required using only macros predefined by gcc.
  • Property mode set to 100644
File size: 8.3 KB
Line 
1/*  c4x.h
2 *
3 *  This file is an example (i.e. "no CPU") of the file which is
4 *  created for each CPU family port of RTEMS.
5 *
6 *
7 *  COPYRIGHT (c) 1989-1999.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 *
16 */
17
18#ifndef _INCLUDE_C4X_h
19#define _INCLUDE_C4X_h
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/*
26 *  This file contains the information required to build
27 *  RTEMS for a particular member of the "no cpu"
28 *  family when executing in protected mode.  It does
29 *  this by setting variables to indicate which implementation
30 *  dependent features are present in a particular member
31 *  of the family.
32 */
33 
34#if defined(_C30)
35#define CPU_MODEL_NAME  "C30"
36
37#elif defined(_C31)
38#define CPU_MODEL_NAME  "C31"
39 
40#elif defined(_C32)
41#define CPU_MODEL_NAME  "C32"
42 
43#elif defined(_C33)
44#define CPU_MODEL_NAME  "C33"
45 
46#elif defined(_C40)
47#define CPU_MODEL_NAME  "C40"
48 
49#elif defined(_C44)
50#define CPU_MODEL_NAME  "C44"
51 
52#else
53 
54#error "Unsupported CPU Model"
55 
56#endif
57
58/*
59 *  Define the name of the CPU family.
60 */
61
62#define CPU_NAME "Texas Instruments C3x/C4x"
63
64/*
65 *  This port is a little unusual in that even though there are "floating
66 *  point registers", the notion of floating point is very inherent to
67 *  applications.  In addition, the calling conventions require that
68 *  only a few extended registers be preserved across subroutine calls.
69 *  The overhead of including these few registers in the basic
70 *  context is small compared to the overhead of managing the notion
71 *  of separate floating point contexts.  So we decided to pretend that
72 *  there is no FPU on the C3x or C4x.
73 */
74
75#define C4X_HAS_FPU  0
76
77/*
78 *  Routines to manipulate the bits in the Status Word (ST).
79 */
80
81#define C4X_ST_C      0x0001
82#define C4X_ST_V      0x0002
83#define C4X_ST_Z      0x0004
84#define C4X_ST_N      0x0008
85#define C4X_ST_UF     0x0010
86#define C4X_ST_LV     0x0020
87#define C4X_ST_LUF    0x0040
88#define C4X_ST_OVM    0x0080
89#define C4X_ST_RM     0x0100
90#define C4X_ST_CF     0x0400
91#define C4X_ST_CE     0x0800
92#define C4X_ST_CC     0x1000
93#define C4X_ST_GIE    0x2000
94
95#ifndef _TMS320C40
96#define C3X_IE_INTERRUPT_MASK_BITS     0xffff
97#define C3x_IE_INTERRUPTS_ALL_ENABLED  0x0000
98#define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff
99#endif
100
101#ifndef ASM
102
103/*
104 *  A nop macro.
105 */
106
107#define c4x_nop() \
108  __asm__("nop");
109
110/*
111 *  Routines to set and clear individual bits in the ST (status word).
112 *
113 *  cpu_st_bit_clear  - clear bit in ST
114 *  cpu_st_bit_set    - set bit in ST
115 *  cpu_st_get        - obtain entire ST
116 */
117
118#ifdef _TMS320C40
119#define c4x_gie_nop()
120#else
121#define c4x_gie_nop() { c4x_nop(); c4x_nop(); }
122#endif
123
124#define cpu_st_bit_clear(_st_bit) \
125  do { \
126    __asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \
127    c4x_gie_nop(); \
128  } while (0)
129
130#define cpu_st_bit_set(_st_bit) \
131  do { \
132    __asm__("or %0,st" : : "g" (_st_bit) : "cc"); \
133    c4x_gie_nop(); \
134  } while (0)
135
136static inline unsigned int cpu_st_get(void)
137{
138  register unsigned int st_value;
139  __asm__("ldi st, %0" : "=r" (st_value));
140  return st_value;
141}
142
143/*
144 *  Routines to manipulate the Global Interrupt Enable (GIE) bit in
145 *  the Status Word (ST).
146 *
147 *  c4x_global_interrupts_get      - returns current GIE setting
148 *  c4x_global_interrupts_disable  - disables global interrupts
149 *  c4x_global_interrupts_enable   - enables global interrupts
150 *  c4x_global_interrupts_restore  - restores GIE to pre-disable state
151 *  c4x_global_interrupts_flash    - temporarily enable global interrupts
152 */
153
154#define c4x_global_interrupts_get() \
155  (cpu_st_get() & C4X_ST_GIE)
156 
157#define c4x_global_interrupts_disable() \
158  cpu_st_bit_clear(C4X_ST_GIE)
159
160#define c4x_global_interrupts_enable() \
161  cpu_st_bit_set(C4X_ST_GIE)
162
163#define c4x_global_interrupts_restore(_old_level) \
164  cpu_st_bit_set(_old_level)
165
166#define c4x_global_interrupts_flash(_old_level) \
167  do { \
168    cpu_st_bit_set(_old_level); \
169    cpu_st_bit_clear(C4X_ST_GIE); \
170  } while (0)
171
172#ifndef _TMS320C40
173
174/*
175 *  Routines to set and get the IF register
176 *
177 *  c3x_get_if     - obtains IF register
178 *  c3x_set_if     - sets IF register
179 */
180
181static inline unsigned int c3x_get_if(void)
182{
183  register unsigned int _if_value;
184
185  __asm__( "ldi if, %0" : "=r" (_if_value) );
186  return _if_value;
187}
188
189static inline void c3x_set_if(unsigned int _if_value)
190{
191  __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); 
192}
193
194/*
195 *  Routines to set and get the IE register
196 *
197 *  c3x_get_ie     - obtains IE register
198 *  c3x_set_ie     - sets IE register
199 */
200
201static inline unsigned int c3x_get_ie(void)
202{
203  register unsigned int _ie_value;
204
205  __asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) );
206  return _ie_value;
207}
208
209static inline void c3x_set_ie(unsigned int _ie_value)
210{
211  __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); 
212}
213
214/*
215 *  Routines to manipulates the mask portion of the IE register.
216 *
217 *  c3x_ie_mask_all     - returns previous IE mask
218 *  c3x_ie_mask_restore - restores previous IE mask
219 *  c3x_ie_mask_flash   - temporarily restores previous IE mask
220 *  c3x_ie_mask_set     - sets a specific set of the IE mask
221 */
222 
223#define c3x_ie_mask_all( _isr_cookie ) \
224  do { \
225    __asm__("ldi  ie,%0\n" \
226            "\tandn 0ffffh, ie" \
227          : "=r" (_isr_cookie): : "ie", "cc" ); \
228  } while (0)
229
230#define c3x_ie_mask_restore( _isr_cookie )  \
231  do { \
232    __asm__("or %0, ie" \
233          : : "g" (_isr_cookie) : "ie", "cc" ); \
234  } while (0)
235
236#define c3x_ie_mask_flash( _isr_cookie ) \
237  do { \
238    __asm__("or %0, ie\n" \
239           "\tandn 0ffffh, ie" \
240          : : "g" (_isr_cookie) : "ie", "cc" ); \
241  } while (0)
242
243#define c3x_ie_mask_set( _new_mask ) \
244  do { unsigned int _ie_mask; \
245    unsigned int _ie_value; \
246    \
247    if ( _new_mask == 0 ) _ie_mask = 0; \
248    else                  _ie_mask = 0xffff; \
249    _ie_value = c3x_get_ie(); \
250    _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \
251    _ie_value |= _ie_mask; \
252    c3x_set_ie(_ie_value); \
253  } while (0)
254#endif
255/* end of C3x specific interrupt flag routines */
256
257/*
258 *  This is a section of C4x specific interrupt flag management routines.
259 */
260
261#ifdef _TMS320C40
262
263/*
264 *  Routines to set and get the IIF register
265 *
266 *  c4x_get_iif     - obtains IIF register
267 *  c4x_set_iif     - sets IIF register
268 */
269
270static inline unsigned int c4x_get_iif(void)
271{
272  register unsigned int _iif_value;
273
274  __asm__( "ldi iif, %0" : "=r" (_iif_value) );
275  return _iif_value;
276}
277
278static inline void c4x_set_iif(unsigned int _iif_value)
279{
280  __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); 
281}
282
283/*
284 *  Routines to set and get the IIE register
285 *
286 *  c4x_get_iie     - obtains IIE register
287 *  c4x_set_iie     - sets IIE register
288 */
289
290static inline unsigned int c4x_get_iie(void)
291{
292  register unsigned int _iie_value;
293
294  __asm__( "ldi iie, %0" : "=r" (_iie_value) );
295  return _iie_value;
296}
297
298static inline void c4x_set_iie(unsigned int _iie_value)
299{
300  __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); 
301}
302
303/*
304 *  Routines to manipulates the mask portion of the IIE register.
305 *
306 *  c4x_ie_mask_all     - returns previous IIE mask
307 *  c4x_ie_mask_restore - restores previous IIE mask
308 *  c4x_ie_mask_flash   - temporarily restores previous IIE mask
309 *  c4x_ie_mask_set     - sets a specific set of the IIE mask
310 */
311
312#if 0
313#warning "C4x IIE masking routines not implemented."
314#define c4x_iie_mask_all( _isr_cookie )
315#define c4x_iie_mask_restore( _isr_cookie )
316#define c4x_iie_mask_flash( _isr_cookie )
317#define c4x_iie_mask_set( _new_mask )
318#endif
319
320#endif
321/* end of C4x specific interrupt flag routines */
322
323/*
324 *  Routines to access the Interrupt Trap Table Pointer
325 *
326 *  c4x_get_ittp    - get ITTP
327 *  c4x_set_ittp    - set ITTP
328 */
329
330static inline void * c4x_get_ittp(void)
331{ 
332  register unsigned int _if_value;
333 
334  __asm__( "ldi if, %0" : "=r" (_if_value) );
335  return (void *)((_if_value & 0xffff0000) >> 8); 
336} 
337
338static inline void c4x_set_ittp(void *_ittp_value)
339{ 
340  unsigned int _if_value;
341  unsigned int _ittp_field;
342
343#ifdef _TMS320C40
344  _if_value = c4x_get_iif();
345#else
346  _if_value = c3x_get_if();
347#endif
348  _if_value &= 0xffff;
349  _ittp_field = (((unsigned int) _ittp_value) >> 8);
350  _if_value |= _ittp_field << 16 ;
351#ifdef _TMS320C40
352  c4x_set_iif( _if_value );
353#else
354  c3x_set_if( _if_value );
355#endif
356} 
357
358#endif /* ifndef ASM */
359
360#ifdef __cplusplus
361}
362#endif
363
364#endif /* ! _INCLUDE_C4X_h */
365/* end of include file */
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