source: rtems/cpukit/score/cpu/c4x/irq.c @ 7a28ac8

4.104.11
Last change on this file since 7a28ac8 was 7a28ac8, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 10, 2008 at 3:41:37 PM

2008-09-10 Joel Sherrill <joel.sherrill@…>

  • configure.ac, aclocal/canonical-target-name.m4: Readd NIOS2 and TI C4x. Accidentally not done on 4.9 branch. :(
  • score/cpu/c4x/.cvsignore, score/cpu/c4x/ChangeLog, score/cpu/c4x/Makefile.am, score/cpu/c4x/cpu.c, score/cpu/c4x/cpu_asm.S, score/cpu/c4x/irq.c, score/cpu/c4x/preinstall.am, score/cpu/c4x/rtems/asm.h, score/cpu/c4x/rtems/score/c4x.h, score/cpu/c4x/rtems/score/cpu.h, score/cpu/c4x/rtems/score/cpu_asm.h, score/cpu/c4x/rtems/score/types.h, score/cpu/c4x/rtems/tic4x/c4xio.h, score/cpu/nios2/.cvsignore, score/cpu/nios2/ChangeLog, score/cpu/nios2/Makefile.am, score/cpu/nios2/cpu.c, score/cpu/nios2/cpu_asm.S, score/cpu/nios2/irq.c, score/cpu/nios2/preinstall.am, score/cpu/nios2/rtems/asm.h, score/cpu/nios2/rtems/score/cpu.h, score/cpu/nios2/rtems/score/cpu_asm.h, score/cpu/nios2/rtems/score/nios2.h, score/cpu/nios2/rtems/score/types.h: New files.
  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 *  C4x CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#include <rtems/system.h>
16#include <rtems/score/cpu.h>
17#include <rtems/score/isr.h>
18#include <rtems/score/thread.h>
19
20/*
21 *  This routine provides the RTEMS interrupt management.
22 */
23
24#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
25  unsigned long    *_old_stack_ptr;
26#endif
27
28register unsigned long  *stack_ptr asm("sp");
29
30void __ISR_Handler(uint32_t   vector, void *isr_sp)
31{
32  register uint32_t   level;
33
34  /* already disabled when we get here */
35  /* _CPU_ISR_Disable( level ); */
36
37  _Thread_Dispatch_disable_level++;
38
39#if 0
40  if ( stack_ptr > (_Thread_Executing->Start.stack +
41            _Thread_Executing->Start.Initial_stack.size) ) {
42    printk( "Blown interrupt stack at 0x%x\n", stack_ptr );
43  }
44#endif
45
46#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
47  if ( _ISR_Nest_level == 0 ) {
48    /* Install irq stack */
49    _old_stack_ptr = stack_ptr;
50    stack_ptr = _CPU_Interrupt_stack_low;
51  }
52#endif
53
54  _ISR_Nest_level++;
55
56  /* leave it to the ISR to decide if they get reenabled */
57  /* _CPU_ISR_Enable( level ); */
58
59  /* call isp */
60  if ( _ISR_Vector_table[ vector] )
61    (*_ISR_Vector_table[ vector ])(
62       vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 );
63
64  _CPU_ISR_Disable( level );
65
66  _ISR_Nest_level--;
67
68#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
69  if ( _ISR_Nest_level == 0 )       /* restore old stack pointer */
70    stack_ptr = _old_stack_ptr;
71#endif
72
73  _Thread_Dispatch_disable_level--;
74
75  _CPU_ISR_Enable( level );
76
77  if ( _ISR_Nest_level )
78    return;
79
80  if ( _Thread_Dispatch_disable_level ) {
81    _ISR_Signals_to_thread_executing = FALSE;
82    return;
83  }
84
85  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
86    _ISR_Signals_to_thread_executing = FALSE;
87    _Thread_Dispatch();
88  }
89}
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