1 | /* cpu_asm.c ===> cpu_asm.S or cpu_asm.s |
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2 | * |
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3 | * This file contains the basic algorithms for all assembly code used |
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4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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5 | * in assembly language |
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6 | * |
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7 | * NOTE: This is supposed to be a .S or .s file NOT a C file. |
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8 | * |
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9 | * COPYRIGHT (c) 1989-1999. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #ifdef HAVE_CONFIG_H |
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20 | #include "config.h" |
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21 | #endif |
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22 | |
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23 | #include <rtems/asm.h> |
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24 | |
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25 | /* |
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26 | * _CPU_Context_save_fp_context |
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27 | * |
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28 | * This routine is responsible for saving the FP context |
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29 | * at *fp_context_ptr. If the point to load the FP context |
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30 | * from is changed then the pointer is modified by this routine. |
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31 | * |
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32 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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33 | * the ** and a similarly named routine in this file is passed something |
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34 | * like a (Context_Control_fp *). The general rule on making this decision |
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35 | * is to avoid writing assembly language. |
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36 | * |
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37 | * void _CPU_Context_save_fp( |
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38 | * void **fp_context_ptr |
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39 | * |
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40 | * C4x Specific Information: |
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41 | * |
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42 | * There is no distiniction between FP and integer context in this port. |
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43 | */ |
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44 | |
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45 | /* |
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46 | * _CPU_Context_restore_fp_context |
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47 | * |
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48 | * This routine is responsible for restoring the FP context |
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49 | * at *fp_context_ptr. If the point to load the FP context |
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50 | * from is changed then the pointer is modified by this routine. |
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51 | * |
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52 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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53 | * the ** and a similarly named routine in this file is passed something |
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54 | * like a (Context_Control_fp *). The general rule on making this decision |
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55 | * is to avoid writing assembly language. |
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56 | * |
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57 | * void _CPU_Context_restore_fp( |
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58 | * void **fp_context_ptr |
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59 | * ) |
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60 | * |
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61 | * C4x Specific Information: |
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62 | * |
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63 | * There is no distiniction between FP and integer context in this port. |
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64 | */ |
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65 | |
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66 | |
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67 | /* _CPU_Context_switch |
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68 | * |
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69 | * This routine performs a normal non-FP context switch. |
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70 | * |
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71 | * void _CPU_Context_switch( |
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72 | * Context_Control *run, |
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73 | * Context_Control *heir |
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74 | * ) |
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75 | * |
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76 | * TMS320C3x General-Purpose Applications User's Guide, section 2.4 |
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77 | * (p 2-11 and following), Context Switching in Interrupts and |
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78 | * Subroutines states that "If the program is in a subroutine, it |
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79 | * must preserve the dedicated C registers as follows:" |
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80 | * |
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81 | * Save as Integers Save as Floating-Point |
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82 | * ================ ====================== |
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83 | * R4 R8 R6 R7 |
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84 | * AR4 AR5 |
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85 | * AR6 AR7 |
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86 | * FP DP (small model only) |
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87 | * SP |
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88 | */ |
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89 | |
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90 | .global SYM(_CPU_Context_switch) |
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91 | SYM(_CPU_Context_switch): |
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92 | .if .REGPARM == 0 |
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93 | ldi sp, ar0 |
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94 | ldi *ar0, ar2 ; get the location of running context |
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95 | .endif |
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96 | sti st,*ar2++ ; store status word |
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97 | sti ar3,*ar2++ ; store ar3 |
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98 | sti ar4,*ar2++ ; store ar4 |
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99 | sti ar5,*ar2++ ; store ar5 |
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100 | sti ar6,*ar2++ ; store ar6 |
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101 | sti ar7,*ar2++ ; store ar7 |
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102 | sti r4,*ar2++ ; store integer portion of r4 |
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103 | sti r5,*ar2++ ; store integer portion of r5 |
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104 | stf r6,*ar2++ ; store float portion of r6 |
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105 | stf r7,*ar2++ ; store float portion of r7 |
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106 | .if .TMS320C40 |
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107 | sti r8,*ar2++ ; store integer portion of r8 |
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108 | .endif |
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109 | sti sp,*ar2++ ; store sp |
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110 | |
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111 | ; end of save |
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112 | |
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113 | .if .REGPARM == 0 |
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114 | ldi *-ar0(2), ar2 ; get the location of heir context |
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115 | .else |
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116 | ldi r2,ar2 |
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117 | .endif |
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118 | _local_restore: |
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119 | ldi *ar2++,ar0 ; load status word into register |
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120 | ldi *ar2++,ar3 ; load ar3 |
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121 | ldi *ar2++,ar4 ; load ar4 |
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122 | ldi *ar2++,ar5 ; load ar5 |
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123 | ldi *ar2++,ar6 ; load ar6 |
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124 | ldi *ar2++,ar7 ; load ar7 |
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125 | ldi *ar2++,r4 ; load integer portion of r4 |
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126 | ldi *ar2++,r5 ; load integer portion of r5 |
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127 | ldf *ar2++,r6 ; load float portion of r6 |
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128 | ldf *ar2++,r7 ; load float portion of r7 |
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129 | .if .TMS320C40 |
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130 | ldi *ar2++,r8 ; load integer portion of r8 |
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131 | .endif |
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132 | ldi *ar2++,sp ; load sp |
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133 | ldi ar0,st ; restore status word and interrupts |
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134 | rets |
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135 | |
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136 | /* |
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137 | * _CPU_Context_restore |
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138 | * |
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139 | * This routine is generally used only to restart self in an |
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140 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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141 | * |
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142 | * NOTE: May be unnecessary to reload some registers. |
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143 | * |
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144 | * void _CPU_Context_restore( |
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145 | * Context_Control *new_context |
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146 | * ) |
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147 | */ |
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148 | |
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149 | .global SYM(_CPU_Context_restore) |
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150 | SYM(_CPU_Context_restore): |
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151 | .if .REGPARM == 0 |
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152 | ldi sp, ar0 |
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153 | ldi *ar0, ar2 ; get the location of context to restore |
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154 | .endif |
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155 | br _local_restore |
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156 | |
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157 | /* void _ISR_Handler() |
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158 | * |
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159 | * This routine provides the RTEMS interrupt management. |
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160 | * |
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161 | * void _ISR_Handler() |
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162 | */ |
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163 | |
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164 | /* |
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165 | * At entry to "common" _ISR_Handler, the vector number must be |
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166 | * available. On some CPUs the hardware puts either the vector |
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167 | * number or the offset into the vector table for this ISR in a |
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168 | * known place. If the hardware does not give us this information, |
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169 | * then the assembly portion of RTEMS for this port will contain |
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170 | * a set of distinct interrupt entry points which somehow place |
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171 | * the vector number in a known place (which is safe if another |
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172 | * interrupt nests this one) and branches to _ISR_Handler. |
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173 | */ |
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174 | |
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175 | /* |
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176 | * save some or all context on stack |
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177 | * may need to save some special interrupt information for exit |
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178 | * |
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179 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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180 | * if ( _ISR_Nest_level == 0 ) |
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181 | * switch to software interrupt stack |
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182 | * #endif |
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183 | * |
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184 | * _ISR_Nest_level++; |
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185 | * |
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186 | * _Thread_Dispatch_disable_level++; |
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187 | * |
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188 | * (*_ISR_Vector_table[ vector ])( vector ); |
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189 | * |
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190 | * --_ISR_Nest_level; |
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191 | * |
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192 | * if ( _ISR_Nest_level ) |
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193 | * goto the label "exit interrupt (simple case)" |
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194 | * |
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195 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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196 | * restore stack |
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197 | * #endif |
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198 | * |
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199 | * if ( !_Context_Switch_necessary ) |
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200 | * goto the label "exit interrupt (simple case)" |
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201 | * |
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202 | * if ( !_ISR_Signals_to_thread_executing ) |
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203 | * _ISR_Signals_to_thread_executing = FALSE; |
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204 | * goto the label "exit interrupt (simple case)" |
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205 | * |
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206 | * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch |
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207 | * |
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208 | * prepare to get out of interrupt |
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209 | * return from interrupt (maybe to _ISR_Dispatch) |
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210 | * |
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211 | * LABEL "exit interrupt (simple case): |
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212 | * prepare to get out of interrupt |
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213 | * return from interrupt |
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214 | */ |
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215 | |
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216 | .global SYM(_ISR_Handler_save_registers) |
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217 | SYM(_ISR_Handler_save_registers): |
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218 | ; no push st because it is already pushed |
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219 | ; no push ar2 because it is already pushed and vector number loaded |
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220 | push ar0 |
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221 | push ar1 |
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222 | push dp |
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223 | push ir0 |
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224 | push ir1 |
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225 | push rs |
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226 | push re |
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227 | push rc |
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228 | push bk |
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229 | |
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230 | push r0 |
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231 | pushf r0 |
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232 | push r1 |
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233 | pushf r1 |
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234 | push r2 |
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235 | pushf r2 |
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236 | push r3 |
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237 | pushf r3 |
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238 | ; no push r4 because other part of register is in basic context |
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239 | push r4 |
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240 | pushf r4 |
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241 | ; no push r5 because other part of register is in basic context |
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242 | push r5 |
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243 | pushf r5 |
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244 | push r6 |
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245 | pushf r6 |
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246 | ; no pushf r6 because other part of register is in basic context |
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247 | push r7 |
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248 | pushf r7 |
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249 | ; no pushf r7 because other part of register is in basic context |
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250 | .if .TMS320C40 |
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251 | push r8 |
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252 | ; no pushf r8 because other part of register is in basic context |
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253 | push r9 |
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254 | pushf r9 |
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255 | push r10 |
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256 | pushf r10 |
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257 | push r11 |
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258 | pushf r11 |
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259 | .endif |
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260 | |
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261 | ldi sp,r2 |
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262 | call SYM(__ISR_Handler) |
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263 | |
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264 | .if .TMS320C40 |
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265 | popf r11 |
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266 | pop r11 |
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267 | popf r10 |
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268 | pop r10 |
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269 | popf r9 |
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270 | pop r9 |
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271 | ; no popf r8 because other part of register is in basic context |
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272 | pop r8 |
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273 | .endif |
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274 | ; no popf r7 because other part of register is in basic context |
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275 | popf r7 |
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276 | pop r7 |
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277 | ; no popf r6 because other part of register is in basic context |
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278 | popf r6 |
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279 | pop r6 |
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280 | ; no popf r5 because other part of register is in basic context |
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281 | popf r5 |
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282 | pop r5 |
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283 | ; no pop r4 because other part of register is in basic context |
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284 | popf r4 |
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285 | pop r4 |
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286 | popf r3 |
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287 | pop r3 |
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288 | popf r2 |
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289 | pop r2 |
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290 | popf r1 |
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291 | pop r1 |
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292 | popf r0 |
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293 | pop r0 |
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294 | |
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295 | pop bk |
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296 | pop rc |
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297 | pop re |
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298 | pop rs |
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299 | pop ir1 |
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300 | pop ir0 |
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301 | pop dp |
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302 | pop ar1 |
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303 | pop ar0 |
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304 | pop ar2 ; because the vector numbers goes here |
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305 | pop st |
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306 | reti |
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307 | |
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308 | /* |
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309 | * Prologues so we can know the vector number. Generated by this script: |
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310 | * |
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311 | * i=0 |
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312 | * while test $i -lt 64 |
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313 | * do |
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314 | * |
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315 | * printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i |
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316 | * printf "SYM(rtems_irq_prologue_%X):\n" $i |
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317 | * printf "\tpush\tst\n" |
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318 | * printf "\tpush\tar2\n" |
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319 | * printf "\tldi\t0x%x,ar2\n" $i |
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320 | * printf "\tbr\tSYM(_ISR_Handler_save_registers)\n" |
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321 | * printf "\n" |
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322 | * i=`expr $i + 1` |
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323 | * |
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324 | * done |
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325 | */ |
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326 | |
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327 | .global SYM(rtems_irq_prologue_0) |
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328 | SYM(rtems_irq_prologue_0): |
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329 | push st |
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330 | push ar2 |
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331 | ldi 0x0,ar2 |
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332 | br SYM(_ISR_Handler_save_registers) |
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333 | |
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334 | .global SYM(rtems_irq_prologue_1) |
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335 | SYM(rtems_irq_prologue_1): |
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336 | push st |
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337 | push ar2 |
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338 | ldi 0x1,ar2 |
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339 | br SYM(_ISR_Handler_save_registers) |
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340 | |
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341 | .global SYM(rtems_irq_prologue_2) |
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342 | SYM(rtems_irq_prologue_2): |
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343 | push st |
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344 | push ar2 |
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345 | ldi 0x2,ar2 |
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346 | br SYM(_ISR_Handler_save_registers) |
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347 | |
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348 | .global SYM(rtems_irq_prologue_3) |
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349 | SYM(rtems_irq_prologue_3): |
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350 | push st |
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351 | push ar2 |
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352 | ldi 0x3,ar2 |
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353 | br SYM(_ISR_Handler_save_registers) |
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354 | |
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355 | .global SYM(rtems_irq_prologue_4) |
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356 | SYM(rtems_irq_prologue_4): |
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357 | push st |
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358 | push ar2 |
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359 | ldi 0x4,ar2 |
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360 | br SYM(_ISR_Handler_save_registers) |
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361 | |
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362 | .global SYM(rtems_irq_prologue_5) |
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363 | SYM(rtems_irq_prologue_5): |
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364 | push st |
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365 | push ar2 |
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366 | ldi 0x5,ar2 |
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367 | br SYM(_ISR_Handler_save_registers) |
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368 | |
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369 | .global SYM(rtems_irq_prologue_6) |
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370 | SYM(rtems_irq_prologue_6): |
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371 | push st |
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372 | push ar2 |
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373 | ldi 0x6,ar2 |
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374 | br SYM(_ISR_Handler_save_registers) |
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375 | |
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376 | .global SYM(rtems_irq_prologue_7) |
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377 | SYM(rtems_irq_prologue_7): |
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378 | push st |
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379 | push ar2 |
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380 | ldi 0x7,ar2 |
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381 | br SYM(_ISR_Handler_save_registers) |
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382 | |
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383 | .global SYM(rtems_irq_prologue_8) |
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384 | SYM(rtems_irq_prologue_8): |
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385 | push st |
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386 | push ar2 |
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387 | ldi 0x8,ar2 |
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388 | br SYM(_ISR_Handler_save_registers) |
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389 | |
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390 | .global SYM(rtems_irq_prologue_9) |
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391 | SYM(rtems_irq_prologue_9): |
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392 | push st |
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393 | push ar2 |
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394 | ldi 0x9,ar2 |
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395 | br SYM(_ISR_Handler_save_registers) |
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396 | |
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397 | .global SYM(rtems_irq_prologue_A) |
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398 | SYM(rtems_irq_prologue_A): |
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399 | push st |
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400 | push ar2 |
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401 | ldi 0xa,ar2 |
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402 | br SYM(_ISR_Handler_save_registers) |
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403 | |
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404 | .global SYM(rtems_irq_prologue_B) |
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405 | SYM(rtems_irq_prologue_B): |
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406 | push st |
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407 | push ar2 |
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408 | ldi 0xb,ar2 |
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409 | br SYM(_ISR_Handler_save_registers) |
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410 | |
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411 | .global SYM(rtems_irq_prologue_C) |
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412 | SYM(rtems_irq_prologue_C): |
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413 | push st |
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414 | push ar2 |
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415 | ldi 0xc,ar2 |
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416 | br SYM(_ISR_Handler_save_registers) |
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417 | |
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418 | .global SYM(rtems_irq_prologue_D) |
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419 | SYM(rtems_irq_prologue_D): |
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420 | push st |
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421 | push ar2 |
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422 | ldi 0xd,ar2 |
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423 | br SYM(_ISR_Handler_save_registers) |
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424 | |
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425 | .global SYM(rtems_irq_prologue_E) |
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426 | SYM(rtems_irq_prologue_E): |
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427 | push st |
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428 | push ar2 |
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429 | ldi 0xe,ar2 |
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430 | br SYM(_ISR_Handler_save_registers) |
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431 | |
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432 | .global SYM(rtems_irq_prologue_F) |
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433 | SYM(rtems_irq_prologue_F): |
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434 | push st |
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435 | push ar2 |
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436 | ldi 0xf,ar2 |
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437 | br SYM(_ISR_Handler_save_registers) |
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438 | |
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439 | .global SYM(rtems_irq_prologue_10) |
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440 | SYM(rtems_irq_prologue_10): |
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441 | push st |
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442 | push ar2 |
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443 | ldi 0x10,ar2 |
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444 | br SYM(_ISR_Handler_save_registers) |
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445 | |
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446 | .global SYM(rtems_irq_prologue_11) |
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447 | SYM(rtems_irq_prologue_11): |
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448 | push st |
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449 | push ar2 |
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450 | ldi 0x11,ar2 |
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451 | br SYM(_ISR_Handler_save_registers) |
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452 | |
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453 | .global SYM(rtems_irq_prologue_12) |
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454 | SYM(rtems_irq_prologue_12): |
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455 | push st |
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456 | push ar2 |
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457 | ldi 0x12,ar2 |
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458 | br SYM(_ISR_Handler_save_registers) |
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459 | |
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460 | .global SYM(rtems_irq_prologue_13) |
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461 | SYM(rtems_irq_prologue_13): |
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462 | push st |
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463 | push ar2 |
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464 | ldi 0x13,ar2 |
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465 | br SYM(_ISR_Handler_save_registers) |
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466 | |
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467 | .global SYM(rtems_irq_prologue_14) |
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468 | SYM(rtems_irq_prologue_14): |
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469 | push st |
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470 | push ar2 |
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471 | ldi 0x14,ar2 |
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472 | br SYM(_ISR_Handler_save_registers) |
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473 | |
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474 | .global SYM(rtems_irq_prologue_15) |
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475 | SYM(rtems_irq_prologue_15): |
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476 | push st |
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477 | push ar2 |
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478 | ldi 0x15,ar2 |
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479 | br SYM(_ISR_Handler_save_registers) |
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480 | |
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481 | .global SYM(rtems_irq_prologue_16) |
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482 | SYM(rtems_irq_prologue_16): |
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483 | push st |
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484 | push ar2 |
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485 | ldi 0x16,ar2 |
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486 | br SYM(_ISR_Handler_save_registers) |
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487 | |
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488 | .global SYM(rtems_irq_prologue_17) |
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489 | SYM(rtems_irq_prologue_17): |
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490 | push st |
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491 | push ar2 |
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492 | ldi 0x17,ar2 |
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493 | br SYM(_ISR_Handler_save_registers) |
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494 | |
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495 | .global SYM(rtems_irq_prologue_18) |
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496 | SYM(rtems_irq_prologue_18): |
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497 | push st |
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498 | push ar2 |
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499 | ldi 0x18,ar2 |
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500 | br SYM(_ISR_Handler_save_registers) |
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501 | |
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502 | .global SYM(rtems_irq_prologue_19) |
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503 | SYM(rtems_irq_prologue_19): |
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504 | push st |
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505 | push ar2 |
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506 | ldi 0x19,ar2 |
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507 | br SYM(_ISR_Handler_save_registers) |
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508 | |
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509 | .global SYM(rtems_irq_prologue_1A) |
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510 | SYM(rtems_irq_prologue_1A): |
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511 | push st |
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512 | push ar2 |
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513 | ldi 0x1a,ar2 |
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514 | br SYM(_ISR_Handler_save_registers) |
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515 | |
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516 | .global SYM(rtems_irq_prologue_1B) |
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517 | SYM(rtems_irq_prologue_1B): |
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518 | push st |
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519 | push ar2 |
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520 | ldi 0x1b,ar2 |
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521 | br SYM(_ISR_Handler_save_registers) |
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522 | |
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523 | .global SYM(rtems_irq_prologue_1C) |
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524 | SYM(rtems_irq_prologue_1C): |
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525 | push st |
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526 | push ar2 |
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527 | ldi 0x1c,ar2 |
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528 | br SYM(_ISR_Handler_save_registers) |
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529 | |
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530 | .global SYM(rtems_irq_prologue_1D) |
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531 | SYM(rtems_irq_prologue_1D): |
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532 | push st |
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533 | push ar2 |
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534 | ldi 0x1d,ar2 |
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535 | br SYM(_ISR_Handler_save_registers) |
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536 | |
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537 | .global SYM(rtems_irq_prologue_1E) |
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538 | SYM(rtems_irq_prologue_1E): |
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539 | push st |
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540 | push ar2 |
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541 | ldi 0x1e,ar2 |
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542 | br SYM(_ISR_Handler_save_registers) |
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543 | |
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544 | .global SYM(rtems_irq_prologue_1F) |
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545 | SYM(rtems_irq_prologue_1F): |
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546 | push st |
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547 | push ar2 |
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548 | ldi 0x1f,ar2 |
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549 | br SYM(_ISR_Handler_save_registers) |
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550 | |
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551 | .global SYM(rtems_irq_prologue_20) |
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552 | SYM(rtems_irq_prologue_20): |
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553 | push st |
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554 | push ar2 |
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555 | ldi 0x20,ar2 |
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556 | br SYM(_ISR_Handler_save_registers) |
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557 | |
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558 | .global SYM(rtems_irq_prologue_21) |
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559 | SYM(rtems_irq_prologue_21): |
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560 | push st |
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561 | push ar2 |
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562 | ldi 0x21,ar2 |
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563 | br SYM(_ISR_Handler_save_registers) |
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564 | |
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565 | .global SYM(rtems_irq_prologue_22) |
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566 | SYM(rtems_irq_prologue_22): |
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567 | push st |
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568 | push ar2 |
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569 | ldi 0x22,ar2 |
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570 | br SYM(_ISR_Handler_save_registers) |
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571 | |
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572 | .global SYM(rtems_irq_prologue_23) |
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573 | SYM(rtems_irq_prologue_23): |
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574 | push st |
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575 | push ar2 |
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576 | ldi 0x23,ar2 |
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577 | br SYM(_ISR_Handler_save_registers) |
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578 | |
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579 | .global SYM(rtems_irq_prologue_24) |
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580 | SYM(rtems_irq_prologue_24): |
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581 | push st |
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582 | push ar2 |
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583 | ldi 0x24,ar2 |
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584 | br SYM(_ISR_Handler_save_registers) |
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585 | |
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586 | .global SYM(rtems_irq_prologue_25) |
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587 | SYM(rtems_irq_prologue_25): |
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588 | push st |
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589 | push ar2 |
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590 | ldi 0x25,ar2 |
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591 | br SYM(_ISR_Handler_save_registers) |
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592 | |
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593 | .global SYM(rtems_irq_prologue_26) |
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594 | SYM(rtems_irq_prologue_26): |
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595 | push st |
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596 | push ar2 |
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597 | ldi 0x26,ar2 |
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598 | br SYM(_ISR_Handler_save_registers) |
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599 | |
---|
600 | .global SYM(rtems_irq_prologue_27) |
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601 | SYM(rtems_irq_prologue_27): |
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602 | push st |
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603 | push ar2 |
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604 | ldi 0x27,ar2 |
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605 | br SYM(_ISR_Handler_save_registers) |
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606 | |
---|
607 | .global SYM(rtems_irq_prologue_28) |
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608 | SYM(rtems_irq_prologue_28): |
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609 | push st |
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610 | push ar2 |
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611 | ldi 0x28,ar2 |
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612 | br SYM(_ISR_Handler_save_registers) |
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613 | |
---|
614 | .global SYM(rtems_irq_prologue_29) |
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615 | SYM(rtems_irq_prologue_29): |
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616 | push st |
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617 | push ar2 |
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618 | ldi 0x29,ar2 |
---|
619 | br SYM(_ISR_Handler_save_registers) |
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620 | |
---|
621 | .global SYM(rtems_irq_prologue_2A) |
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622 | SYM(rtems_irq_prologue_2A): |
---|
623 | push st |
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624 | push ar2 |
---|
625 | ldi 0x2a,ar2 |
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626 | br SYM(_ISR_Handler_save_registers) |
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627 | |
---|
628 | .global SYM(rtems_irq_prologue_2B) |
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629 | SYM(rtems_irq_prologue_2B): |
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630 | push st |
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631 | push ar2 |
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632 | ldi 0x2b,ar2 |
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633 | br SYM(_ISR_Handler_save_registers) |
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634 | |
---|
635 | .global SYM(rtems_irq_prologue_2C) |
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636 | SYM(rtems_irq_prologue_2C): |
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637 | push st |
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638 | push ar2 |
---|
639 | ldi 0x2c,ar2 |
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640 | br SYM(_ISR_Handler_save_registers) |
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641 | |
---|
642 | .global SYM(rtems_irq_prologue_2D) |
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643 | SYM(rtems_irq_prologue_2D): |
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644 | push st |
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645 | push ar2 |
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646 | ldi 0x2d,ar2 |
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647 | br SYM(_ISR_Handler_save_registers) |
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648 | |
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649 | .global SYM(rtems_irq_prologue_2E) |
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650 | SYM(rtems_irq_prologue_2E): |
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651 | push st |
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652 | push ar2 |
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653 | ldi 0x2e,ar2 |
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654 | br SYM(_ISR_Handler_save_registers) |
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655 | |
---|
656 | .global SYM(rtems_irq_prologue_2F) |
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657 | SYM(rtems_irq_prologue_2F): |
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658 | push st |
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659 | push ar2 |
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660 | ldi 0x2f,ar2 |
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661 | br SYM(_ISR_Handler_save_registers) |
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662 | |
---|
663 | .global SYM(rtems_irq_prologue_30) |
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664 | SYM(rtems_irq_prologue_30): |
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665 | push st |
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666 | push ar2 |
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667 | ldi 0x30,ar2 |
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668 | br SYM(_ISR_Handler_save_registers) |
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669 | |
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670 | .global SYM(rtems_irq_prologue_31) |
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671 | SYM(rtems_irq_prologue_31): |
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672 | push st |
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673 | push ar2 |
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674 | ldi 0x31,ar2 |
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675 | br SYM(_ISR_Handler_save_registers) |
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676 | |
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677 | .global SYM(rtems_irq_prologue_32) |
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678 | SYM(rtems_irq_prologue_32): |
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679 | push st |
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680 | push ar2 |
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681 | ldi 0x32,ar2 |
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682 | br SYM(_ISR_Handler_save_registers) |
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683 | |
---|
684 | .global SYM(rtems_irq_prologue_33) |
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685 | SYM(rtems_irq_prologue_33): |
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686 | push st |
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687 | push ar2 |
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688 | ldi 0x33,ar2 |
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689 | br SYM(_ISR_Handler_save_registers) |
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690 | |
---|
691 | .global SYM(rtems_irq_prologue_34) |
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692 | SYM(rtems_irq_prologue_34): |
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693 | push st |
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694 | push ar2 |
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695 | ldi 0x34,ar2 |
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696 | br SYM(_ISR_Handler_save_registers) |
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697 | |
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698 | .global SYM(rtems_irq_prologue_35) |
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699 | SYM(rtems_irq_prologue_35): |
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700 | push st |
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701 | push ar2 |
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702 | ldi 0x35,ar2 |
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703 | br SYM(_ISR_Handler_save_registers) |
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704 | |
---|
705 | .global SYM(rtems_irq_prologue_36) |
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706 | SYM(rtems_irq_prologue_36): |
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707 | push st |
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708 | push ar2 |
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709 | ldi 0x36,ar2 |
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710 | br SYM(_ISR_Handler_save_registers) |
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711 | |
---|
712 | .global SYM(rtems_irq_prologue_37) |
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713 | SYM(rtems_irq_prologue_37): |
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714 | push st |
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715 | push ar2 |
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716 | ldi 0x37,ar2 |
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717 | br SYM(_ISR_Handler_save_registers) |
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718 | |
---|
719 | .global SYM(rtems_irq_prologue_38) |
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720 | SYM(rtems_irq_prologue_38): |
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721 | push st |
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722 | push ar2 |
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723 | ldi 0x38,ar2 |
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724 | br SYM(_ISR_Handler_save_registers) |
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725 | |
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726 | .global SYM(rtems_irq_prologue_39) |
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727 | SYM(rtems_irq_prologue_39): |
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728 | push st |
---|
729 | push ar2 |
---|
730 | ldi 0x39,ar2 |
---|
731 | br SYM(_ISR_Handler_save_registers) |
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732 | |
---|
733 | .global SYM(rtems_irq_prologue_3A) |
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734 | SYM(rtems_irq_prologue_3A): |
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735 | push st |
---|
736 | push ar2 |
---|
737 | ldi 0x3a,ar2 |
---|
738 | br SYM(_ISR_Handler_save_registers) |
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739 | |
---|
740 | .global SYM(rtems_irq_prologue_3B) |
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741 | SYM(rtems_irq_prologue_3B): |
---|
742 | push st |
---|
743 | push ar2 |
---|
744 | ldi 0x3b,ar2 |
---|
745 | br SYM(_ISR_Handler_save_registers) |
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746 | |
---|
747 | .global SYM(rtems_irq_prologue_3C) |
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748 | SYM(rtems_irq_prologue_3C): |
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749 | push st |
---|
750 | push ar2 |
---|
751 | ldi 0x3c,ar2 |
---|
752 | br SYM(_ISR_Handler_save_registers) |
---|
753 | |
---|
754 | .global SYM(rtems_irq_prologue_3D) |
---|
755 | SYM(rtems_irq_prologue_3D): |
---|
756 | push st |
---|
757 | push ar2 |
---|
758 | ldi 0x3d,ar2 |
---|
759 | br SYM(_ISR_Handler_save_registers) |
---|
760 | |
---|
761 | .global SYM(rtems_irq_prologue_3E) |
---|
762 | SYM(rtems_irq_prologue_3E): |
---|
763 | push st |
---|
764 | push ar2 |
---|
765 | ldi 0x3e,ar2 |
---|
766 | br SYM(_ISR_Handler_save_registers) |
---|
767 | |
---|
768 | .global SYM(rtems_irq_prologue_3F) |
---|
769 | SYM(rtems_irq_prologue_3F): |
---|
770 | push st |
---|
771 | push ar2 |
---|
772 | ldi 0x3f,ar2 |
---|
773 | br SYM(_ISR_Handler_save_registers) |
---|