source: rtems/cpukit/score/cpu/c4x/cpu.c @ f26145b

4.104.114.84.95
Last change on this file since f26145b was 16ce0e70, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 30, 2004 at 11:45:56 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • c4xio.h, cpu.c, irq.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  C4x CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#include <rtems/system.h>
16#include <rtems/score/isr.h>
17#include <rtems/score/wkspace.h>
18
19
20/*  _CPU_Initialize
21 *
22 *  This routine performs processor dependent initialization.
23 *
24 *  INPUT PARAMETERS:
25 *    cpu_table       - CPU table to initialize
26 *    thread_dispatch - address of disptaching routine
27 *
28 *  C4x Specific Information:
29 *
30 */
31
32void _CPU_Initialize(
33  rtems_cpu_table  *cpu_table,
34  void      (*thread_dispatch)      /* ignored on this CPU */
35)
36{
37#if 0
38  /*
39   *  The thread_dispatch argument is the address of the entry point
40   *  for the routine called at the end of an ISR once it has been
41   *  decided a context switch is necessary.  On some compilation
42   *  systems it is difficult to call a high-level language routine
43   *  from assembly.  This allows us to trick these systems.
44   *
45   *  If you encounter this problem save the entry point in a CPU
46   *  dependent variable.
47   */
48
49  _CPU_Thread_dispatch_pointer = thread_dispatch;
50#endif
51
52#if (CPU_HARDWARE_FP == TRUE)
53  /*
54   *  If there is not an easy way to initialize the FP context
55   *  during Context_Initialize, then it is usually easier to
56   *  save an "uninitialized" FP context here and copy it to
57   *  the task's during Context_Initialize.
58   */
59
60  /* FP context initialization support goes here */
61#endif
62
63  _CPU_Table = *cpu_table;
64}
65
66/*PAGE
67 *
68 *  _CPU_ISR_install_raw_handler
69 *
70 *  C4x Specific Information:
71 *
72 */
73 
74void _CPU_ISR_install_raw_handler(
75  uint32_t    vector,
76  proc_ptr    new_handler,
77  proc_ptr   *old_handler
78)
79{
80  void       **ittp;
81
82  /*
83   *  This is where we install the interrupt handler into the "raw" interrupt
84   *  table used by the CPU to dispatch interrupt handlers.
85   */
86   
87  ittp = c4x_get_ittp();
88  *old_handler = ittp[ vector ];
89  ittp[ vector ] = new_handler;
90}
91
92/*XXX */
93
94#define C4X_CACHE       1
95#define C4X_BASE_ST     (C4X_CACHE==1) ? 0x4800 : 0x4000
96
97void _CPU_Context_Initialize(
98  Context_Control       *_the_context,
99  void                  *_stack_base,
100  uint32_t              _size,
101  uint32_t              _isr,
102  void  (*_entry_point)(void),
103  int                   _is_fp
104)
105{
106  unsigned int *_stack;
107  _stack = (unsigned int *)_stack_base;
108
109  *_stack = (unsigned int) _entry_point;
110  _the_context->sp = (unsigned int) _stack;
111  _the_context->st = C4X_BASE_ST;
112  if ( _isr == 0 )
113    _the_context->st |= C4X_ST_GIE;
114}
115
116/*PAGE
117 *
118 *  _CPU_ISR_install_vector
119 *
120 *  This kernel routine installs the RTEMS handler for the
121 *  specified vector.
122 *
123 *  Input parameters:
124 *    vector      - interrupt vector number
125 *    old_handler - former ISR for this vector number
126 *    new_handler - replacement ISR for this vector number
127 *
128 *  Output parameters:  NONE
129 *
130 *
131 *  C4x Specific Information:
132 *
133 */
134
135void _CPU_ISR_install_vector(
136  uint32_t    vector,
137  proc_ptr    new_handler,
138  proc_ptr   *old_handler
139)
140{
141  proc_ptr ignored;
142  extern void rtems_irq_prologue_0(void);
143  extern void rtems_irq_prologue_1(void);
144  void *entry;
145
146  *old_handler = _ISR_Vector_table[ vector ];
147
148  /*
149   *  If the interrupt vector table is a table of pointer to isr entry
150   *  points, then we need to install the appropriate RTEMS interrupt
151   *  handler for this vector number.
152   */
153
154  entry = (void *)rtems_irq_prologue_0 +
155    ((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector);
156  _CPU_ISR_install_raw_handler( vector, entry, &ignored );
157
158  /*
159   *  We put the actual user ISR address in '_ISR_vector_table'.  This will
160   *  be used by the _ISR_Handler so the user gets control.
161   */
162
163   _ISR_Vector_table[ vector ] = new_handler;
164}
165
166/*PAGE
167 *
168 *  _CPU_Thread_Idle_body
169 *
170 *  NOTES:
171 *
172 *  1. This is the same as the regular CPU independent algorithm.
173 *
174 *  2. If you implement this using a "halt", "idle", or "shutdown"
175 *     instruction, then don't forget to put it in an infinite loop.
176 *
177 *  3. Be warned. Some processors with onboard DMA have been known
178 *     to stop the DMA if the CPU were put in IDLE mode.  This might
179 *     also be a problem with other on-chip peripherals.  So use this
180 *     hook with caution.
181 *
182 *  C4x Specific Information:
183 *
184 *
185 */
186
187#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1)
188void _CPU_Thread_Idle_body( void )
189{
190
191  for( ; ; ) {
192    __asm__( "idle" );
193    __asm__( "nop" );
194    __asm__( "nop" );
195    __asm__( "nop" );
196    /* insert your "halt" instruction here */ ;
197  }
198}
199#endif
Note: See TracBrowser for help on using the repository browser.