source: rtems/cpukit/score/cpu/c4x/cpu.c @ 60f016f

4.104.114.84.95
Last change on this file since 60f016f was 60f016f, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2007 at 8:57:34 PM

2007-05-22 Joel Sherrill <joel.sherrill@…>

  • score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  C4x CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#include <rtems/system.h>
16#include <rtems/score/isr.h>
17#include <rtems/score/wkspace.h>
18
19
20/*  _CPU_Initialize
21 *
22 *  This routine performs processor dependent initialization.
23 *
24 *  INPUT PARAMETERS:
25 *    cpu_table       - CPU table to initialize
26 *    thread_dispatch - address of disptaching routine
27 *
28 *  C4x Specific Information:
29 *
30 */
31
32void _CPU_Initialize(
33  rtems_cpu_table  *cpu_table,
34  void      (*thread_dispatch)      /* ignored on this CPU */
35)
36{
37#if 0
38  /*
39   *  The thread_dispatch argument is the address of the entry point
40   *  for the routine called at the end of an ISR once it has been
41   *  decided a context switch is necessary.  On some compilation
42   *  systems it is difficult to call a high-level language routine
43   *  from assembly.  This allows us to trick these systems.
44   *
45   *  If you encounter this problem save the entry point in a CPU
46   *  dependent variable.
47   */
48
49  _CPU_Thread_dispatch_pointer = thread_dispatch;
50#endif
51
52#if (CPU_HARDWARE_FP == TRUE)
53  /*
54   *  If there is not an easy way to initialize the FP context
55   *  during Context_Initialize, then it is usually easier to
56   *  save an "uninitialized" FP context here and copy it to
57   *  the task's during Context_Initialize.
58   */
59
60  /* FP context initialization support goes here */
61#endif
62}
63
64/*PAGE
65 *
66 *  _CPU_ISR_install_raw_handler
67 *
68 *  C4x Specific Information:
69 *
70 */
71 
72void _CPU_ISR_install_raw_handler(
73  uint32_t    vector,
74  proc_ptr    new_handler,
75  proc_ptr   *old_handler
76)
77{
78  void       **ittp;
79
80  /*
81   *  This is where we install the interrupt handler into the "raw" interrupt
82   *  table used by the CPU to dispatch interrupt handlers.
83   */
84   
85  ittp = c4x_get_ittp();
86  *old_handler = ittp[ vector ];
87  ittp[ vector ] = new_handler;
88}
89
90/*XXX */
91
92#define C4X_CACHE       1
93#define C4X_BASE_ST     (C4X_CACHE==1) ? 0x4800 : 0x4000
94
95void _CPU_Context_Initialize(
96  Context_Control       *_the_context,
97  void                  *_stack_base,
98  uint32_t              _size,
99  uint32_t              _isr,
100  void  (*_entry_point)(void),
101  int                   _is_fp
102)
103{
104  unsigned int *_stack;
105  _stack = (unsigned int *)_stack_base;
106
107  *_stack = (unsigned int) _entry_point;
108  _the_context->sp = (unsigned int) _stack;
109  _the_context->st = C4X_BASE_ST;
110  if ( _isr == 0 )
111    _the_context->st |= C4X_ST_GIE;
112}
113
114/*PAGE
115 *
116 *  _CPU_ISR_install_vector
117 *
118 *  This kernel routine installs the RTEMS handler for the
119 *  specified vector.
120 *
121 *  Input parameters:
122 *    vector      - interrupt vector number
123 *    old_handler - former ISR for this vector number
124 *    new_handler - replacement ISR for this vector number
125 *
126 *  Output parameters:  NONE
127 *
128 *
129 *  C4x Specific Information:
130 *
131 */
132
133void _CPU_ISR_install_vector(
134  uint32_t    vector,
135  proc_ptr    new_handler,
136  proc_ptr   *old_handler
137)
138{
139  proc_ptr ignored;
140  extern void rtems_irq_prologue_0(void);
141  extern void rtems_irq_prologue_1(void);
142  void *entry;
143
144  *old_handler = _ISR_Vector_table[ vector ];
145
146  /*
147   *  If the interrupt vector table is a table of pointer to isr entry
148   *  points, then we need to install the appropriate RTEMS interrupt
149   *  handler for this vector number.
150   */
151
152  entry = (void *)rtems_irq_prologue_0 +
153    ((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector);
154  _CPU_ISR_install_raw_handler( vector, entry, &ignored );
155
156  /*
157   *  We put the actual user ISR address in '_ISR_vector_table'.  This will
158   *  be used by the _ISR_Handler so the user gets control.
159   */
160
161   _ISR_Vector_table[ vector ] = new_handler;
162}
163
164/*PAGE
165 *
166 *  _CPU_Thread_Idle_body
167 *
168 *  NOTES:
169 *
170 *  1. This is the same as the regular CPU independent algorithm.
171 *
172 *  2. If you implement this using a "halt", "idle", or "shutdown"
173 *     instruction, then don't forget to put it in an infinite loop.
174 *
175 *  3. Be warned. Some processors with onboard DMA have been known
176 *     to stop the DMA if the CPU were put in IDLE mode.  This might
177 *     also be a problem with other on-chip peripherals.  So use this
178 *     hook with caution.
179 *
180 *  C4x Specific Information:
181 *
182 *
183 */
184
185#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1)
186void _CPU_Thread_Idle_body( void )
187{
188
189  for( ; ; ) {
190    __asm__( "idle" );
191    __asm__( "nop" );
192    __asm__( "nop" );
193    __asm__( "nop" );
194    /* insert your "halt" instruction here */ ;
195  }
196}
197#endif
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