source: rtems/cpukit/score/cpu/c4x/cpu.c @ 5632f8d

4.104.11
Last change on this file since 5632f8d was 5632f8d, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:02:21 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • cpu.c, cpu_asm.S, irq.c: Add include of config.h
  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 *  C4x CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#ifdef HAVE_CONFIG_H
16#include "config.h"
17#endif
18
19#include <rtems/system.h>
20#include <rtems/score/isr.h>
21#include <rtems/score/wkspace.h>
22
23/*  _CPU_Initialize
24 *
25 *  This routine performs processor dependent initialization.
26 *
27 *  INPUT PARAMETERS: NONE
28 *
29 *  C4x Specific Information:
30 *
31 */
32
33void _CPU_Initialize(void)
34{
35#if (CPU_HARDWARE_FP == TRUE)
36  /*
37   *  If there is not an easy way to initialize the FP context
38   *  during Context_Initialize, then it is usually easier to
39   *  save an "uninitialized" FP context here and copy it to
40   *  the task's during Context_Initialize.
41   */
42
43  /* FP context initialization support goes here */
44#endif
45}
46
47/*PAGE
48 *
49 *  _CPU_ISR_install_raw_handler
50 *
51 *  C4x Specific Information:
52 *
53 */
54
55void _CPU_ISR_install_raw_handler(
56  uint32_t    vector,
57  proc_ptr    new_handler,
58  proc_ptr   *old_handler
59)
60{
61  void       **ittp;
62
63  /*
64   *  This is where we install the interrupt handler into the "raw" interrupt
65   *  table used by the CPU to dispatch interrupt handlers.
66   */
67
68  ittp = c4x_get_ittp();
69  *old_handler = ittp[ vector ];
70  ittp[ vector ] = new_handler;
71}
72
73/*XXX */
74
75#define C4X_CACHE       1
76#define C4X_BASE_ST     (C4X_CACHE==1) ? 0x4800 : 0x4000
77
78void _CPU_Context_Initialize(
79  Context_Control       *_the_context,
80  void                  *_stack_base,
81  uint32_t              _size,
82  uint32_t              _isr,
83  void  (*_entry_point)(void),
84  int                   _is_fp
85)
86{
87  unsigned int *_stack;
88  _stack = (unsigned int *)_stack_base;
89
90  *_stack = (unsigned int) _entry_point;
91  _the_context->sp = (unsigned int) _stack;
92  _the_context->st = C4X_BASE_ST;
93  if ( _isr == 0 )
94    _the_context->st |= C4X_ST_GIE;
95}
96
97/*PAGE
98 *
99 *  _CPU_ISR_install_vector
100 *
101 *  This kernel routine installs the RTEMS handler for the
102 *  specified vector.
103 *
104 *  Input parameters:
105 *    vector      - interrupt vector number
106 *    old_handler - former ISR for this vector number
107 *    new_handler - replacement ISR for this vector number
108 *
109 *  Output parameters:  NONE
110 *
111 *
112 *  C4x Specific Information:
113 *
114 */
115
116void _CPU_ISR_install_vector(
117  uint32_t    vector,
118  proc_ptr    new_handler,
119  proc_ptr   *old_handler
120)
121{
122  proc_ptr ignored;
123  extern void rtems_irq_prologue_0(void);
124  extern void rtems_irq_prologue_1(void);
125  void *entry;
126
127  *old_handler = _ISR_Vector_table[ vector ];
128
129  /*
130   *  If the interrupt vector table is a table of pointer to isr entry
131   *  points, then we need to install the appropriate RTEMS interrupt
132   *  handler for this vector number.
133   */
134
135  entry = (void *)rtems_irq_prologue_0 +
136    ((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector);
137  _CPU_ISR_install_raw_handler( vector, entry, &ignored );
138
139  /*
140   *  We put the actual user ISR address in '_ISR_vector_table'.  This will
141   *  be used by the _ISR_Handler so the user gets control.
142   */
143
144   _ISR_Vector_table[ vector ] = new_handler;
145}
146
147/*PAGE
148 *
149 *  _CPU_Thread_Idle_body
150 *
151 *  NOTES:
152 *
153 *  1. This is the same as the regular CPU independent algorithm.
154 *
155 *  2. If you implement this using a "halt", "idle", or "shutdown"
156 *     instruction, then don't forget to put it in an infinite loop.
157 *
158 *  3. Be warned. Some processors with onboard DMA have been known
159 *     to stop the DMA if the CPU were put in IDLE mode.  This might
160 *     also be a problem with other on-chip peripherals.  So use this
161 *     hook with caution.
162 *
163 *  C4x Specific Information:
164 *
165 *
166 */
167
168#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1)
169void *_CPU_Thread_Idle_body( uintptr_t ignored )
170{
171
172  for( ; ; ) {
173    __asm__( "idle" );
174    __asm__( "nop" );
175    __asm__( "nop" );
176    __asm__( "nop" );
177    /* insert your "halt" instruction here */ ;
178  }
179}
180#endif
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