source: rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 40.7 KB
Line 
1/**
2 * @file
3 *
4 * @brief Blackfin CPU Department Source
5 *
6 * This include file contains information pertaining to the Blackfin
7 * processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2006.
12 *  On-Line Applications Research Corporation (OAR).
13 *  adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
14 *                     and Antonio Giovanini <antonio@atos.com.br>
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *  http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef _RTEMS_SCORE_CPU_H
22#define _RTEMS_SCORE_CPU_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#include <rtems/score/types.h>
29#include <rtems/score/bfin.h>
30
31/* conditional compilation parameters */
32
33/**
34 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
35 *
36 * If TRUE, then they are inlined.
37 * If FALSE, then a subroutine call is made.
38 *
39 * This conditional is an example of the classic trade-off of size
40 * versus speed.  Inlining the call (TRUE) typically increases the
41 * size of RTEMS while speeding up the enabling of dispatching.
42 *
43 * @note In general, the @ref _Thread_Dispatch_disable_level will
44 * only be 0 or 1 unless you are in an interrupt handler and that
45 * interrupt handler invokes the executive.]  When not inlined
46 * something calls @ref _Thread_Enable_dispatch which in turns calls
47 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
48 * one subroutine call is avoided entirely.
49 *
50 * Port Specific Information:
51 *
52 * XXX document implementation including references if appropriate
53 */
54#define CPU_INLINE_ENABLE_DISPATCH       FALSE
55
56/**
57 * Should the body of the search loops in _Thread_queue_Enqueue_priority
58 * be unrolled one time?  In unrolled each iteration of the loop examines
59 * two "nodes" on the chain being searched.  Otherwise, only one node
60 * is examined per iteration.
61 *
62 * If TRUE, then the loops are unrolled.
63 * If FALSE, then the loops are not unrolled.
64 *
65 * The primary factor in making this decision is the cost of disabling
66 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
67 * body of the loop.  On some CPUs, the flash is more expensive than
68 * one iteration of the loop body.  In this case, it might be desirable
69 * to unroll the loop.  It is important to note that on some CPUs, this
70 * code is the longest interrupt disable period in RTEMS.  So it is
71 * necessary to strike a balance when setting this parameter.
72 *
73 * Port Specific Information:
74 *
75 * XXX document implementation including references if appropriate
76 */
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/**
80 * Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
83 * If FALSE, nothing is done.
84 *
85 * If the CPU supports a dedicated interrupt stack in hardware,
86 * then it is generally the responsibility of the BSP to allocate it
87 * and set it up.
88 *
89 * If the CPU does not support a dedicated interrupt stack, then
90 * the porter has two options: (1) execute interrupts on the
91 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 * interrupt stack.
93 *
94 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 * possible that both are FALSE for a particular CPU.  Although it
99 * is unclear what that would imply about the interrupt processing
100 * procedure on that CPU.
101 *
102 * Port Specific Information:
103 *
104 * XXX document implementation including references if appropriate
105 */
106#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
107
108/*
109 *  Does the CPU follow the simple vectored interrupt model?
110 *
111 *  If TRUE, then RTEMS allocates the vector table it internally manages.
112 *  If FALSE, then the BSP is assumed to allocate and manage the vector
113 *  table
114 *
115 *  BFIN Specific Information:
116 *
117 *  XXX document implementation including references if appropriate
118 */
119#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
120
121/**
122 * Does this CPU have hardware support for a dedicated interrupt stack?
123 *
124 * If TRUE, then it must be installed during initialization.
125 * If FALSE, then no installation is performed.
126 *
127 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
128 *
129 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
130 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
131 * possible that both are FALSE for a particular CPU.  Although it
132 * is unclear what that would imply about the interrupt processing
133 * procedure on that CPU.
134 *
135 * Port Specific Information:
136 *
137 * XXX document implementation including references if appropriate
138 */
139#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
140
141/**
142 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
143 *
144 * If TRUE, then the memory is allocated during initialization.
145 * If FALSE, then the memory is allocated during initialization.
146 *
147 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
148 *
149 * Port Specific Information:
150 *
151 * XXX document implementation including references if appropriate
152 */
153#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
154
155/**
156 * Does the RTEMS invoke the user's ISR with the vector number and
157 * a pointer to the saved interrupt frame (1) or just the vector
158 * number (0)?
159 *
160 * Port Specific Information:
161 *
162 * XXX document implementation including references if appropriate
163 */
164#define CPU_ISR_PASSES_FRAME_POINTER 1
165
166/**
167 * @def CPU_HARDWARE_FP
168 *
169 * Does the CPU have hardware floating point?
170 *
171 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
172 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
173 *
174 * If there is a FP coprocessor such as the i387 or mc68881, then
175 * the answer is TRUE.
176 *
177 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
178 * It indicates whether or not this CPU model has FP support.  For
179 * example, it would be possible to have an i386_nofp CPU model
180 * which set this to false to indicate that you have an i386 without
181 * an i387 and wish to leave floating point support out of RTEMS.
182 */
183
184/**
185 * @def CPU_SOFTWARE_FP
186 *
187 * Does the CPU have no hardware floating point and GCC provides a
188 * software floating point implementation which must be context
189 * switched?
190 *
191 * This feature conditional is used to indicate whether or not there
192 * is software implemented floating point that must be context
193 * switched.  The determination of whether or not this applies
194 * is very tool specific and the state saved/restored is also
195 * compiler specific.
196 *
197 * Port Specific Information:
198 *
199 * XXX document implementation including references if appropriate
200 */
201#if ( BLACKFIN_CPU_HAS_FPU == 1 )
202#define CPU_HARDWARE_FP     TRUE
203#else
204#define CPU_HARDWARE_FP     FALSE
205#endif
206#define CPU_SOFTWARE_FP     FALSE
207
208/**
209 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
210 *
211 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
212 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
213 *
214 * So far, the only CPUs in which this option has been used are the
215 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
216 * gcc both implicitly used the floating point registers to perform
217 * integer multiplies.  Similarly, the PowerPC port of gcc has been
218 * seen to allocate floating point local variables and touch the FPU
219 * even when the flow through a subroutine (like vfprintf()) might
220 * not use floating point formats.
221 *
222 * If a function which you would not think utilize the FP unit DOES,
223 * then one can not easily predict which tasks will use the FP hardware.
224 * In this case, this option should be TRUE.
225 *
226 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
227 *
228 * Port Specific Information:
229 *
230 * XXX document implementation including references if appropriate
231 */
232#define CPU_ALL_TASKS_ARE_FP     FALSE
233
234/**
235 * Should the IDLE task have a floating point context?
236 *
237 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
238 * and it has a floating point context which is switched in and out.
239 * If FALSE, then the IDLE task does not have a floating point context.
240 *
241 * Setting this to TRUE negatively impacts the time required to preempt
242 * the IDLE task from an interrupt because the floating point context
243 * must be saved as part of the preemption.
244 *
245 * Port Specific Information:
246 *
247 * XXX document implementation including references if appropriate
248 */
249#define CPU_IDLE_TASK_IS_FP      FALSE
250
251/**
252 * Should the saving of the floating point registers be deferred
253 * until a context switch is made to another different floating point
254 * task?
255 *
256 * If TRUE, then the floating point context will not be stored until
257 * necessary.  It will remain in the floating point registers and not
258 * disturned until another floating point task is switched to.
259 *
260 * If FALSE, then the floating point context is saved when a floating
261 * point task is switched out and restored when the next floating point
262 * task is restored.  The state of the floating point registers between
263 * those two operations is not specified.
264 *
265 * If the floating point context does NOT have to be saved as part of
266 * interrupt dispatching, then it should be safe to set this to TRUE.
267 *
268 * Setting this flag to TRUE results in using a different algorithm
269 * for deciding when to save and restore the floating point context.
270 * The deferred FP switch algorithm minimizes the number of times
271 * the FP context is saved and restored.  The FP context is not saved
272 * until a context switch is made to another, different FP task.
273 * Thus in a system with only one FP task, the FP context will never
274 * be saved or restored.
275 *
276 * Port Specific Information:
277 *
278 * XXX document implementation including references if appropriate
279 */
280#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
281
282/**
283 * Does this port provide a CPU dependent IDLE task implementation?
284 *
285 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
286 * must be provided and is the default IDLE thread body instead of
287 * @ref _CPU_Thread_Idle_body.
288 *
289 * If FALSE, then use the generic IDLE thread body if the BSP does
290 * not provide one.
291 *
292 * This is intended to allow for supporting processors which have
293 * a low power or idle mode.  When the IDLE thread is executed, then
294 * the CPU can be powered down.
295 *
296 * The order of precedence for selecting the IDLE thread body is:
297 *
298 *   -#  BSP provided
299 *   -#  CPU dependent (if provided)
300 *   -#  generic (if no BSP and no CPU dependent)
301 *
302 * Port Specific Information:
303 *
304 * XXX document implementation including references if appropriate
305 */
306#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
307
308/**
309 * Does the stack grow up (toward higher addresses) or down
310 * (toward lower addresses)?
311 *
312 * If TRUE, then the grows upward.
313 * If FALSE, then the grows toward smaller addresses.
314 *
315 * Port Specific Information:
316 *
317 * XXX document implementation including references if appropriate
318 */
319#define CPU_STACK_GROWS_UP               FALSE
320
321/**
322 * The following is the variable attribute used to force alignment
323 * of critical RTEMS structures.  On some processors it may make
324 * sense to have these aligned on tighter boundaries than
325 * the minimum requirements of the compiler in order to have as
326 * much of the critical data area as possible in a cache line.
327 *
328 * The placement of this macro in the declaration of the variables
329 * is based on the syntactically requirements of the GNU C
330 * "__attribute__" extension.  For example with GNU C, use
331 * the following to force a structures to a 32 byte boundary.
332 *
333 *     __attribute__ ((aligned (32)))
334 *
335 * @note Currently only the Priority Bit Map table uses this feature.
336 *       To benefit from using this, the data must be heavily
337 *       used so it will stay in the cache and used frequently enough
338 *       in the executive to justify turning this on.
339 *
340 * Port Specific Information:
341 *
342 * XXX document implementation including references if appropriate
343 */
344#define CPU_STRUCTURE_ALIGNMENT
345
346#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
347
348/**
349 * @defgroup CPUEndian Processor Dependent Endianness Support
350 *
351 * This group assists in issues related to processor endianness.
352 *
353 */
354/**@{**/
355
356/**
357 * Define what is required to specify how the network to host conversion
358 * routines are handled.
359 *
360 * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
361 * same values.
362 *
363 * @see CPU_LITTLE_ENDIAN
364 *
365 * Port Specific Information:
366 *
367 * XXX document implementation including references if appropriate
368 */
369#define CPU_BIG_ENDIAN                           FALSE
370
371/**
372 * Define what is required to specify how the network to host conversion
373 * routines are handled.
374 *
375 * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
376 * same values.
377 *
378 * @see CPU_BIG_ENDIAN
379 *
380 * Port Specific Information:
381 *
382 * XXX document implementation including references if appropriate
383 */
384#define CPU_LITTLE_ENDIAN                        TRUE
385
386/** @} */
387
388/**
389 * @ingroup CPUInterrupt
390 * The following defines the number of bits actually used in the
391 * interrupt field of the task mode.  How those bits map to the
392 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
393 *
394 * Port Specific Information:
395 *
396 * XXX document implementation including references if appropriate
397 */
398#define CPU_MODES_INTERRUPT_MASK   0x00000001
399
400#define CPU_PER_CPU_CONTROL_SIZE 0
401
402/*
403 *  Processor defined structures required for cpukit/score.
404 *
405 *  Port Specific Information:
406 *
407 *  XXX document implementation including references if appropriate
408 */
409
410/* may need to put some structures here.  */
411
412#ifndef ASM
413
414typedef struct {
415  /* There is no CPU specific per-CPU state */
416} CPU_Per_CPU_control;
417
418/**
419 * @defgroup CPUContext Processor Dependent Context Management
420 *
421 * From the highest level viewpoint, there are 2 types of context to save.
422 *
423 *    -# Interrupt registers to save
424 *    -# Task level registers to save
425 *
426 * Since RTEMS handles integer and floating point contexts separately, this
427 * means we have the following 3 context items:
428 *
429 *    -# task level context stuff::  Context_Control
430 *    -# floating point task stuff:: Context_Control_fp
431 *    -# special interrupt level context :: CPU_Interrupt_frame
432 *
433 * On some processors, it is cost-effective to save only the callee
434 * preserved registers during a task context switch.  This means
435 * that the ISR code needs to save those registers which do not
436 * persist across function calls.  It is not mandatory to make this
437 * distinctions between the caller/callee saves registers for the
438 * purpose of minimizing context saved during task switch and on interrupts.
439 * If the cost of saving extra registers is minimal, simplicity is the
440 * choice.  Save the same context on interrupt entry as for tasks in
441 * this case.
442 *
443 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
444 * care should be used in designing the context area.
445 *
446 * On some CPUs with hardware floating point support, the Context_Control_fp
447 * structure will not be used or it simply consist of an array of a
448 * fixed number of bytes.   This is done when the floating point context
449 * is dumped by a "FP save context" type instruction and the format
450 * is not really defined by the CPU.  In this case, there is no need
451 * to figure out the exact format -- only the size.  Of course, although
452 * this is enough information for RTEMS, it is probably not enough for
453 * a debugger such as gdb.  But that is another problem.
454 *
455 * Port Specific Information:
456 *
457 * XXX document implementation including references if appropriate
458 */
459/**@{**/
460
461/**
462 * This defines the minimal set of integer and processor state registers
463 * that must be saved during a voluntary context switch from one thread
464 * to another.
465 */
466
467/* make sure this stays in sync with the assembly function
468   __CPU_Context_switch in cpu_asm.S  */
469typedef struct {
470    uint32_t   register_r4;
471    uint32_t   register_r5;
472    uint32_t   register_r6;
473    uint32_t   register_r7;
474
475    uint32_t   register_p3;
476    uint32_t   register_p4;
477    uint32_t   register_p5;
478    uint32_t   register_fp;
479    uint32_t   register_sp;
480
481    uint32_t   register_rets;
482
483    uint32_t   imask;
484} Context_Control;
485
486#define _CPU_Context_Get_SP( _context ) \
487  (_context)->register_sp
488
489/**
490 * This defines the complete set of floating point registers that must
491 * be saved during any context switch from one thread to another.
492 */
493typedef struct {
494    /* FPU registers are listed here */
495    /* Blackfin has no Floating Point */
496} Context_Control_fp;
497
498/**
499 * This defines the set of integer and processor state registers that must
500 * be saved during an interrupt.  This set does not include any which are
501 * in @ref Context_Control.
502 */
503typedef struct {
504    /** This field is a hint that a port will have a number of integer
505     * registers that need to be saved when an interrupt occurs or
506     * when a context switch occurs at the end of an ISR.
507     */
508    /*uint32_t   special_interrupt_register;*/
509} CPU_Interrupt_frame;
510
511/**
512 * This variable is optional.  It is used on CPUs on which it is difficult
513 * to generate an "uninitialized" FP context.  It is filled in by
514 * @ref _CPU_Initialize and copied into the task's FP context area during
515 * @ref _CPU_Context_Initialize.
516 *
517 * Port Specific Information:
518 *
519 * XXX document implementation including references if appropriate
520 */
521SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
522
523/** @} */
524
525/**
526 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
527 *
528 * On some CPUs, RTEMS supports a software managed interrupt stack.
529 * This stack is allocated by the Interrupt Manager and the switch
530 * is performed in @ref _ISR_Handler.  These variables contain pointers
531 * to the lowest and highest addresses in the chunk of memory allocated
532 * for the interrupt stack.  Since it is unknown whether the stack
533 * grows up or down (in general), this give the CPU dependent
534 * code the option of picking the version it wants to use.
535 *
536 * @note These two variables are required if the macro
537 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
538 *
539 * Port Specific Information:
540 *
541 * XXX document implementation including references if appropriate
542 */
543/**@{**/
544
545/*
546 *  Nothing prevents the porter from declaring more CPU specific variables.
547 *
548 *  Port Specific Information:
549 *
550 *  XXX document implementation including references if appropriate
551 */
552
553/* XXX: if needed, put more variables here */
554
555/**
556 * @ingroup CPUContext
557 * The size of the floating point context area.  On some CPUs this
558 * will not be a "sizeof" because the format of the floating point
559 * area is not defined -- only the size is.  This is usually on
560 * CPUs with a "floating point save context" instruction.
561 *
562 * Port Specific Information:
563 *
564 * XXX document implementation including references if appropriate
565 */
566#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
567
568#endif /* ASM */
569
570/**
571 * Amount of extra stack (above minimum stack size) required by
572 * MPCI receive server thread.  Remember that in a multiprocessor
573 * system this thread must exist and be able to process all directives.
574 *
575 * Port Specific Information:
576 *
577 * XXX document implementation including references if appropriate
578 */
579#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
580
581/**
582 * @ingroup CPUInterrupt
583 * This defines the number of entries in the @ref _ISR_Vector_table managed
584 * by RTEMS.
585 *
586 * Port Specific Information:
587 *
588 * XXX document implementation including references if appropriate
589 */
590#define CPU_INTERRUPT_NUMBER_OF_VECTORS      16
591
592/**
593 * @ingroup CPUInterrupt
594 * This defines the highest interrupt vector number for this port.
595 */
596#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
597
598/**
599 * @ingroup CPUInterrupt
600 * This is defined if the port has a special way to report the ISR nesting
601 * level.  Most ports maintain the variable @a _ISR_Nest_level.
602 */
603#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
604
605/** @} */
606
607/**
608 * @ingroup CPUContext
609 * Should be large enough to run all RTEMS tests.  This ensures
610 * that a "reasonable" small application should not have any problems.
611 *
612 * Port Specific Information:
613 *
614 * XXX document implementation including references if appropriate
615 */
616#define CPU_STACK_MINIMUM_SIZE          (1024*8)
617
618#define CPU_SIZEOF_POINTER 4
619
620/**
621 * CPU's worst alignment requirement for data types on a byte boundary.  This
622 * alignment does not take into account the requirements for the stack.
623 *
624 * Port Specific Information:
625 *
626 * XXX document implementation including references if appropriate
627 */
628#define CPU_ALIGNMENT              8
629
630/**
631 * This number corresponds to the byte alignment requirement for the
632 * heap handler.  This alignment requirement may be stricter than that
633 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
634 * common for the heap to follow the same alignment requirement as
635 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
636 * the heap, then this should be set to @ref CPU_ALIGNMENT.
637 *
638 * @note  This does not have to be a power of 2 although it should be
639 *        a multiple of 2 greater than or equal to 2.  The requirement
640 *        to be a multiple of 2 is because the heap uses the least
641 *        significant field of the front and back flags to indicate
642 *        that a block is in use or free.  So you do not want any odd
643 *        length blocks really putting length data in that bit.
644 *
645 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
646 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
647 *        elements allocated from the heap meet all restrictions.
648 *
649 * Port Specific Information:
650 *
651 * XXX document implementation including references if appropriate
652 */
653#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
654
655/**
656 * This number corresponds to the byte alignment requirement for memory
657 * buffers allocated by the partition manager.  This alignment requirement
658 * may be stricter than that for the data types alignment specified by
659 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
660 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
661 * strict enough for the partition, then this should be set to
662 * @ref CPU_ALIGNMENT.
663 *
664 * @note  This does not have to be a power of 2.  It does have to
665 *        be greater or equal to than @ref CPU_ALIGNMENT.
666 *
667 * Port Specific Information:
668 *
669 * XXX document implementation including references if appropriate
670 */
671#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
672
673/**
674 * This number corresponds to the byte alignment requirement for the
675 * stack.  This alignment requirement may be stricter than that for the
676 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
677 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
678 * set to 0.
679 *
680 * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
681 *
682 * Port Specific Information:
683 *
684 * XXX document implementation including references if appropriate
685 */
686#define CPU_STACK_ALIGNMENT        8
687
688/*
689 *  ISR handler macros
690 */
691
692/**
693 * @addtogroup CPUInterrupt
694 */
695/**@{**/
696
697/**
698 * Support routine to initialize the RTEMS vector table after it is allocated.
699 *
700 * Port Specific Information:
701 *
702 * XXX document implementation including references if appropriate
703 */
704#define _CPU_Initialize_vectors()
705
706/**
707 * Disable all interrupts for an RTEMS critical section.  The previous
708 * level is returned in @a _isr_cookie.
709 *
710 * @param[out] _isr_cookie will contain the previous level cookie
711 *
712 * Port Specific Information:
713 *
714 * XXX document implementation including references if appropriate
715 */
716#define _CPU_ISR_Disable( _level ) \
717  {                                     \
718       __asm__ volatile ("cli %0; csync \n" : "=d" (_level) );     \
719  }
720
721
722/**
723 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
724 * This indicates the end of an RTEMS critical section.  The parameter
725 * @a _isr_cookie is not modified.
726 *
727 * @param[in] _isr_cookie contain the previous level cookie
728 *
729 * Port Specific Information:
730 *
731 * XXX document implementation including references if appropriate
732 */
733#define _CPU_ISR_Enable( _level ) { \
734    __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) );   \
735  }
736
737/**
738 * This temporarily restores the interrupt to @a _isr_cookie before immediately
739 * disabling them again.  This is used to divide long RTEMS critical
740 * sections into two or more parts.  The parameter @a _isr_cookie is not
741 * modified.
742 *
743 * @param[in] _isr_cookie contain the previous level cookie
744 *
745 * Port Specific Information:
746 *
747 * XXX document implementation including references if appropriate
748 */
749#define _CPU_ISR_Flash( _level ) { \
750    __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
751                          : : "d"(_level) : "R0" ); \
752  }
753
754/**
755 * This routine and @ref _CPU_ISR_Get_level
756 * Map the interrupt level in task mode onto the hardware that the CPU
757 * actually provides.  Currently, interrupt levels which do not
758 * map onto the CPU in a generic fashion are undefined.  Someday,
759 * it would be nice if these were "mapped" by the application
760 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
761 * 8 - 255 would be available for bsp/application specific meaning.
762 * This could be used to manage a programmable interrupt controller
763 * via the rtems_task_mode directive.
764 *
765 * Port Specific Information:
766 *
767 * XXX document implementation including references if appropriate
768 */
769#define _CPU_ISR_Set_level( _new_level ) \
770  { \
771    __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
772  }
773
774#ifndef ASM
775
776/**
777 * Return the current interrupt disable level for this task in
778 * the format used by the interrupt level portion of the task mode.
779 *
780 * @note This routine usually must be implemented as a subroutine.
781 *
782 * Port Specific Information:
783 *
784 * XXX document implementation including references if appropriate
785 */
786uint32_t   _CPU_ISR_Get_level( void );
787
788/* end of ISR handler macros */
789
790/** @} */
791
792/* Context handler macros */
793
794/**
795 * @ingroup CPUContext
796 * Initialize the context to a state suitable for starting a
797 * task after a context restore operation.  Generally, this
798 * involves:
799 *
800 *    - setting a starting address
801 *    - preparing the stack
802 *    - preparing the stack and frame pointers
803 *    - setting the proper interrupt level in the context
804 *    - initializing the floating point context
805 *
806 * This routine generally does not set any unnecessary register
807 * in the context.  The state of the "general data" registers is
808 * undefined at task start time.
809 *
810 * @param[in] _the_context is the context structure to be initialized
811 * @param[in] _stack_base is the lowest physical address of this task's stack
812 * @param[in] _size is the size of this task's stack
813 * @param[in] _isr is the interrupt disable level
814 * @param[in] _entry_point is the thread's entry point.  This is
815 *        always @a _Thread_Handler
816 * @param[in] _is_fp is TRUE if the thread is to be a floating
817 *       point thread.  This is typically only used on CPUs where the
818 *       FPU may be easily disabled by software such as on the SPARC
819 *       where the PSR contains an enable FPU bit.
820 * @param[in] tls_area is the thread-local storage (TLS) area
821 *
822 * Port Specific Information:
823 *
824 * See implementation in cpu.c
825 */
826void _CPU_Context_Initialize(
827  Context_Control  *the_context,
828  uint32_t         *stack_base,
829  uint32_t          size,
830  uint32_t          new_level,
831  void             *entry_point,
832  bool              is_fp,
833  void             *tls_area
834);
835
836/**
837 * This routine is responsible for somehow restarting the currently
838 * executing task.  If you are lucky, then all that is necessary
839 * is restoring the context.  Otherwise, there will need to be
840 * a special assembly routine which does something special in this
841 * case.  For many ports, simply adding a label to the restore path
842 * of @ref _CPU_Context_switch will work.  On other ports, it may be
843 * possibly to load a few arguments and jump to the restore path. It will
844 * not work if restarting self conflicts with the stack frame
845 * assumptions of restoring a context.
846 *
847 * Port Specific Information:
848 *
849 * XXX document implementation including references if appropriate
850 */
851#define _CPU_Context_Restart_self( _the_context ) \
852   _CPU_Context_restore( (_the_context) );
853
854/**
855 * @ingroup CPUContext
856 * The purpose of this macro is to allow the initial pointer into
857 * a floating point context area (used to save the floating point
858 * context) to be at an arbitrary place in the floating point
859 * context area.
860 *
861 * This is necessary because some FP units are designed to have
862 * their context saved as a stack which grows into lower addresses.
863 * Other FP units can be saved by simply moving registers into offsets
864 * from the base of the context area.  Finally some FP units provide
865 * a "dump context" instruction which could fill in from high to low
866 * or low to high based on the whim of the CPU designers.
867 *
868 * @param[in] _base is the lowest physical address of the floating point
869 *        context area
870 * @param[in] _offset is the offset into the floating point area
871 *
872 * Port Specific Information:
873 *
874 * XXX document implementation including references if appropriate
875 */
876#define _CPU_Context_Fp_start( _base, _offset ) \
877   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
878
879/**
880 * This routine initializes the FP context area passed to it to.
881 * There are a few standard ways in which to initialize the
882 * floating point context.  The code included for this macro assumes
883 * that this is a CPU in which a "initial" FP context was saved into
884 * @a _CPU_Null_fp_context and it simply copies it to the destination
885 * context passed to it.
886 *
887 * Other floating point context save/restore models include:
888 *   -# not doing anything, and
889 *   -# putting a "null FP status word" in the correct place in the FP context.
890 *
891 * @param[in] _destination is the floating point context area
892 *
893 * Port Specific Information:
894 *
895 * XXX document implementation including references if appropriate
896 */
897#define _CPU_Context_Initialize_fp( _destination ) \
898  { \
899   *(*(_destination)) = _CPU_Null_fp_context; \
900  }
901
902/* end of Context handler macros */
903
904/* Fatal Error manager macros */
905
906/**
907 * This routine copies _error into a known place -- typically a stack
908 * location or a register, optionally disables interrupts, and
909 * halts/stops the CPU.
910 *
911 * Port Specific Information:
912 *
913 * XXX document implementation including references if appropriate
914 */
915#define _CPU_Fatal_halt( _source, _error ) \
916  { \
917    __asm__ volatile ( "cli R1; \
918                    R1 = %0; \
919                    _halt: \
920                    idle; \
921                    jump _halt;"\
922                    : : "r" (_error) ); \
923  }
924
925/* end of Fatal Error manager macros */
926
927/* Bitfield handler macros */
928
929/**
930 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
931 *
932 * This set of routines are used to implement fast searches for
933 * the most important ready task.
934 */
935/**@{**/
936
937/**
938 * This definition is set to TRUE if the port uses the generic bitfield
939 * manipulation implementation.
940 */
941#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
942
943/**
944 * This definition is set to TRUE if the port uses the data tables provided
945 * by the generic bitfield manipulation implementation.
946 * This can occur when actually using the generic bitfield manipulation
947 * implementation or when implementing the same algorithm in assembly
948 * language for improved performance.  It is unlikely that a port will use
949 * the data if it has a bitfield scan instruction.
950 */
951#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
952
953/**
954 * This routine sets @a _output to the bit number of the first bit
955 * set in @a _value.  @a _value is of CPU dependent type
956 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
957 * wide although only the 16 least significant bits will be used.
958 *
959 * There are a number of variables in using a "find first bit" type
960 * instruction.
961 *
962 *   -# What happens when run on a value of zero?
963 *   -# Bits may be numbered from MSB to LSB or vice-versa.
964 *   -# The numbering may be zero or one based.
965 *   -# The "find first bit" instruction may search from MSB or LSB.
966 *
967 * RTEMS guarantees that (1) will never happen so it is not a concern.
968 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
969 * @ref _CPU_Priority_bits_index.  These three form a set of routines
970 * which must logically operate together.  Bits in the _value are
971 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
972 * The basic major and minor values calculated by @ref _Priority_Major
973 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
974 * to properly range between the values returned by the "find first bit"
975 * instruction.  This makes it possible for @ref _Priority_Get_highest to
976 * calculate the major and directly index into the minor table.
977 * This mapping is necessary to ensure that 0 (a high priority major/minor)
978 * is the first bit found.
979 *
980 * This entire "find first bit" and mapping process depends heavily
981 * on the manner in which a priority is broken into a major and minor
982 * components with the major being the 4 MSB of a priority and minor
983 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
984 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
985 * to the lowest priority.
986 *
987 * If your CPU does not have a "find first bit" instruction, then
988 * there are ways to make do without it.  Here are a handful of ways
989 * to implement this in software:
990 *
991@verbatim
992      - a series of 16 bit test instructions
993      - a "binary search using if's"
994      - _number = 0
995        if _value > 0x00ff
996          _value >>=8
997          _number = 8;
998
999        if _value > 0x0000f
1000          _value >=8
1001          _number += 4
1002
1003        _number += bit_set_table[ _value ]
1004@endverbatim
1005
1006 *   where bit_set_table[ 16 ] has values which indicate the first
1007 *     bit set
1008 *
1009 * @param[in] _value is the value to be scanned
1010 * @param[in] _output is the first bit set
1011 *
1012 * Port Specific Information:
1013 *
1014 * XXX document implementation including references if appropriate
1015 */
1016
1017#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1018#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1019  { \
1020    __asm__ ("bit(1);"):
1021    (_output) = 0;   /* do something to prevent warnings */ \
1022  }
1023#endif
1024
1025/* end of Bitfield handler macros */
1026
1027/** @} */
1028
1029/**
1030 * This routine builds the mask which corresponds to the bit fields
1031 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1032 * for that routine.
1033 *
1034 * Port Specific Information:
1035 *
1036 * XXX document implementation including references if appropriate
1037 */
1038#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1039
1040#define _CPU_Priority_Mask( _bit_number ) \
1041  ( 1 << (_bit_number) )
1042
1043#endif
1044
1045/**
1046 * @ingroup CPUBitfield
1047 * This routine translates the bit numbers returned by
1048 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1049 * a major or minor component of a priority.  See the discussion
1050 * for that routine.
1051 *
1052 * @param[in] _priority is the major or minor number to translate
1053 *
1054 * Port Specific Information:
1055 *
1056 * XXX document implementation including references if appropriate
1057 */
1058#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1059
1060#define _CPU_Priority_bits_index( _priority ) \
1061  (_priority)
1062
1063#endif
1064
1065/* end of Priority handler macros */
1066
1067/* functions */
1068
1069/**
1070 * @brief CPU initialize.
1071 * This routine performs CPU dependent initialization.
1072 *
1073 * Port Specific Information:
1074 *
1075 * XXX document implementation including references if appropriate
1076 */
1077void _CPU_Initialize(void);
1078
1079/**
1080 * @ingroup CPUInterrupt
1081 * This routine installs a "raw" interrupt handler directly into the
1082 * processor's vector table.
1083 *
1084 * @param[in] vector is the vector number
1085 * @param[in] new_handler is the raw ISR handler to install
1086 * @param[in] old_handler is the previously installed ISR Handler
1087 *
1088 * Port Specific Information:
1089 *
1090 * XXX document implementation including references if appropriate
1091 */
1092void _CPU_ISR_install_raw_handler(
1093  uint32_t    vector,
1094  proc_ptr    new_handler,
1095  proc_ptr   *old_handler
1096);
1097
1098/**
1099 * @ingroup CPUInterrupt
1100 * This routine installs an interrupt vector.
1101 *
1102 * @param[in] vector is the vector number
1103 * @param[in] new_handler is the RTEMS ISR handler to install
1104 * @param[in] old_handler is the previously installed ISR Handler
1105 *
1106 * Port Specific Information:
1107 *
1108 * XXX document implementation including references if appropriate
1109 */
1110void _CPU_ISR_install_vector(
1111  uint32_t    vector,
1112  proc_ptr    new_handler,
1113  proc_ptr   *old_handler
1114);
1115
1116/**
1117 * @ingroup CPUInterrupt
1118 * This routine installs the hardware interrupt stack pointer.
1119 *
1120 * @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1121 *        is TRUE.
1122 *
1123 * Port Specific Information:
1124 *
1125 * XXX document implementation including references if appropriate
1126 */
1127void _CPU_Install_interrupt_stack( void );
1128
1129/**
1130 * This routine is the CPU dependent IDLE thread body.
1131 *
1132 * @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1133 *        is TRUE.
1134 *
1135 * Port Specific Information:
1136 *
1137 * XXX document implementation including references if appropriate
1138 */
1139void *_CPU_Thread_Idle_body( uintptr_t ignored );
1140
1141/**
1142 * @addtogroup CPUContext
1143 */
1144/**@{**/
1145
1146/**
1147 * This routine switches from the run context to the heir context.
1148 *
1149 * @param[in] run points to the context of the currently executing task
1150 * @param[in] heir points to the context of the heir task
1151 *
1152 * Port Specific Information:
1153 *
1154 * XXX document implementation including references if appropriate
1155 */
1156void _CPU_Context_switch(
1157  Context_Control  *run,
1158  Context_Control  *heir
1159);
1160
1161/**
1162 * This routine is generally used only to restart self in an
1163 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1164 *
1165 * @param[in] new_context points to the context to be restored.
1166 *
1167 * @note May be unnecessary to reload some registers.
1168 *
1169 * Port Specific Information:
1170 *
1171 * XXX document implementation including references if appropriate
1172 */
1173void _CPU_Context_restore(
1174  Context_Control *new_context
1175) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1176
1177/**
1178 * This routine saves the floating point context passed to it.
1179 *
1180 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1181 * point context area
1182 *
1183 * @return on output @a *fp_context_ptr will contain the address that
1184 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1185 *
1186 * Port Specific Information:
1187 *
1188 * XXX document implementation including references if appropriate
1189 */
1190void _CPU_Context_save_fp(
1191  Context_Control_fp **fp_context_ptr
1192);
1193
1194/**
1195 * This routine restores the floating point context passed to it.
1196 *
1197 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1198 * point context area to restore
1199 *
1200 * @return on output @a *fp_context_ptr will contain the address that
1201 * should be used with @ref _CPU_Context_save_fp to save this context.
1202 *
1203 * Port Specific Information:
1204 *
1205 * XXX document implementation including references if appropriate
1206 */
1207void _CPU_Context_restore_fp(
1208  Context_Control_fp **fp_context_ptr
1209);
1210
1211static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1212{
1213  /* TODO */
1214}
1215
1216static inline void _CPU_Context_validate( uintptr_t pattern )
1217{
1218  while (1) {
1219    /* TODO */
1220  }
1221}
1222
1223/** @} */
1224
1225/* FIXME */
1226typedef CPU_Interrupt_frame CPU_Exception_frame;
1227
1228void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1229
1230/**
1231 * @ingroup CPUEndian
1232 * The following routine swaps the endian format of an unsigned int.
1233 * It must be static because it is referenced indirectly.
1234 *
1235 * This version will work on any processor, but if there is a better
1236 * way for your CPU PLEASE use it.  The most common way to do this is to:
1237 *
1238 *    swap least significant two bytes with 16-bit rotate
1239 *    swap upper and lower 16-bits
1240 *    swap most significant two bytes with 16-bit rotate
1241 *
1242 * Some CPUs have special instructions which swap a 32-bit quantity in
1243 * a single instruction (e.g. i486).  It is probably best to avoid
1244 * an "endian swapping control bit" in the CPU.  One good reason is
1245 * that interrupts would probably have to be disabled to ensure that
1246 * an interrupt does not try to access the same "chunk" with the wrong
1247 * endian.  Another good reason is that on some CPUs, the endian bit
1248 * endianness for ALL fetches -- both code and data -- so the code
1249 * will be fetched incorrectly.
1250 *
1251 * @param[in] value is the value to be swapped
1252 * @return the value after being endian swapped
1253 *
1254 * Port Specific Information:
1255 *
1256 * XXX document implementation including references if appropriate
1257 */
1258static inline uint32_t CPU_swap_u32(
1259  uint32_t value
1260)
1261{
1262  uint32_t   byte1, byte2, byte3, byte4, swapped;
1263
1264  byte4 = (value >> 24) & 0xff;
1265  byte3 = (value >> 16) & 0xff;
1266  byte2 = (value >> 8)  & 0xff;
1267  byte1 =  value        & 0xff;
1268
1269  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1270  return( swapped );
1271}
1272
1273/**
1274 * @ingroup CPUEndian
1275 * This routine swaps a 16 bir quantity.
1276 *
1277 * @param[in] value is the value to be swapped
1278 * @return the value after being endian swapped
1279 */
1280#define CPU_swap_u16( value ) \
1281  (((value&0xff) << 8) | ((value >> 8)&0xff))
1282
1283typedef uint32_t CPU_Counter_ticks;
1284
1285CPU_Counter_ticks _CPU_Counter_read( void );
1286
1287static inline CPU_Counter_ticks _CPU_Counter_difference(
1288  CPU_Counter_ticks second,
1289  CPU_Counter_ticks first
1290)
1291{
1292  return second - first;
1293}
1294
1295#endif /* ASM */
1296
1297#ifdef __cplusplus
1298}
1299#endif
1300
1301#endif
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